# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Cheng:2009:DSE
author: Chung-Kuan Cheng
title: Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders
crossref: Bruguera:2009:PIS
pages: 212--212
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
remark: Only abstract published.
acknowledgement: ack-nhfb
rawauthor: Chung-Kuan Cheng
rawtitle: Design Space Exploration for Power-Efficient Mixed-Radix {Ling} Adders
abstract:
We present an integer linear programming (ILP) method that optimizes generalized prefix Ling adders in terms of area, delay, and power. The contribution is listed in the following.par (1) We devise an ILP formulation based on logical effort models so that we can use ILP solver, CPLEX, to produce minimum power solutions with given structural, area and timing constraints. The formulation allows the adjustment of parameters and constraints, e.g. the radix numbers and the ratio of static and dynamic power. We implement the flow for the users to automatically synthesize the adders.par (2) We engineer sets of integer decision variables and linear constraints to depict the prefix topology, signal delay, and power characterization. Since the design space of prefix adders is large, optimal solutions are usually hard to generate without good formulations. We generate redundant constraints to prune the search space. The approach significantly reduces the execution time.par (3) We explore mixed radices for prefix topologies, i.e. GP cells have radices 2, 3, or 4, and a prefix network can contain cells of different radices. This mixed-radix feature expands the design space for better solutions. High-radix adders reduce logic levels and thus can serve for high performance applications. On the other hand, high-radix cells take more logical effort, longer parasitic delay, and more power consumption. These factors are all taken care of in the devised ILP formulation.par (4) We adopt the structure of Ling adders to produce faster sum and carry responses. The experiments show that Ling adders achieve better results than normal prefix adders.par (5) We apply hierarchical design methods to handle high bit-width modules. One weakness of ILP solver is the scaleability of computational time with the bit-width. We use a divide-and-conquer strategy to synthesize 64-bit adders.

rawabstract:
We present an integer linear programming (ILP) method that optimizes generalized prefix Ling adders in terms of area, delay, and power. The contribution is listed in the following.\par (1) We devise an ILP formulation based on logical effort models so that we can use ILP solver, CPLEX, to produce minimum power solutions with given structural, area and timing constraints. The formulation allows the adjustment of parameters and constraints, e.g. the radix numbers and the ratio of static and dynamic power. We implement the flow for the users to automatically synthesize the adders.\par (2) We engineer sets of integer decision variables and linear constraints to depict the prefix topology, signal delay, and power characterization. Since the design space of prefix adders is large, optimal solutions are usually hard to generate without good formulations. We generate redundant constraints to prune the search space. The approach significantly reduces the execution time.\par (3) We explore mixed radices for prefix topologies, i.e. GP cells have radices 2, 3, or 4, and a prefix network can contain cells of different radices. This mixed-radix feature expands the design space for better solutions. High-radix adders reduce logic levels and thus can serve for high performance applications. On the other hand, high-radix cells take more logical effort, longer parasitic delay, and more power consumption. These factors are all taken care of in the devised ILP formulation.\par (4) We adopt the structure of Ling adders to produce faster sum and carry responses. The experiments show that Ling adders achieve better results than normal prefix adders.\par (5) We apply hierarchical design methods to handle high bit-width modules. One weakness of ILP solver is the scaleability of computational time with the bit-width. We use a divide-and-conquer strategy to synthesize 64-bit adders.

entry:
@InProceedings{Cheng:2009:DSE,
  author =       "Chung-Kuan Cheng",
  title =        "Design Space Exploration for Power-Efficient
                 Mixed-Radix {Ling} Adders",
  crossref =     "Bruguera:2009:PIS",
  pages =        "212--212",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present an integer linear programming (ILP) method
                 that optimizes generalized prefix Ling adders in terms
                 of area, delay, and power. The contribution is listed
                 in the following.\par

                 (1) We devise an ILP formulation based on logical
                 effort models so that we can use ILP solver, CPLEX, to
                 produce minimum power solutions with given structural,
                 area and timing constraints. The formulation allows the
                 adjustment of parameters and constraints, e.g. the
                 radix numbers and the ratio of static and dynamic
                 power. We implement the flow for the users to
                 automatically synthesize the adders.\par

                 (2) We engineer sets of integer decision variables and
                 linear constraints to depict the prefix topology,
                 signal delay, and power characterization. Since the
                 design space of prefix adders is large, optimal
                 solutions are usually hard to generate without good
                 formulations. We generate redundant constraints to
                 prune the search space. The approach significantly
                 reduces the execution time.\par

                 (3) We explore mixed radices for prefix topologies,
                 i.e. GP cells have radices 2, 3, or 4, and a prefix
                 network can contain cells of different radices. This
                 mixed-radix feature expands the design space for better
                 solutions. High-radix adders reduce logic levels and
                 thus can serve for high performance applications. On
                 the other hand, high-radix cells take more logical
                 effort, longer parasitic delay, and more power
                 consumption. These factors are all taken care of in the
                 devised ILP formulation.\par

                 (4) We adopt the structure of Ling adders to produce
                 faster sum and carry responses. The experiments show
                 that Ling adders achieve better results than normal
                 prefix adders.\par

                 (5) We apply hierarchical design methods to handle high
                 bit-width modules. One weakness of ILP solver is the
                 scaleability of computational time with the bit-width.
                 We use a divide-and-conquer strategy to synthesize
                 64-bit adders.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
  remark =       "Only abstract published.",
}


bibtype: inproceedings
filename: fparith.bib
label: Chevillard:2009:CFC
author: Sylvain Chevillard and Mioara Joldes and Christoph Lauter
title: Certified and Fast Computation of Supremum Norms of Approximation Errors
crossref: Bruguera:2009:PIS
pages: 169--176
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
acknowledgement: ack-nhfb
rawauthor: Sylvain Chevillard and Mioara Joldes and Christoph Lauter
rawtitle: Certified and Fast Computation of Supremum Norms of Approximation Errors
abstract:
In many numerical programs there is a need for a high-quality floating-point approximation of useful functions $f$, such as such as $ exp $, $ sin $, $ erf $. In the actual implementation, the function is replaced by a polynomial $p$, which leads to an approximation error (absolute or relative) $ epsilon = p - f $ or $ epsilon = p / f - 1 $. The tight yet certain bounding of this error is an important step towards safe implementations. The problem is difficult mainly because that approximation error is very small and the difference $ p - f $ is subject to high cancellation. Previous approaches for computing the supremum norm in this degenerate case, have proven to be unsafe, not sufficiently tight or too tedious in manual work. We present a safe and fast algorithm that computes a tight lower and upper bound for the supremum norms of approximation errors. The algorithm is based on a combination of several techniques, including enhanced interval arithmetic, automatic differentiation and isolation of the roots of a polynomial. We have implemented our algorithm and give timings on several examples.

keywords:
approximation error; ARITH-19; automatic/algorithmic differentiation; certified computation; elementary function; interval arithmetic; roots isolation technique.; supremum/infinity norm

rawabstract:
In many numerical programs there is a need for a high-quality floating-point approximation of useful functions $f$, such as such as $ \exp $, $ \sin $, $ \erf $. In the actual implementation, the function is replaced by a polynomial $p$, which leads to an approximation error (absolute or relative) $ \epsilon = p - f $ or $ \epsilon = p / f - 1 $. The tight yet certain bounding of this error is an important step towards safe implementations. The problem is difficult mainly because that approximation error is very small and the difference $ p - f $ is subject to high cancellation. Previous approaches for computing the supremum norm in this degenerate case, have proven to be unsafe, not sufficiently tight or too tedious in manual work. We present a safe and fast algorithm that computes a tight lower and upper bound for the supremum norms of approximation errors. The algorithm is based on a combination of several techniques, including enhanced interval arithmetic, automatic differentiation and isolation of the roots of a polynomial. We have implemented our algorithm and give timings on several examples.

entry:
@InProceedings{Chevillard:2009:CFC,
  author =       "Sylvain Chevillard and Mioara Joldes and Christoph
                 Lauter",
  title =        "Certified and Fast Computation of Supremum Norms of
                 Approximation Errors",
  crossref =     "Bruguera:2009:PIS",
  pages =        "169--176",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In many numerical programs there is a need for a
                 high-quality floating-point approximation of useful
                 functions $f$, such as such as $ \exp $, $ \sin $, $
                 \erf $. In the actual implementation, the function is
                 replaced by a polynomial $p$, which leads to an
                 approximation error (absolute or relative) $ \epsilon =
                 p - f $ or $ \epsilon = p / f - 1 $. The tight yet
                 certain bounding of this error is an important step
                 towards safe implementations. The problem is difficult
                 mainly because that approximation error is very small
                 and the difference $ p - f $ is subject to high
                 cancellation. Previous approaches for computing the
                 supremum norm in this degenerate case, have proven to
                 be unsafe, not sufficiently tight or too tedious in
                 manual work. We present a safe and fast algorithm that
                 computes a tight lower and upper bound for the supremum
                 norms of approximation errors. The algorithm is based
                 on a combination of several techniques, including
                 enhanced interval arithmetic, automatic differentiation
                 and isolation of the roots of a polynomial. We have
                 implemented our algorithm and give timings on several
                 examples.",
  acknowledgement = ack-nhfb,
  keywords =     "approximation error; ARITH-19; automatic/algorithmic
                 differentiation; certified computation; elementary
                 function; interval arithmetic; roots isolation
                 technique.; supremum/infinity norm",
}


bibtype: article
filename: fparith.bib
label: Cho:2009:AMD
author: H. Cho and E. E. Swartzlander
title: Adder and Multiplier Design in Quantum-Dot Cellular Automata
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 6
pages: 721--727
month: jun
monthnumber: 6
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2009.21
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:41 MDT 2011
bibtimestamp: 2011.07.04 11:37:41 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4760137
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Cho and E. E. Swartzlander
rawtitle: Adder and Multiplier Design in Quantum-Dot Cellular Automata
entry:
@Article{Cho:2009:AMD,
  author =       "H. Cho and E. E. Swartzlander",
  title =        "Adder and Multiplier Design in Quantum-Dot Cellular
                 Automata",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "6",
  pages =        "721--727",
  month =        jun,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2009.21",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:41 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4760137",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Chouliaras:2009:CLF
author: V. A. Chouliaras and K. Manolopoulos and D. Reisis
title: A configurable length, Fused Multiply-Add floating point unit for a VLIW processor
crossref: Sezer:2009:IIS
pages: 93--96
year: 2009
DOI: https://doi.org/10.1109/SOCCON.2009.5398088
bibdate: Sun Feb 20 10:03:30 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.20 10:03:30 ???
acknowledgement: ack-nhfb
rawauthor: V. A. Chouliaras and K. Manolopoulos and D. Reisis
rawtitle: A configurable length, Fused Multiply-Add floating point unit for a {VLIW} processor
abstract:
The efficiency of fused multiply add units plays a key role in the processor's performance for a variety of applications. A design keeping the advantages of the FMA regarding the latency and the hardware utilization and also improving the result's accuracy in both normalized and denormalized numbers is the subject of this work. The FMA unit has configurable latency and it is integrated in a VLIW processor. The VLSI TSMC 0.13 implementation achieved an operating frequency of 232.6 MHz and a final post-routed area of 121900.478 $ mu $ m$^2$.

rawabstract:
The efficiency of fused multiply add units plays a key role in the processor's performance for a variety of applications. A design keeping the advantages of the FMA regarding the latency and the hardware utilization and also improving the result's accuracy in both normalized and denormalized numbers is the subject of this work. The FMA unit has configurable latency and it is integrated in a VLIW processor. The VLSI TSMC 0.13 implementation achieved an operating frequency of 232.6 MHz and a final post-routed area of 121900.478 $ \mu $ m$^2$.

entry:
@InProceedings{Chouliaras:2009:CLF,
  author =       "V. A. Chouliaras and K. Manolopoulos and D. Reisis",
  title =        "A configurable length, Fused Multiply-Add floating
                 point unit for a {VLIW} processor",
  crossref =     "Sezer:2009:IIS",
  pages =        "93--96",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/SOCCON.2009.5398088",
  bibdate =      "Sun Feb 20 10:03:30 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The efficiency of fused multiply add units plays a key
                 role in the processor's performance for a variety of
                 applications. A design keeping the advantages of the
                 FMA regarding the latency and the hardware utilization
                 and also improving the result's accuracy in both
                 normalized and denormalized numbers is the subject of
                 this work. The FMA unit has configurable latency and it
                 is integrated in a VLIW processor. The VLSI TSMC 0.13
                 implementation achieved an operating frequency of 232.6
                 MHz and a final post-routed area of 121900.478 $ \mu $
                 m$^2$.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Cilardo:2009:EBP
author: A. Cilardo
title: Efficient Bit-Parallel $ mathrm GF(2^m) $ Multiplier for a Large Class of Irreducible Pentanomials
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 7
pages: 1001--1008
month: jul
monthnumber: 7
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2009.16
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:42 MDT 2011
bibtimestamp: 2011.07.04 11:37:42 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4752811
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Cilardo
rawtitle:
Efficient Bit-Parallel {$ \mathrm {GF}(2^m) $} Multiplier for a Large Class of Irreducible Pentanomials

entry:
@Article{Cilardo:2009:EBP,
  author =       "A. Cilardo",
  title =        "Efficient Bit-Parallel {$ \mathrm {GF}(2^m) $}
                 Multiplier for a Large Class of Irreducible
                 Pentanomials",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "7",
  pages =        "1001--1008",
  month =        jul,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2009.16",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:42 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4752811",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Colberg:2009:HAS
author: Peter H. Colberg and Felix Hofling
journal: arXiv.org
pages: 1--12
day: 20
month: dec
monthnumber: 12
year: 2009
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
note: Published in Comp. Phys. Comm. bf 182, 1120 (2011).
URL: http://arxiv.org/abs/0912.3824
acknowledgement: ack-nhfb
rawauthor: Peter H. Colberg and Felix H{\"o}fling
rawnote: Published in Comp. Phys. Comm. {\bf 182}, 1120 (2011).
title:
Highly accelerated simulations of glassy dynamics using GPUs: caveats on limited floating-point precision

abstract:
Modern graphics processing units (GPUs) provide impressive computing resources, which can be accessed conveniently through the CUDA programming interface. We describe how GPUs can be used to considerably speed up molecular dynamics (MD) simulations for system sizes ranging up to about 1 million particles. Particular emphasis is put on the numerical long-time stability in terms of energy and momentum conservation, and caveats on limited floating-point precision are issued. Strict energy conservation over $ 10^8 $ MD steps is obtained by double-single emulation of the floating-point arithmetic in accuracy-critical parts of the algorithm. For the slow dynamics of a supercooled binary Lennard-Jones mixture, we demonstrate that the use of single-floating point precision may result in quantitatively and even physically wrong results. For simulations of a Lennard-Jones fluid, the described implementation shows speedup factors of up to 80 compared to a serial implementation for the CPU, and a single GPU was found to compare with a parallelised MD simulation using 64 distributed cores.

subject:
Computational Physics (physics.comp-ph); Soft Condensed Matter (cond-mat.soft); Distributed, Parallel, and Cluster Computing (cs.DC)

rawabstract:
Modern graphics processing units (GPUs) provide impressive computing resources, which can be accessed conveniently through the CUDA programming interface. We describe how GPUs can be used to considerably speed up molecular dynamics (MD) simulations for system sizes ranging up to about 1 million particles. Particular emphasis is put on the numerical long-time stability in terms of energy and momentum conservation, and caveats on limited floating-point precision are issued. Strict energy conservation over $ 10^8 $ MD steps is obtained by double-single emulation of the floating-point arithmetic in accuracy-critical parts of the algorithm. For the slow dynamics of a supercooled binary Lennard-Jones mixture, we demonstrate that the use of single-floating point precision may result in quantitatively and even physically wrong results. For simulations of a Lennard-Jones fluid, the described implementation shows speedup factors of up to 80 compared to a serial implementation for the CPU, and a single GPU was found to compare with a parallelised MD simulation using 64 distributed cores.

rawtitle:
Highly accelerated simulations of glassy dynamics using {GPUs}: caveats on limited floating-point precision

entry:
@Article{Colberg:2009:HAS,
  author =       "Peter H. Colberg and Felix H{\"o}fling",
  title =        "Highly accelerated simulations of glassy dynamics
                 using {GPUs}: caveats on limited floating-point
                 precision",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--12",
  day =          "20",
  month =        dec,
  year =         "2009",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Published in Comp. Phys. Comm. {\bf 182}, 1120
                 (2011).",
  URL =          "http://arxiv.org/abs/0912.3824",
  abstract =     "Modern graphics processing units (GPUs) provide
                 impressive computing resources, which can be accessed
                 conveniently through the CUDA programming interface. We
                 describe how GPUs can be used to considerably speed up
                 molecular dynamics (MD) simulations for system sizes
                 ranging up to about 1 million particles. Particular
                 emphasis is put on the numerical long-time stability in
                 terms of energy and momentum conservation, and caveats
                 on limited floating-point precision are issued. Strict
                 energy conservation over $ 10^8 $ MD steps is obtained
                 by double-single emulation of the floating-point
                 arithmetic in accuracy-critical parts of the algorithm.
                 For the slow dynamics of a supercooled binary
                 Lennard-Jones mixture, we demonstrate that the use of
                 single-floating point precision may result in
                 quantitatively and even physically wrong results. For
                 simulations of a Lennard-Jones fluid, the described
                 implementation shows speedup factors of up to 80
                 compared to a serial implementation for the CPU, and a
                 single GPU was found to compare with a parallelised MD
                 simulation using 64 distributed cores.",
  acknowledgement = ack-nhfb,
  subject =      "Computational Physics (physics.comp-ph); Soft
                 Condensed Matter (cond-mat.soft); Distributed,
                 Parallel, and Cluster Computing (cs.DC)",
}


bibtype: inproceedings
filename: fparith.bib
label: Cornea:2009:IDF
author: Marius Cornea
title: IEEE 754-2008 Decimal Floating-Point for Intel Architecture Processors
crossref: Bruguera:2009:PIS
pages: 225--228
year: 2009
DOI: https://doi.org/10.1109/ARITH.2009.35
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: Marius Cornea
rawtitle: {IEEE 754-2008} Decimal Floating-Point for {Intel} Architecture Processors
abstract:
A brief description is provided of the decimal floating-point support available for Intel Architecture processors, compliant with the IEEE Standard 754-2008 for Floating-Point Arithmetic [1]. Some performance results are included.

rawabstract:
A brief description is provided of the decimal floating-point support available for Intel Architecture processors, compliant with the IEEE Standard 754-2008 for Floating-Point Arithmetic [1]. Some performance results are included.

entry:
@InProceedings{Cornea:2009:IDF,
  author =       "Marius Cornea",
  title =        "{IEEE 754-2008} Decimal Floating-Point for {Intel}
                 Architecture Processors",
  crossref =     "Bruguera:2009:PIS",
  pages =        "225--228",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ARITH.2009.35",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A brief description is provided of the decimal
                 floating-point support available for Intel Architecture
                 processors, compliant with the IEEE Standard 754-2008
                 for Floating-Point Arithmetic [1]. Some performance
                 results are included.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: article
filename: fparith.bib
label: Cornea:2009:SII
author: M. Cornea and J. Harrison and C. Anderson and P. Tang and E. Schneider and E. Gvozdev
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 2
pages: 148--162
month: feb
monthnumber: 2
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.209
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:39 MDT 2011
bibtimestamp: 2011.07.04 11:37:39 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4674342
fjournal: IEEE Transactions on Computers
remark: Extended version of ARITH-18 article cite Cornea:2007:SII.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. Cornea and J. Harrison and C. Anderson and P. Tang and E. Schneider and E. Gvozdev
title:
A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format

abstract:
The IEEE Standard 754-1985 for Binary Floating-Point Arithmetic [19] was revised [20], and an important addition is the definition of decimal floating-point arithmetic [8], [24]. This is intended mainly to provide a robust reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic may introduce small but unacceptable errors. Using binary floating-point calculations to emulate decimal calculations in order to correct this issue has led to the existence of numerous proprietary software packages, each with its own characteristics and capabilities. The IEEE 754R decimal arithmetic should unify the ways decimal floating-point calculations are carried out on various platforms. New algorithms and properties are presented in this paper, which are used in a software implementation of the IEEE 754R decimal floating-point arithmetic, with emphasis on using binary operations efficiently. The focus is on rounding techniques for decimal values stored in binary format, but algorithms are outlined for the more important or interesting operations of addition, multiplication, and division, including the case of nonhomogeneous operands, as well as conversions between binary and decimal floating-point formats. Performance results are included for a wider range of operations, showing promise that our approach is viable for applications that require decimal floating-point calculations. This paper extends an earlier publication [6].

keywords:
binary-decimal conversion.; computer arithmetic; correct rounding; decimal floating-point; floating-point arithmetic; multiple-precision arithmetic

rawabstract:
The IEEE Standard 754-1985 for Binary Floating-Point Arithmetic [19] was revised [20], and an important addition is the definition of decimal floating-point arithmetic [8], [24]. This is intended mainly to provide a robust reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic may introduce small but unacceptable errors. Using binary floating-point calculations to emulate decimal calculations in order to correct this issue has led to the existence of numerous proprietary software packages, each with its own characteristics and capabilities. The IEEE 754R decimal arithmetic should unify the ways decimal floating-point calculations are carried out on various platforms. New algorithms and properties are presented in this paper, which are used in a software implementation of the IEEE 754R decimal floating-point arithmetic, with emphasis on using binary operations efficiently. The focus is on rounding techniques for decimal values stored in binary format, but algorithms are outlined for the more important or interesting operations of addition, multiplication, and division, including the case of nonhomogeneous operands, as well as conversions between binary and decimal floating-point formats. Performance results are included for a wider range of operations, showing promise that our approach is viable for applications that require decimal floating-point calculations. This paper extends an earlier publication [6].

rawtitle:
A Software Implementation of the {IEEE 754R} Decimal Floating-Point Arithmetic Using the Binary Encoding Format

entry:
@Article{Cornea:2009:SII,
  author =       "M. Cornea and J. Harrison and C. Anderson and P. Tang
                 and E. Schneider and E. Gvozdev",
  title =        "A Software Implementation of the {IEEE 754R} Decimal
                 Floating-Point Arithmetic Using the Binary Encoding
                 Format",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "2",
  pages =        "148--162",
  month =        feb,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.209",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4674342",
  abstract =     "The IEEE Standard 754-1985 for Binary Floating-Point
                 Arithmetic [19] was revised [20], and an important
                 addition is the definition of decimal floating-point
                 arithmetic [8], [24]. This is intended mainly to
                 provide a robust reliable framework for financial
                 applications that are often subject to legal
                 requirements concerning rounding and precision of the
                 results, because the binary floating-point arithmetic
                 may introduce small but unacceptable errors. Using
                 binary floating-point calculations to emulate decimal
                 calculations in order to correct this issue has led to
                 the existence of numerous proprietary software
                 packages, each with its own characteristics and
                 capabilities. The IEEE 754R decimal arithmetic should
                 unify the ways decimal floating-point calculations are
                 carried out on various platforms. New algorithms and
                 properties are presented in this paper, which are used
                 in a software implementation of the IEEE 754R decimal
                 floating-point arithmetic, with emphasis on using
                 binary operations efficiently. The focus is on rounding
                 techniques for decimal values stored in binary format,
                 but algorithms are outlined for the more important or
                 interesting operations of addition, multiplication, and
                 division, including the case of nonhomogeneous
                 operands, as well as conversions between binary and
                 decimal floating-point formats. Performance results are
                 included for a wider range of operations, showing
                 promise that our approach is viable for applications
                 that require decimal floating-point calculations. This
                 paper extends an earlier publication [6].",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "binary-decimal conversion.; computer arithmetic;
                 correct rounding; decimal floating-point;
                 floating-point arithmetic; multiple-precision
                 arithmetic",
  remark =       "Extended version of ARITH-18 article
                 \cite{Cornea:2007:SII}.",
}


bibtype: article
filename: fparith.bib
label: Csuros:2009:ACF
author: Miklos Csuros
title: Approximate counting with a floating-point counter
journal: arXiv.org
pages: ??--??
day: 20
month: apr
monthnumber: 4
year: 2009
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/0904.3062
subject: Data Structures and Algorithms (cs.DS)
acknowledgement: ack-nhfb
rawauthor: Miklos Csuros
rawtitle: Approximate counting with a floating-point counter
abstract:
Memory becomes a limiting factor in contemporary applications, such as analyses of the Webgraph and molecular sequences, when many objects need to be counted simultaneously. Robert Morris [Communications of the ACM, 21:840--842, 1978] proposed a probabilistic technique for approximate counting that is extremely space-efficient. The basic idea is to increment a counter containing the value $X$ with probability $ 2^-X$. As a result, the counter contains an approximation of $ lg n$ after $n$ probabilistic updates stored in $ lg lg n$ bits. Here we revisit the original idea of Morris, and introduce a binary floating-point counter that uses a $d$-bit significand in conjunction with a binary exponent. The counter yields a simple formula for an unbiased estimation of $n$ with a standard deviation of about $ 0.6 cdot n2^-d / 2$, and uses $ d + lg lg n$ bits. We analyze the floating-point counter's performance in a general framework that applies to any probabilistic counter, and derive practical formulas to assess its accuracy.

rawabstract:
Memory becomes a limiting factor in contemporary applications, such as analyses of the Webgraph and molecular sequences, when many objects need to be counted simultaneously. Robert Morris [Communications of the ACM, 21:840--842, 1978] proposed a probabilistic technique for approximate counting that is extremely space-efficient. The basic idea is to increment a counter containing the value $X$ with probability $ 2^{-X}$. As a result, the counter contains an approximation of $ \lg n$ after $n$ probabilistic updates stored in $ \lg \lg n$ bits. Here we revisit the original idea of Morris, and introduce a binary floating-point counter that uses a $d$-bit significand in conjunction with a binary exponent. The counter yields a simple formula for an unbiased estimation of $n$ with a standard deviation of about $ 0.6 \cdot n2^{-d / 2}$, and uses $ d + \lg \lg n$ bits. We analyze the floating-point counter's performance in a general framework that applies to any probabilistic counter, and derive practical formulas to assess its accuracy.

entry:
@Article{Csuros:2009:ACF,
  author =       "Miklos Csuros",
  title =        "Approximate counting with a floating-point counter",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "20",
  month =        apr,
  year =         "2009",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/0904.3062",
  abstract =     "Memory becomes a limiting factor in contemporary
                 applications, such as analyses of the Webgraph and
                 molecular sequences, when many objects need to be
                 counted simultaneously. Robert Morris [Communications
                 of the ACM, 21:840--842, 1978] proposed a probabilistic
                 technique for approximate counting that is extremely
                 space-efficient. The basic idea is to increment a
                 counter containing the value $X$ with probability $
                 2^{-X}$. As a result, the counter contains an
                 approximation of $ \lg n$ after $n$ probabilistic
                 updates stored in $ \lg \lg n$ bits. Here we revisit
                 the original idea of Morris, and introduce a binary
                 floating-point counter that uses a $d$-bit significand
                 in conjunction with a binary exponent. The counter
                 yields a simple formula for an unbiased estimation of
                 $n$ with a standard deviation of about $ 0.6 \cdot
                 n2^{-d / 2}$, and uses $ d + \lg \lg n$ bits. We
                 analyze the floating-point counter's performance in a
                 general framework that applies to any probabilistic
                 counter, and derive practical formulas to assess its
                 accuracy.",
  acknowledgement = ack-nhfb,
  subject =      "Data Structures and Algorithms (cs.DS)",
}


bibtype: article
filename: fparith.bib
label: Daumas:2009:VRN
author: M. Daumas and D. Lester and C. Muoz
title: Verified Real Number Calculations: a Library for Interval Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 2
pages: 226--237
month: feb
monthnumber: 2
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.213
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:39 MDT 2011
bibtimestamp: 2011.07.04 11:37:39 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4685896
fjournal: IEEE Transactions on Computers
keywords: interval arithmetic; proof checking; real number calculations; theorem proving
remark: Extended version of ARITH-18 article cite Daumas:2009:VRN.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. Daumas and D. Lester and C. Muoz
rawtitle: Verified Real Number Calculations: a Library for Interval Arithmetic
abstract:
Real number calculations on elementary functions are remarkably difficult to handle in mechanical proofs. In this paper, we show how these calculations can be performed within a theorem prover or proof assistant in a convenient and highly automated as well as interactive way. First, we formally establish upper and lower bounds for elementary functions. Then, based on these bounds, we develop a rational interval arithmetic where real number calculations take place in an algebraic setting. In order to reduce the dependency effect of interval arithmetic, we integrate two techniques: interval splitting and Taylor series expansions. This pragmatic approach has been developed, and formally verified, in a theorem prover. The formal development also includes a set of customizable strategies to automate proofs involving explicit calculations over real numbers. Our ultimate goal is to provide guaranteed proofs of numerical properties with minimal human theorem-prover interaction.

rawabstract:
Real number calculations on elementary functions are remarkably difficult to handle in mechanical proofs. In this paper, we show how these calculations can be performed within a theorem prover or proof assistant in a convenient and highly automated as well as interactive way. First, we formally establish upper and lower bounds for elementary functions. Then, based on these bounds, we develop a rational interval arithmetic where real number calculations take place in an algebraic setting. In order to reduce the dependency effect of interval arithmetic, we integrate two techniques: interval splitting and Taylor series expansions. This pragmatic approach has been developed, and formally verified, in a theorem prover. The formal development also includes a set of customizable strategies to automate proofs involving explicit calculations over real numbers. Our ultimate goal is to provide guaranteed proofs of numerical properties with minimal human theorem-prover interaction.

entry:
@Article{Daumas:2009:VRN,
  author =       "M. Daumas and D. Lester and C. Muoz",
  title =        "Verified Real Number Calculations: a Library for
                 Interval Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "2",
  pages =        "226--237",
  month =        feb,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.213",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4685896",
  abstract =     "Real number calculations on elementary functions are
                 remarkably difficult to handle in mechanical proofs. In
                 this paper, we show how these calculations can be
                 performed within a theorem prover or proof assistant in
                 a convenient and highly automated as well as
                 interactive way. First, we formally establish upper and
                 lower bounds for elementary functions. Then, based on
                 these bounds, we develop a rational interval arithmetic
                 where real number calculations take place in an
                 algebraic setting. In order to reduce the dependency
                 effect of interval arithmetic, we integrate two
                 techniques: interval splitting and Taylor series
                 expansions. This pragmatic approach has been developed,
                 and formally verified, in a theorem prover. The formal
                 development also includes a set of customizable
                 strategies to automate proofs involving explicit
                 calculations over real numbers. Our ultimate goal is to
                 provide guaranteed proofs of numerical properties with
                 minimal human theorem-prover interaction.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "interval arithmetic; proof checking; real number
                 calculations; theorem proving",
  remark =       "Extended version of ARITH-18 article
                 \cite{Daumas:2009:VRN}.",
}


bibtype: article
filename: fparith.bib
label: Davida:2009:FAU
author: George Davida and Bruce Litow and Guangwu Xu
title: Fast arithmetics using Chinese remaindering
journal: j-INFO-PROC-LETT
volume: 109
number: 13
pages: 660--662
day: 15
month: jun
monthnumber: 6
year: 2009
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Thu Mar 31 15:53:33 MDT 2011
bibtimestamp: 2011.03.31 15:53:33 MDT
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: George Davida and Bruce Litow and Guangwu Xu
rawtitle: Fast arithmetics using {Chinese} remaindering
entry:
@Article{Davida:2009:FAU,
  author =       "George Davida and Bruce Litow and Guangwu Xu",
  title =        "Fast arithmetics using {Chinese} remaindering",
  journal =      j-INFO-PROC-LETT,
  volume =       "109",
  number =       "13",
  pages =        "660--662",
  day =          "15",
  month =        jun,
  year =         "2009",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Thu Mar 31 15:53:33 MDT 2011",
  bibsource =    "http://www.sciencedirect.com/science/journal/00200190;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: book
filename: fparith.bib
label: Deschamps:2009:HIF
author: Jean-Pierre Deschamps and Jose Luis Imana and Gustavo D. Sutter
title: Hardware implementation of finite-field arithmetic
publisher: pub-MCGRAW-HILL
address: pub-MCGRAW-HILL:adr
pages: xiii + 347
year: 2009
ISBN: 0-07-154581-6 (hardcover) OR 0071545816 (hardcover)
ISBN13: 978-0-07-154581-5 (hardcover) OR 9780071545815 (hardcover)
LCCN: TK7895.E42 D466 2009
bibdate: Sat Sep 20 16:04:08 MDT 2014
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; z3950.loc.gov:7090/Voyager
bibtimestamp: 2014.09.20 16:04:08 MDT
series: Electronic engineering
acknowledgement: ack-nhfb
authordates: 1945--
rawauthor: Jean-Pierre Deschamps and Jos{\'e} Luis Ima{\~n}a and Gustavo D. Sutter
rawtitle: Hardware implementation of finite-field arithmetic
abstract:
Master cutting-edge electronic circuit synthesis and design with help from this detailed guide. Hardware Implementation of Finite-Field Arithmetic describes algorithms and circuits for executing finite-field operations, including addition, subtraction, multiplication, squaring, exponentiation, and division.par This comprehensive resource begins with an overview of mathematics, covering algebra, number theory, finite fields, and cryptography. The book then presents algorithms which can be executed and verified with actual input data. Logic schemes and VHDL models are described in such a way that the corresponding circuits can be easily simulated and synthesized. The book concludes with a real-world example of a finite-field application --- elliptic-curve cryptography. This is an essential guide for hardware engineers involved in the development of embedded systems.

subject:
Embedded computer systems; Design and construction; Field programmable gate arrays; Application-specific integrated circuits; Computer arithmetic

TOC:
1. Mathematical background / 1--24 2. Mod $m$ reduction / 25--60 3. Mod $m$ operations / 61--90 4. Operations over $rm GF(p)$ / 91--116 5. Operations over $Z_p[x] / f(x)$ / 117--138 6. Operations over $rm GF(p^n)$ / 139--162 7. Operations over $rm GF(2^m)$ --- Polynomial bases / 163--234 8. Operations over $rm GF(2^m)$ --- Normal bases / 235--268 9. Operations over $rm GF(2^m)$ --- Other bases / 269--286 10. An Example of Application --- Elliptic curve cryptography / 287--312 Appendix A. $p = 2^192 - 2^64 - 1$ / 313--318 Appendix B. Optical Extension Fields / 319--330 Appendix C. Binary Fields / 331--334 Appendix D. Ada versus VHDL / 337--340 Index / 341--347

rawabstract:
Master cutting-edge electronic circuit synthesis and design with help from this detailed guide. Hardware Implementation of Finite-Field Arithmetic describes algorithms and circuits for executing finite-field operations, including addition, subtraction, multiplication, squaring, exponentiation, and division.\par This comprehensive resource begins with an overview of mathematics, covering algebra, number theory, finite fields, and cryptography. The book then presents algorithms which can be executed and verified with actual input data. Logic schemes and VHDL models are described in such a way that the corresponding circuits can be easily simulated and synthesized. The book concludes with a real-world example of a finite-field application --- elliptic-curve cryptography. This is an essential guide for hardware engineers involved in the development of embedded systems.

rawTOC:
1. Mathematical background / 1--24 \\ 2. Mod $m$ reduction / 25--60 \\ 3. Mod $m$ operations / 61--90 \\ 4. Operations over ${\rm GF}(p)$ / 91--116 \\ 5. Operations over $Z_p[x] / f(x)$ / 117--138 \\ 6. Operations over ${\rm GF}(p^n)$ / 139--162 \\ 7. Operations over ${\rm GF}(2^m)$ --- Polynomial bases / 163--234 \\ 8. Operations over ${\rm GF}(2^m)$ --- Normal bases / 235--268 \\ 9. Operations over ${\rm GF}(2^m)$ --- Other bases / 269--286 \\ 10. An Example of Application --- Elliptic curve cryptography / 287--312 \\ Appendix A. $p = 2^{192} - 2^{64} - 1$ / 313--318 \\ Appendix B. Optical Extension Fields / 319--330 \\ Appendix C. Binary Fields / 331--334 \\ Appendix D. Ada versus VHDL / 337--340 \\ Index / 341--347

entry:
@Book{Deschamps:2009:HIF,
  author =       "Jean-Pierre Deschamps and Jos{\'e} Luis Ima{\~n}a and
                 Gustavo D. Sutter",
  title =        "Hardware implementation of finite-field arithmetic",
  publisher =    pub-MCGRAW-HILL,
  address =      pub-MCGRAW-HILL:adr,
  pages =        "xiii + 347",
  year =         "2009",
  ISBN =         "0-07-154581-6 (hardcover)",
  ISBN-13 =      "978-0-07-154581-5 (hardcover)",
  LCCN =         "TK7895.E42 D466 2009",
  bibdate =      "Sat Sep 20 16:04:08 MDT 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 z3950.loc.gov:7090/Voyager",
  series =       "Electronic engineering",
  abstract =     "Master cutting-edge electronic circuit synthesis and
                 design with help from this detailed guide. Hardware
                 Implementation of Finite-Field Arithmetic describes
                 algorithms and circuits for executing finite-field
                 operations, including addition, subtraction,
                 multiplication, squaring, exponentiation, and
                 division.\par

                 This comprehensive resource begins with an overview of
                 mathematics, covering algebra, number theory, finite
                 fields, and cryptography. The book then presents
                 algorithms which can be executed and verified with
                 actual input data. Logic schemes and VHDL models are
                 described in such a way that the corresponding circuits
                 can be easily simulated and synthesized. The book
                 concludes with a real-world example of a finite-field
                 application --- elliptic-curve cryptography. This is an
                 essential guide for hardware engineers involved in the
                 development of embedded systems.",
  acknowledgement = ack-nhfb,
  author-dates = "1945--",
  subject =      "Embedded computer systems; Design and construction;
                 Field programmable gate arrays; Application-specific
                 integrated circuits; Computer arithmetic",
  tableofcontents = "1. Mathematical background / 1--24 \\
                 2. Mod $m$ reduction / 25--60 \\
                 3. Mod $m$ operations / 61--90 \\
                 4. Operations over ${\rm GF}(p)$ / 91--116 \\
                 5. Operations over $Z_p[x] / f(x)$ / 117--138 \\
                 6. Operations over ${\rm GF}(p^n)$ / 139--162 \\
                 7. Operations over ${\rm GF}(2^m)$ --- Polynomial bases
                 / 163--234 \\
                 8. Operations over ${\rm GF}(2^m)$ --- Normal bases /
                 235--268 \\
                 9. Operations over ${\rm GF}(2^m)$ --- Other bases /
                 269--286 \\
                 10. An Example of Application --- Elliptic curve
                 cryptography / 287--312 \\
                 Appendix A. $p = 2^{192} - 2^{64} - 1$ / 313--318 \\
                 Appendix B. Optical Extension Fields / 319--330 \\
                 Appendix C. Binary Fields / 331--334 \\
                 Appendix D. Ada versus VHDL / 337--340 \\
                 Index / 341--347",
}


bibtype: inproceedings
filename: fparith.bib
label: Dormiani:2009:DIR
author: P. Dormiani and M. D. Ercegovac and Jean-Michel Muller
title: Design and Implementation of a Radix-4 Complex Division Unit with Prescaling
crossref: IEEE:2009:IICa
pages: 83--90
year: 2009
DOI: https://doi.org/10.1109/ASAP.2009.32
bibdate: Fri Dec 03 15:01:28 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.12.03 15:01:28 ???
acknowledgement: ack-nhfb
rawauthor: P. Dormiani and M. D. Ercegovac and Jean-Michel Muller
rawtitle: Design and Implementation of a Radix-4 Complex Division Unit with Prescaling
abstract:
We present a design and implementation of a radix-4 complex division unit with prescaling of the operands. Specifically, we extend the treatment of the residual bound and errors due to the use of truncated redundant representation. The requirements for prescaling tables are simplified and a detailed specification of the table design is given. All principal components used in the design are described and the proposed optimizations are explained. The target platform for implementation was an Altera Stratix II FPGA for which we report timing and area requirements. For a precision of 36 bits, the implementation uses 1185 ALUTs, achieving a latency of 157 ns. The maximum clock frequency is 173.49 MHz.

keywords:
Altera Stratix II FPGA; digital arithmetic; field programmable gate arrays; frequency 173.49 MHz; integrated circuit design; logic design; operand prescaling; prescalers; prescaling tables; radix-4 complex division unit; table design

rawabstract:
We present a design and implementation of a radix-4 complex division unit with prescaling of the operands. Specifically, we extend the treatment of the residual bound and errors due to the use of truncated redundant representation. The requirements for prescaling tables are simplified and a detailed specification of the table design is given. All principal components used in the design are described and the proposed optimizations are explained. The target platform for implementation was an Altera Stratix II FPGA for which we report timing and area requirements. For a precision of 36 bits, the implementation uses 1185 ALUTs, achieving a latency of 157 ns. The maximum clock frequency is 173.49 MHz.

entry:
@InProceedings{Dormiani:2009:DIR,
  author =       "P. Dormiani and M. D. Ercegovac and Jean-Michel
                 Muller",
  title =        "Design and Implementation of a Radix-4 Complex
                 Division Unit with Prescaling",
  crossref =     "IEEE:2009:IICa",
  pages =        "83--90",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ASAP.2009.32",
  bibdate =      "Fri Dec 03 15:01:28 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a design and implementation of a radix-4
                 complex division unit with prescaling of the operands.
                 Specifically, we extend the treatment of the residual
                 bound and errors due to the use of truncated redundant
                 representation. The requirements for prescaling tables
                 are simplified and a detailed specification of the
                 table design is given. All principal components used in
                 the design are described and the proposed optimizations
                 are explained. The target platform for implementation
                 was an Altera Stratix II FPGA for which we report
                 timing and area requirements. For a precision of 36
                 bits, the implementation uses 1185 ALUTs, achieving a
                 latency of 157 ns. The maximum clock frequency is
                 173.49 MHz.",
  acknowledgement = ack-nhfb,
  keywords =     "Altera Stratix II FPGA; digital arithmetic; field
                 programmable gate arrays; frequency 173.49 MHz;
                 integrated circuit design; logic design; operand
                 prescaling; prescalers; prescaling tables; radix-4
                 complex division unit; table design",
}


bibtype: inproceedings
filename: fparith.bib
label: Dormiani:2009:LPT
author: Pouya Dormiani and Milo D. Ercegovac and Jean-Michel Muller
editor: Michael B. Matthews
title: Low precision table based complex reciprocal approximation
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1803--1807
year: 2009
DOI: https://doi.org/10.1109/ACSSC.2009.5470209
ISBN: 1-4244-5827-7 OR 1424458277
ISBN13: 978-1-4244-5827-1 OR 9781424458271
ISSN: 1058-6393 OR 10586393
ISSNL: 1058-6393 OR 10586393
bibdate: Fri Sep 29 10:50:54 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 10:50:54 ???
acknowledgement: ack-nhfb
rawauthor: Pouya Dormiani and Milo D. Ercegovac and Jean-Michel Muller
raweditor: Michael B. Matthews
rawtitle: Low precision table based complex reciprocal approximation
booktitle:
2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers. November 1--4, 2009. Pacific Grove, California

rawbooktitle:
{2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers. November 1--4, 2009. Pacific Grove, California}

entry:
@InProceedings{Dormiani:2009:LPT,
  author =       "Pouya Dormiani and Milo D. Ercegovac and Jean-Michel
                 Muller",
  editor =       "Michael B. Matthews",
  booktitle =    "{2009 Conference Record of the Forty-Third Asilomar
                 Conference on Signals, Systems and Computers. November
                 1--4, 2009. Pacific Grove, California}",
  title =        "Low precision table based complex reciprocal
                 approximation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1803--1807",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ACSSC.2009.5470209",
  ISBN =         "1-4244-5827-7",
  ISBN-13 =      "978-1-4244-5827-1",
  ISSN =         "1058-6393",
  ISSN-L =       "1058-6393",
  bibdate =      "Fri Sep 29 10:50:54 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Duff:2009:GMA
author: Bob Duff
title: Gem #26: the tt mod attribute
journal: j-SIGADA-LETTERS
volume: 29
number: 1
pages: 33--34
month: apr
monthnumber: 4
year: 2009
CODEN: AALEE5
DOI: https://doi.org/10.1145/1541788.1541795
ISSN: 1094-3641 (print), 1557-9476 (electronic) OR 10943641 (print), 15579476 (electronic)
ISSNL: 1094-3641 OR 10943641
bibdate: Mon Jun 21 14:03:13 MDT 2010
bibtimestamp: 2010.06.21 14:03:13 MDT
fjournal: ACM SIGAda Ada Letters
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/citation.cfm?id=J32
rawauthor: Bob Duff
rawtitle: Gem \#26: the {\tt mod} attribute
abstract:
Ada Gem #26 --- T'Mod can be used to convert signed integers to modular integers using modular (wraparound) arithmetic.

rawabstract:
Ada Gem \#26 --- T'Mod can be used to convert signed integers to modular integers using modular (wraparound) arithmetic.

entry:
@Article{Duff:2009:GMA,
  author =       "Bob Duff",
  title =        "Gem \#26: the {\tt mod} attribute",
  journal =      j-SIGADA-LETTERS,
  volume =       "29",
  number =       "1",
  pages =        "33--34",
  month =        apr,
  year =         "2009",
  CODEN =        "AALEE5",
  DOI =          "https://doi.org/10.1145/1541788.1541795",
  ISSN =         "1094-3641 (print), 1557-9476 (electronic)",
  ISSN-L =       "1094-3641",
  bibdate =      "Mon Jun 21 14:03:13 MDT 2010",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigada.bib",
  abstract =     "Ada Gem \#26 --- T'Mod can be used to convert signed
                 integers to modular integers using modular (wraparound)
                 arithmetic.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGAda Ada Letters",
  journal-URL =  "http://portal.acm.org/citation.cfm?id=J32",
}


bibtype: inproceedings
filename: fparith.bib
label: Edmonson:2009:IIS
author: William Edmonson and Guillaume Melquiond
title: IEEE Interval Standard Working Group --- P1788: Current Status
crossref: Bruguera:2009:PIS
pages: 231--234
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: William Edmonson and Guillaume Melquiond
rawtitle: {IEEE Interval Standard Working Group --- P1788}: Current Status
abstract:
Late 2008, at SCAN 2008 in El Paso, TX, an effort to standardize interval computations was started by a working group of the IEEE Microprocessor Standards Committee, titled the Interval Arithmetic Working Group of the IEEE P1788 Standard. This paper describes the goals of this effort, the history of the working group, and how it relates to the IEEE 754 Standard. It gives a brief overview of the policies and procedures for constructing the standard, and its expected structure. It also presents some of the questions the group may have to solve in the future.

rawabstract:
Late 2008, at SCAN 2008 in El Paso, TX, an effort to standardize interval computations was started by a working group of the IEEE Microprocessor Standards Committee, titled the Interval Arithmetic Working Group of the IEEE P1788 Standard. This paper describes the goals of this effort, the history of the working group, and how it relates to the IEEE 754 Standard. It gives a brief overview of the policies and procedures for constructing the standard, and its expected structure. It also presents some of the questions the group may have to solve in the future.

entry:
@InProceedings{Edmonson:2009:IIS,
  author =       "William Edmonson and Guillaume Melquiond",
  title =        "{IEEE Interval Standard Working Group --- P1788}:
                 Current Status",
  crossref =     "Bruguera:2009:PIS",
  pages =        "231--234",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Late 2008, at SCAN 2008 in El Paso, TX, an effort to
                 standardize interval computations was started by a
                 working group of the IEEE Microprocessor Standards
                 Committee, titled the Interval Arithmetic Working Group
                 of the IEEE P1788 Standard. This paper describes the
                 goals of this effort, the history of the working group,
                 and how it relates to the IEEE 754 Standard. It gives a
                 brief overview of the policies and procedures for
                 constructing the standard, and its expected structure.
                 It also presents some of the questions the group may
                 have to solve in the future.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: article
filename: fparith.bib
label: Enge:2009:CCP
author: Andreas Enge
title: The complexity of class polynomial computation via floating point approximations
journal: j-MATH-COMPUT
volume: 78
number: 266
pages: 1089--1107
month: apr
monthnumber: 4
year: 2009
CODEN: MCMPAF
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Fri May 14 06:20:58 MDT 2010
bibsource: http://www.ams.org/mcom/2009-78-266; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.14 06:20:58 MDT
fjournal: Mathematics of Computation
keywords: roots of elliptic curves
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Andreas Enge
rawtitle: The complexity of class polynomial computation via floating point approximations
URL:
http://www.ams.org/journals/mcom/2009-78-266/S0025-5718-08-02200-X/home.html; http://www.ams.org/journals/mcom/2009-78-266/S0025-5718-08-02200-X/S0025-5718-08-02200-X.pdf

entry:
@Article{Enge:2009:CCP,
  author =       "Andreas Enge",
  title =        "The complexity of class polynomial computation via
                 floating point approximations",
  journal =      j-MATH-COMPUT,
  volume =       "78",
  number =       "266",
  pages =        "1089--1107",
  month =        apr,
  year =         "2009",
  CODEN =        "MCMPAF",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Fri May 14 06:20:58 MDT 2010",
  bibsource =    "http://www.ams.org/mcom/2009-78-266;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.ams.org/journals/mcom/2009-78-266/S0025-5718-08-02200-X/home.html;
                 http://www.ams.org/journals/mcom/2009-78-266/S0025-5718-08-02200-X/S0025-5718-08-02200-X.pdf",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
  keywords =     "roots of elliptic curves",
}


bibtype: manual
filename: fparith.bib
label: Enge:2009:MLM
author: Andreas Enge and Philippe Theveny and Paul Zimmermann
title: texttt mpc --- a library for multiprecision complex arithmetic with exact rounding
organization: INRIA
address: France
edition: 0.8.1
pages: 1089--1107
month: dec
monthnumber: 12
year: 2009
bibdate: Sun May 2 09:31:32 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.02 09:31:32 ???
URL: http://mpc.multiprecision.org/
acknowledgement: ack-nhfb
rawauthor: Andreas Enge and Philippe Th{\'e}veny and Paul Zimmermann
rawtitle: {\texttt{mpc}} --- a library for multiprecision complex arithmetic with exact rounding
entry:
@Manual{Enge:2009:MLM,
  author =       "Andreas Enge and Philippe Th{\'e}veny and Paul
                 Zimmermann",
  title =        "{\texttt{mpc}} --- a library for multiprecision
                 complex arithmetic with exact rounding",
  organization = "INRIA",
  address =      "France",
  edition =      "0.8.1",
  month =        dec,
  year =         "2009",
  bibdate =      "Sun May 2 09:31:32 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mpc.multiprecision.org/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Erle:2009:DFP
author: Mark A. Erle and Brian J. Hickmann and Michael J. Schulte
title: Decimal Floating-Point Multiplication
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 7
pages: 902--916
month: jul
monthnumber: 7
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.218
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:42 MDT 2011
bibtimestamp: 2011.07.04 11:37:42 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4711044
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Mark A. Erle and Brian J. Hickmann and Michael J. Schulte
rawtitle: Decimal Floating-Point Multiplication
abstract:
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents the design of two decimal floating-point multipliers: one whose partial product accumulation strategy employs decimal carry-save addition and one that employs binary carry-save addition. The multiplier based on decimal carry-save addition favors a nonpipelined iterative implementation. The multiplier utilizing binary carry-save addition allows for an efficient pipelined implementation when latency and throughput are considered more important than area. Both designs comply with specifications for decimal multiplication given in the IEEE 754 Standard for Floating-Point Arithmetic (IEEE 754-2008). The multipliers extend previously published decimal fixed-point multipliers by adding several features, including exponent generation, sticky bit generation, shifting of the intermediate product, rounding, and exception detection and handling. Novel features of the multipliers include support for decimal floating-point numbers, on-the-fly generation of the sticky bit in the iterative design, early estimation of the shift amount, and efficient decimal rounding. Iterative and parallel decimal fixed-point and floating-point multipliers are compared in terms of their area, delay, latency, and throughput based on verified Verilog register-transfer-level models.

keywords:
arithmetic and logic units; binary coded decimal; computer arithmetic; decimal multiplication; floating-point arithmetic; general high-speed arithmetic; parallel multiplication; pipelined multiplication; serial multiplication

rawabstract:
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents the design of two decimal floating-point multipliers: one whose partial product accumulation strategy employs decimal carry-save addition and one that employs binary carry-save addition. The multiplier based on decimal carry-save addition favors a nonpipelined iterative implementation. The multiplier utilizing binary carry-save addition allows for an efficient pipelined implementation when latency and throughput are considered more important than area. Both designs comply with specifications for decimal multiplication given in the IEEE 754 Standard for Floating-Point Arithmetic (IEEE 754-2008). The multipliers extend previously published decimal fixed-point multipliers by adding several features, including exponent generation, sticky bit generation, shifting of the intermediate product, rounding, and exception detection and handling. Novel features of the multipliers include support for decimal floating-point numbers, on-the-fly generation of the sticky bit in the iterative design, early estimation of the shift amount, and efficient decimal rounding. Iterative and parallel decimal fixed-point and floating-point multipliers are compared in terms of their area, delay, latency, and throughput based on verified Verilog register-transfer-level models.

entry:
@Article{Erle:2009:DFP,
  author =       "Mark A. Erle and Brian J. Hickmann and Michael J.
                 Schulte",
  title =        "Decimal Floating-Point Multiplication",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "7",
  pages =        "902--916",
  month =        jul,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.218",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:42 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4711044",
  abstract =     "Decimal multiplication is important in many commercial
                 applications including financial analysis, banking, tax
                 calculation, currency conversion, insurance, and
                 accounting. This paper presents the design of two
                 decimal floating-point multipliers: one whose partial
                 product accumulation strategy employs decimal
                 carry-save addition and one that employs binary
                 carry-save addition. The multiplier based on decimal
                 carry-save addition favors a nonpipelined iterative
                 implementation. The multiplier utilizing binary
                 carry-save addition allows for an efficient pipelined
                 implementation when latency and throughput are
                 considered more important than area. Both designs
                 comply with specifications for decimal multiplication
                 given in the IEEE 754 Standard for Floating-Point
                 Arithmetic (IEEE 754-2008). The multipliers extend
                 previously published decimal fixed-point multipliers by
                 adding several features, including exponent generation,
                 sticky bit generation, shifting of the intermediate
                 product, rounding, and exception detection and
                 handling. Novel features of the multipliers include
                 support for decimal floating-point numbers, on-the-fly
                 generation of the sticky bit in the iterative design,
                 early estimation of the shift amount, and efficient
                 decimal rounding. Iterative and parallel decimal
                 fixed-point and floating-point multipliers are compared
                 in terms of their area, delay, latency, and throughput
                 based on verified Verilog register-transfer-level
                 models.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "arithmetic and logic units; binary coded decimal;
                 computer arithmetic; decimal multiplication;
                 floating-point arithmetic; general high-speed
                 arithmetic; parallel multiplication; pipelined
                 multiplication; serial multiplication",
}


bibtype: inproceedings
filename: fparith.bib
label: Fahmy:2009:EDI
title: Energy and Delay Improvement via Decimal Floating Point Units
crossref: Bruguera:2009:PIS
pages: 221--224
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawtitle: Energy and Delay Improvement via Decimal Floating Point Units
author:
Hossam A. H. Fahmy and Ramy Raafat and Amira M. Abdel-Majeed and Rodina Samy and Tarek ElDeeb and Yasmin Farouk

abstract:
Interest in decimal arithmetic increased considerably in recent years. This paper presents new designs for decimal floating point (DFP) addition, multiplication, fused multiply-add, division, and square root. It stresses the importance of energy savings achieved by hardware implementations of the IEEE standard for decimal floating point. To the best of the authors knowledge, this is the first work to discuss energy savings in DFP and the first to present a hardware implementation of a fused multiply-add. Our Newton--Raphson based divider is over three times faster than the similar design previously reported.

rawabstract:
Interest in decimal arithmetic increased considerably in recent years. This paper presents new designs for decimal floating point (DFP) addition, multiplication, fused multiply-add, division, and square root. It stresses the importance of energy savings achieved by hardware implementations of the IEEE standard for decimal floating point. To the best of the authors knowledge, this is the first work to discuss energy savings in DFP and the first to present a hardware implementation of a fused multiply-add. Our Newton--Raphson based divider is over three times faster than the similar design previously reported.

rawauthor:
Hossam A. H. Fahmy and Ramy Raafat and Amira M. Abdel-Majeed and Rodina Samy and Tarek ElDeeb and Yasmin Farouk

entry:
@InProceedings{Fahmy:2009:EDI,
  author =       "Hossam A. H. Fahmy and Ramy Raafat and Amira M.
                 Abdel-Majeed and Rodina Samy and Tarek ElDeeb and
                 Yasmin Farouk",
  title =        "Energy and Delay Improvement via Decimal Floating
                 Point Units",
  crossref =     "Bruguera:2009:PIS",
  pages =        "221--224",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Interest in decimal arithmetic increased considerably
                 in recent years. This paper presents new designs for
                 decimal floating point (DFP) addition, multiplication,
                 fused multiply-add, division, and square root. It
                 stresses the importance of energy savings achieved by
                 hardware implementations of the IEEE standard for
                 decimal floating point. To the best of the authors
                 knowledge, this is the first work to discuss energy
                 savings in DFP and the first to present a hardware
                 implementation of a fused multiply-add. Our
                 Newton--Raphson based divider is over three times
                 faster than the similar design previously reported.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: article
filename: fparith.bib
label: Fewster:2009:SEB
author: R. M. Fewster
title: A Simple Explanation of Benford's Law
journal: j-AMER-STAT
volume: 63
number: 1
pages: 26--32
month: feb
monthnumber: 2
year: 2009
CODEN: ASTAAJ
DOI: https://doi.org/10.1198/tast.2009.0005
ISSN: 0003-1305 (print), 1537-2731 (electronic) OR 00031305 (print), 15372731 (electronic)
ISSNL: 0003-1305 OR 00031305
bibdate: Thu Aug 26 21:48:27 MDT 2010
bibtimestamp: 2010.08.26 21:48:27 MDT
fjournal: The American Statistician
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/utas20
rawauthor: R. M. Fewster
rawtitle: A Simple Explanation of {Benford's Law}
bibsource:
http://www.amstat.org/publications/tas/; https://www.math.utah.edu/pub/tex/bib/amstat.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Fewster:2009:SEB,
  author =       "R. M. Fewster",
  title =        "A Simple Explanation of {Benford's Law}",
  journal =      j-AMER-STAT,
  volume =       "63",
  number =       "1",
  pages =        "26--32",
  month =        feb,
  year =         "2009",
  CODEN =        "ASTAAJ",
  DOI =          "https://doi.org/10.1198/tast.2009.0005",
  ISSN =         "0003-1305 (print), 1537-2731 (electronic)",
  ISSN-L =       "0003-1305",
  bibdate =      "Thu Aug 26 21:48:27 MDT 2010",
  bibsource =    "http://www.amstat.org/publications/tas/;
                 https://www.math.utah.edu/pub/tex/bib/amstat.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The American Statistician",
  journal-URL =  "http://www.tandfonline.com/loi/utas20",
}


bibtype: article
filename: fparith.bib
label: Fit-Florea:2009:DLN
author: A. Fit-Florea and L. Li and M. A. Thornton and D. W. Matula
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 2
pages: 163--174
month: feb
monthnumber: 2
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.204
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:39 MDT 2011
bibtimestamp: 2011.07.04 11:37:39 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4663061
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Fit-Florea and L. Li and M. A. Thornton and D. W. Matula
title:
A Discrete Logarithm Number System for Integer Arithmetic Modulo $ 2^k $: Algorithms and Lookup Structures

abstract:
We present a $k$-bit encoding of the $k$-bit binary integers based on a discrete logarithm representation. The representation supports a discrete logarithm number system (DLS) that allows integer multiplication to be reduced to addition and integer exponentiation to be reduced to multiplication. We introduce right-to-left bit serial conversion, deconversion, and unified conversion/deconversion algorithms between binary and DLS. The conversion algorithms utilize $ O(k) $ additions, do not require the use of a multiplier, and are applicable at least up to 128-bit integers. We illustrate the use of the representation in determining a novel and efficient integer power modulo $ 2^k $ operation $ |x^y|_2k $ and compare hardware performance with a current state-of-the-art method. Furthermore, we describe properties of the conversion mappings that allow compact table lookup structures to be employed for direct conversion to and deconversion from the DLS encoding. Our lookup architecture allows 16-bit conversion and deconversion mappings to be realized with table sizes of order 2--8 Kbytes, which is up to a $ 64 times $ size reduction of the 128 Kbytes of an arbitrary 16-bits-in, 16-bits-out function table. Performance and area results that demonstrate the effectiveness of the table lookup architecture are given. The lookup methodology extends to other 16-bit integer functions such as multiplicative inverse and squaring operations.

keywords:
arithmetic and logic units; bit serial; computer arithmetic; conversions; discrete logarithm; high-speed arithmetic; integer power; number encodings; table lookup

rawabstract:
We present a $k$-bit encoding of the $k$-bit binary integers based on a discrete logarithm representation. The representation supports a discrete logarithm number system (DLS) that allows integer multiplication to be reduced to addition and integer exponentiation to be reduced to multiplication. We introduce right-to-left bit serial conversion, deconversion, and unified conversion/deconversion algorithms between binary and DLS. The conversion algorithms utilize $ O(k) $ additions, do not require the use of a multiplier, and are applicable at least up to 128-bit integers. We illustrate the use of the representation in determining a novel and efficient integer power modulo $ 2^k $ operation $ |x^y|_{2k} $ and compare hardware performance with a current state-of-the-art method. Furthermore, we describe properties of the conversion mappings that allow compact table lookup structures to be employed for direct conversion to and deconversion from the DLS encoding. Our lookup architecture allows 16-bit conversion and deconversion mappings to be realized with table sizes of order 2--8 Kbytes, which is up to a $ 64 \times $ size reduction of the 128 Kbytes of an arbitrary 16-bits-in, 16-bits-out function table. Performance and area results that demonstrate the effectiveness of the table lookup architecture are given. The lookup methodology extends to other 16-bit integer functions such as multiplicative inverse and squaring operations.

rawtitle:
A Discrete Logarithm Number System for Integer Arithmetic Modulo $ 2^k $: Algorithms and Lookup Structures

entry:
@Article{Fit-Florea:2009:DLN,
  author =       "A. Fit-Florea and L. Li and M. A. Thornton and D. W.
                 Matula",
  title =        "A Discrete Logarithm Number System for Integer
                 Arithmetic Modulo $ 2^k $: Algorithms and Lookup
                 Structures",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "2",
  pages =        "163--174",
  month =        feb,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.204",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4663061",
  abstract =     "We present a $k$-bit encoding of the $k$-bit binary
                 integers based on a discrete logarithm representation.
                 The representation supports a discrete logarithm number
                 system (DLS) that allows integer multiplication to be
                 reduced to addition and integer exponentiation to be
                 reduced to multiplication. We introduce right-to-left
                 bit serial conversion, deconversion, and unified
                 conversion/deconversion algorithms between binary and
                 DLS. The conversion algorithms utilize $ O(k) $
                 additions, do not require the use of a multiplier, and
                 are applicable at least up to 128-bit integers. We
                 illustrate the use of the representation in determining
                 a novel and efficient integer power modulo $ 2^k $
                 operation $ |x^y|_{2k} $ and compare hardware
                 performance with a current state-of-the-art method.
                 Furthermore, we describe properties of the conversion
                 mappings that allow compact table lookup structures to
                 be employed for direct conversion to and deconversion
                 from the DLS encoding. Our lookup architecture allows
                 16-bit conversion and deconversion mappings to be
                 realized with table sizes of order 2--8 Kbytes, which
                 is up to a $ 64 \times $ size reduction of the 128
                 Kbytes of an arbitrary 16-bits-in, 16-bits-out function
                 table. Performance and area results that demonstrate
                 the effectiveness of the table lookup architecture are
                 given. The lookup methodology extends to other 16-bit
                 integer functions such as multiplicative inverse and
                 squaring operations.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "arithmetic and logic units; bit serial; computer
                 arithmetic; conversions; discrete logarithm; high-speed
                 arithmetic; integer power; number encodings; table
                 lookup",
}


bibtype: article
filename: fparith.bib
label: Fraysse:2009:ASF
author: Valerie Fraysse and Luc Giraud and Serge Gratton
journal: j-TOMS
volume: 35
number: 2
pages: 13:1--13:12
month: jul
monthnumber: 7
year: 2009
CODEN: ACMSCU
DOI: https://doi.org/10.1145/1377612.1377617
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Tue Aug 5 18:13:00 MDT 2008
bibsource: http://www.acm.org/pubs/contents/journals/toms/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.05 18:13:00 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 13
journalURL: https://dl.acm.org/loi/toms
rawauthor: Val{\'e}rie Frayss{\'e} and Luc Giraud and Serge Gratton
title:
Algorithm 881: a Set of Flexible GMRES Routines for Real and Complex Arithmetics on High-Performance Computers

abstract:
In this article we describe our implementations of the FGMRES algorithm for both real and complex, single and double precision arithmetics suitable for serial, shared-memory, and distributed-memory computers. For the sake of portability, simplicity, flexibility, and efficiency, the FGMRES solvers have been implemented in Fortran 77 using the reverse communication mechanism for the matrix-vector product, the preconditioning, and the dot-product computations. For distributed-memory computation, several orthogonalization procedures have been implemented to reduce the cost of the dot-product calculation, which is a well-known bottleneck of efficiency for Krylov methods. Furthermore, either implicit or explicit calculation of the residual at restart is possible depending on the actual cost of the matrix-vector product. Finally, the implemented stopping criterion is based on a normwise backward error.

keywords:
distributed memory; FGMRES; flexible Krylov methods; high-performance computing; linear systems; reverse communication

rawabstract:
In this article we describe our implementations of the FGMRES algorithm for both real and complex, single and double precision arithmetics suitable for serial, shared-memory, and distributed-memory computers. For the sake of portability, simplicity, flexibility, and efficiency, the FGMRES solvers have been implemented in Fortran 77 using the reverse communication mechanism for the matrix-vector product, the preconditioning, and the dot-product computations. For distributed-memory computation, several orthogonalization procedures have been implemented to reduce the cost of the dot-product calculation, which is a well-known bottleneck of efficiency for Krylov methods. Furthermore, either implicit or explicit calculation of the residual at restart is possible depending on the actual cost of the matrix-vector product. Finally, the implemented stopping criterion is based on a normwise backward error.

rawtitle:
{Algorithm 881}: a Set of Flexible {GMRES} Routines for Real and Complex Arithmetics on High-Performance Computers

entry:
@Article{Fraysse:2009:ASF,
  author =       "Val{\'e}rie Frayss{\'e} and Luc Giraud and Serge
                 Gratton",
  title =        "{Algorithm 881}: a Set of Flexible {GMRES} Routines
                 for Real and Complex Arithmetics on High-Performance
                 Computers",
  journal =      j-TOMS,
  volume =       "35",
  number =       "2",
  pages =        "13:1--13:12",
  month =        jul,
  year =         "2009",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/1377612.1377617",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Tue Aug 5 18:13:00 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this article we describe our implementations of the
                 FGMRES algorithm for both real and complex, single and
                 double precision arithmetics suitable for serial,
                 shared-memory, and distributed-memory computers. For
                 the sake of portability, simplicity, flexibility, and
                 efficiency, the FGMRES solvers have been implemented in
                 Fortran 77 using the reverse communication mechanism
                 for the matrix-vector product, the preconditioning, and
                 the dot-product computations. For distributed-memory
                 computation, several orthogonalization procedures have
                 been implemented to reduce the cost of the dot-product
                 calculation, which is a well-known bottleneck of
                 efficiency for Krylov methods. Furthermore, either
                 implicit or explicit calculation of the residual at
                 restart is possible depending on the actual cost of the
                 matrix-vector product. Finally, the implemented
                 stopping criterion is based on a normwise backward
                 error.",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "distributed memory; FGMRES; flexible Krylov methods;
                 high-performance computing; linear systems; reverse
                 communication",
}


bibtype: article
filename: fparith.bib
label: Furer:2009:FIM
author: Martin Furer
title: Faster Integer Multiplication
journal: j-SIAM-J-COMPUT
volume: 39
number: 3
pages: 979--1005
year: 2009
CODEN: SMJCAT
ISSN: 0097-5397 (print), 1095-7111 (electronic) OR 00975397 (print), 10957111 (electronic)
ISSNL: 0097-5397 OR 00975397
bibdate: Tue May 18 08:22:12 MDT 2010
bibtimestamp: 2010.05.18 08:22:12 MDT
fjournal: SIAM Journal on Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sicomp
rawauthor: Martin F{\"u}rer
rawtitle: Faster Integer Multiplication
bibsource:
http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/39/3; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Furer:2009:FIM,
  author =       "Martin F{\"u}rer",
  title =        "Faster Integer Multiplication",
  journal =      j-SIAM-J-COMPUT,
  volume =       "39",
  number =       "3",
  pages =        "979--1005",
  month =        "????",
  year =         "2009",
  CODEN =        "SMJCAT",
  DOI =          "",
  ISSN =         "0097-5397 (print), 1095-7111 (electronic)",
  ISSN-L =       "0097-5397",
  bibdate =      "Tue May 18 08:22:12 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/39/3;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Computing",
  journal-URL =  "http://epubs.siam.org/sicomp",
}


bibtype: article
filename: fparith.bib
label: Gavrilova:2009:ESC
author: Marina L. Gavrilova
journal: j-INT-J-COMPUT-GEOM-APPL
volume: 19
number: 5
pages: 415--424
month: oct
monthnumber: 10
year: 2009
CODEN: IJCAEV
DOI: https://doi.org/10.1142/S0218195909003040
ISSN: 0218-1959 OR 02181959
bibdate: Mon Aug 30 10:25:06 MDT 2010
bibsource: http://ejournals.wspc.com.sg/ijcga/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.08.30 10:25:06 MDT
fjournal: International journal of computational geometry and applications
acknowledgement: ack-nhfb
journalURL: http://www.worldscientific.com/loi/ijcga
rawauthor: Marina L. Gavrilova
title:
An Explicit Solution for Computing the Vertices of the Euclidean $d$-Dimensional Voronoi Diagram of Spheres in a Floating-Point Arithmetic

rawtitle:
An Explicit Solution for Computing the Vertices of the {Euclidean} $d$-Dimensional {Voronoi} Diagram of Spheres in a Floating-Point Arithmetic

entry:
@Article{Gavrilova:2009:ESC,
  author =       "Marina L. Gavrilova",
  title =        "An Explicit Solution for Computing the Vertices of the
                 {Euclidean} $d$-Dimensional {Voronoi} Diagram of
                 Spheres in a Floating-Point Arithmetic",
  journal =      j-INT-J-COMPUT-GEOM-APPL,
  volume =       "19",
  number =       "5",
  pages =        "415--424",
  month =        oct,
  year =         "2009",
  CODEN =        "IJCAEV",
  DOI =          "https://doi.org/10.1142/S0218195909003040",
  ISSN =         "0218-1959",
  bibdate =      "Mon Aug 30 10:25:06 MDT 2010",
  bibsource =    "http://ejournals.wspc.com.sg/ijcga/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "International journal of computational geometry and
                 applications",
  journal-URL =  "http://www.worldscientific.com/loi/ijcga",
}


bibtype: incollection
filename: fparith.bib
label: Gentle:2009:CSA
author: James E. Gentle
booktitle: Computational Statistics
title: Computer Storage and Arithmetic
publisher: pub-SV
address: pub-SV:adr
pages: 85--105
year: 2009
DOI: https://doi.org/10.1007/978-0-387-98144-4_2
ISBN: 0-387-98143-8 (print), 0-387-98144-6 (electronic) OR 0387981438 (print), 0387981446 (electronic)
LCCN: QA276.4 .G46 2009
bibdate: Mon May 06 17:36:21 2013
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2013.05.06 17:36:21 ???
series: Statistics and Computing
URL: http://link.springer.com/chapter/10.1007/978-0-387-98144-4_2
acknowledgement: ack-nhfb
bookpages: xxi + 727
rawauthor: James E. Gentle
rawbooktitle: Computational Statistics
rawtitle: Computer Storage and Arithmetic
ISBN13:
978-0-387-98143-7 (print), 978-0-387-98144-4 (electronic) OR 9780387981437 (print), 9780387981444 (electronic)

TOC:
Part I, Preliminaries. Mathematical and statistical preliminaries Part II, Statistical computing Computer storage and arithmetic algorithm and programming Approximation of functions and numerical quadrature Numerical linear algebra Solution of nonlinear equations and optimization Generation of random numbers Part III, Methods of computational statistics Graphical methods in computational statistics Tools for identification of structure in data Estimation of functions Monte Carlo methods for statistical inference Data randomization, partitioning, and augmentation Bootstrap methods Part IV, Exploring data density and relationships Estimation of probability density functions using parametric models Nonparametric estimation of probability density functions Statistical learning and data mining Statistical models of dependencies

rawTOC:
Part I, Preliminaries. Mathematical and statistical preliminaries \\ Part II, Statistical computing \\ Computer storage and arithmetic \\ algorithm and programming \\ Approximation of functions and numerical quadrature \\ Numerical linear algebra \\ Solution of nonlinear equations and optimization \\ Generation of random numbers \\ Part III, Methods of computational statistics \\ Graphical methods in computational statistics \\ Tools for identification of structure in data \\ Estimation of functions \\ Monte Carlo methods for statistical inference \\ Data randomization, partitioning, and augmentation \\ Bootstrap methods \\ Part IV, Exploring data density and relationships \\ Estimation of probability density functions using parametric models \\ Nonparametric estimation of probability density functions \\ Statistical learning and data mining \\ Statistical models of dependencies

entry:
@InCollection{Gentle:2009:CSA,
  author =       "James E. Gentle",
  booktitle =    "Computational Statistics",
  title =        "Computer Storage and Arithmetic",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  bookpages =    "xxi + 727",
  pages =        "85--105",
  year =         "2009",
  DOI =          "https://doi.org/10.1007/978-0-387-98144-4_2",
  ISBN =         "0-387-98143-8 (print), 0-387-98144-6 (electronic)",
  ISBN-13 =      "978-0-387-98143-7 (print), 978-0-387-98144-4
                 (electronic)",
  LCCN =         "QA276.4 .G46 2009",
  bibdate =      "Mon May 06 17:36:21 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "Statistics and Computing",
  URL =          "http://link.springer.com/chapter/10.1007/978-0-387-98144-4_2",
  acknowledgement = ack-nhfb,
  tableofcontents = "Part I, Preliminaries. Mathematical and statistical
                 preliminaries \\
                 Part II, Statistical computing \\
                 Computer storage and arithmetic \\
                 algorithm and programming \\
                 Approximation of functions and numerical quadrature \\
                 Numerical linear algebra \\
                 Solution of nonlinear equations and optimization \\
                 Generation of random numbers \\
                 Part III, Methods of computational statistics \\
                 Graphical methods in computational statistics \\
                 Tools for identification of structure in data \\
                 Estimation of functions \\
                 Monte Carlo methods for statistical inference \\
                 Data randomization, partitioning, and augmentation \\
                 Bootstrap methods \\
                 Part IV, Exploring data density and relationships \\
                 Estimation of probability density functions using
                 parametric models \\
                 Nonparametric estimation of probability density
                 functions \\
                 Statistical learning and data mining \\
                 Statistical models of dependencies",
}


bibtype: inproceedings
filename: fparith.bib
label: Gonzalez-Navarro:2009:CDB
author: Sonia Gonzalez-Navarro and Alberto Nannarelli and Michael J. Schulte and Charles Tsen
title: A combined decimal and binary floating-point divider
crossref: Matthews:2009:CRF
pages: 930--934
year: 2009
DOI: https://doi.org/10.1109/ACSSC.2009.5470014
bibdate: Thu Feb 17 08:16:50 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.17 08:16:50 ???
acknowledgement: ack-nhfb
rawauthor: Sonia Gonzalez-Navarro and Alberto Nannarelli and Michael J. Schulte and Charles Tsen
rawtitle: A combined decimal and binary floating-point divider
abstract:
In this paper, we present the hardware design of a combined decimal and binary floating-point divider, based on specifications in the IEEE 754-2008 Standard for Floating-point Arithmetic. In contrast to most recent decimal divider designs, which are based on the Binary Coded Decimal (BCD) encoding, our divider operates on either 64-bit binary encoded decimal floating-point (DFP) numbers or 64-bit binary floating-point (BFP) numbers. The division approach implemented in our design is based on a digit-recurrence algorithm. We describe the hardware resources shared between the two floating-point datatypes and demonstrate that hardware sharing is advantageous. Compared to a standalone DFP divider, the combined divider has the same worst case delay and 17% more area.

rawabstract:
In this paper, we present the hardware design of a combined decimal and binary floating-point divider, based on specifications in the IEEE 754-2008 Standard for Floating-point Arithmetic. In contrast to most recent decimal divider designs, which are based on the Binary Coded Decimal (BCD) encoding, our divider operates on either 64-bit binary encoded decimal floating-point (DFP) numbers or 64-bit binary floating-point (BFP) numbers. The division approach implemented in our design is based on a digit-recurrence algorithm. We describe the hardware resources shared between the two floating-point datatypes and demonstrate that hardware sharing is advantageous. Compared to a standalone DFP divider, the combined divider has the same worst case delay and 17\% more area.

entry:
@InProceedings{Gonzalez-Navarro:2009:CDB,
  author =       "Sonia Gonzalez-Navarro and Alberto Nannarelli and
                 Michael J. Schulte and Charles Tsen",
  title =        "A combined decimal and binary floating-point divider",
  crossref =     "Matthews:2009:CRF",
  pages =        "930--934",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ACSSC.2009.5470014",
  bibdate =      "Thu Feb 17 08:16:50 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper, we present the hardware design of a
                 combined decimal and binary floating-point divider,
                 based on specifications in the IEEE 754-2008 Standard
                 for Floating-point Arithmetic. In contrast to most
                 recent decimal divider designs, which are based on the
                 Binary Coded Decimal (BCD) encoding, our divider
                 operates on either 64-bit binary encoded decimal
                 floating-point (DFP) numbers or 64-bit binary
                 floating-point (BFP) numbers. The division approach
                 implemented in our design is based on a
                 digit-recurrence algorithm. We describe the hardware
                 resources shared between the two floating-point
                 datatypes and demonstrate that hardware sharing is
                 advantageous. Compared to a standalone DFP divider, the
                 combined divider has the same worst case delay and 17\%
                 more area.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Gorgin:2009:FRD
author: Saeid Gorgin and Ghassem Jaberipur
title: Fully Redundant Decimal Arithmetic
crossref: Bruguera:2009:PIS
pages: 145--152
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: Saeid Gorgin and Ghassem Jaberipur
rawtitle: Fully Redundant Decimal Arithmetic
abstract:
Hardware implementation of all the basic radix-10 arithmetic operations is evolving as a new trend in the design and implementation of general purpose digital processors. Redundant representation of partial products and remainders is common in the multiplication and division hardware algorithms, respectively. Carry-free implementation of the more frequent add/subtract operations, with the byproduct of enhancing the speed of multiplication and division, is possible with redundant number representation. However, conversion of redundant results to conventional representations entails slow carry propagation that can be avoided if the results are kept in redundant format for later use as operands of other arithmetic operations. Given that redundant decimal representations, contrary to redundant binary, do not necessarily require extra storage, we are motivated to develop a framework for fully redundant decimal arithmetic, where all operands and results belong to the same redundant decimal number system and can be stored and later used as operands of further decimal operations. In this paper, we present a new faster decimal signed digit add/sub unit and show how it can be efficiently used in the design of decimal multipliers and dividers, where all operands and results are represented with the same redundant digit set $ [ - 7, 7] $.

rawabstract:
Hardware implementation of all the basic radix-10 arithmetic operations is evolving as a new trend in the design and implementation of general purpose digital processors. Redundant representation of partial products and remainders is common in the multiplication and division hardware algorithms, respectively. Carry-free implementation of the more frequent add/subtract operations, with the byproduct of enhancing the speed of multiplication and division, is possible with redundant number representation. However, conversion of redundant results to conventional representations entails slow carry propagation that can be avoided if the results are kept in redundant format for later use as operands of other arithmetic operations. Given that redundant decimal representations, contrary to redundant binary, do not necessarily require extra storage, we are motivated to develop a framework for fully redundant decimal arithmetic, where all operands and results belong to the same redundant decimal number system and can be stored and later used as operands of further decimal operations. In this paper, we present a new faster decimal signed digit add/sub unit and show how it can be efficiently used in the design of decimal multipliers and dividers, where all operands and results are represented with the same redundant digit set $ [ - 7, 7] $.

entry:
@InProceedings{Gorgin:2009:FRD,
  author =       "Saeid Gorgin and Ghassem Jaberipur",
  title =        "Fully Redundant Decimal Arithmetic",
  crossref =     "Bruguera:2009:PIS",
  pages =        "145--152",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Hardware implementation of all the basic radix-10
                 arithmetic operations is evolving as a new trend in the
                 design and implementation of general purpose digital
                 processors. Redundant representation of partial
                 products and remainders is common in the multiplication
                 and division hardware algorithms, respectively.
                 Carry-free implementation of the more frequent
                 add/subtract operations, with the byproduct of
                 enhancing the speed of multiplication and division, is
                 possible with redundant number representation. However,
                 conversion of redundant results to conventional
                 representations entails slow carry propagation that can
                 be avoided if the results are kept in redundant format
                 for later use as operands of other arithmetic
                 operations. Given that redundant decimal
                 representations, contrary to redundant binary, do not
                 necessarily require extra storage, we are motivated to
                 develop a framework for fully redundant decimal
                 arithmetic, where all operands and results belong to
                 the same redundant decimal number system and can be
                 stored and later used as operands of further decimal
                 operations. In this paper, we present a new faster
                 decimal signed digit add/sub unit and show how it can
                 be efficiently used in the design of decimal
                 multipliers and dividers, where all operands and
                 results are represented with the same redundant digit
                 set $ [ - 7, 7] $.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: article
filename: fparith.bib
label: Graillat:2009:AAV
author: Stef Graillat and Philippe Langlois and Nicolas Louvet
title: Algorithms for accurate, validated and fast polynomial evaluation
journal: j-JAPAN-J-INDUST-APPL-MATH
volume: 26
number: 2--3
pages: 191--214
year: 2009
CODEN: JAPJI7
ISSN: 0916-7005 (print), 1868-937x (electronic) OR 09167005 (print), 1868937x (electronic)
bibdate: Sat Jun 4 17:41:42 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.06.04 17:41:42 ???
fjournal: Japan Journal of Industrial and Applied Mathematics
acknowledgement: ack-nhfb
rawauthor: Stef Graillat and Philippe Langlois and Nicolas Louvet
rawtitle: Algorithms for accurate, validated and fast polynomial evaluation
entry:
@Article{Graillat:2009:AAV,
  author =       "Stef Graillat and Philippe Langlois and Nicolas
                 Louvet",
  title =        "Algorithms for accurate, validated and fast polynomial
                 evaluation",
  journal =      j-JAPAN-J-INDUST-APPL-MATH,
  volume =       "26",
  number =       "2--3",
  pages =        "191--214",
  year =         "2009",
  CODEN =        "JAPJI7",
  ISSN =         "0916-7005 (print), 1868-937x (electronic)",
  bibdate =      "Sat Jun 4 17:41:42 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Japan Journal of Industrial and Applied Mathematics",
}


bibtype: article
filename: fparith.bib
label: Graillat:2009:AFP
author: Stef Graillat
title: Accurate Floating-Point Product and Exponentiation
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 7
pages: 994--1000
month: jul
monthnumber: 7
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.215
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:42 MDT 2011
bibtimestamp: 2011.07.04 11:37:42 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4711041
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Stef Graillat
rawtitle: Accurate Floating-Point Product and Exponentiation
abstract:
Several different techniques and softwares intend to improve the accuracy of results computed in a fixed finite precision. Here, we focus on a method to improve the accuracy of the product of floating-point numbers. We show that the computed result is as accurate as if computed in twice the working precision. The algorithm is simple since it only requires addition, subtraction, and multiplication of floating-point numbers in the same working precision as the given data. Such an algorithm can be useful for example to compute the determinant of a triangular matrix and to evaluate a polynomial when represented by the root product form. It can also be used to compute the integer power of a floating-point number.

keywords:
accurate product; computer arithmetic; error analysis; error-free transformations; exponentiation; faithful rounding; finite precision; floating-point arithmetic; numerical algorithms

rawabstract:
Several different techniques and softwares intend to improve the accuracy of results computed in a fixed finite precision. Here, we focus on a method to improve the accuracy of the product of floating-point numbers. We show that the computed result is as accurate as if computed in twice the working precision. The algorithm is simple since it only requires addition, subtraction, and multiplication of floating-point numbers in the same working precision as the given data. Such an algorithm can be useful for example to compute the determinant of a triangular matrix and to evaluate a polynomial when represented by the root product form. It can also be used to compute the integer power of a floating-point number.

entry:
@Article{Graillat:2009:AFP,
  author =       "Stef Graillat",
  title =        "Accurate Floating-Point Product and Exponentiation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "7",
  pages =        "994--1000",
  month =        jul,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.215",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:42 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4711041",
  abstract =     "Several different techniques and softwares intend to
                 improve the accuracy of results computed in a fixed
                 finite precision. Here, we focus on a method to improve
                 the accuracy of the product of floating-point numbers.
                 We show that the computed result is as accurate as if
                 computed in twice the working precision. The algorithm
                 is simple since it only requires addition, subtraction,
                 and multiplication of floating-point numbers in the
                 same working precision as the given data. Such an
                 algorithm can be useful for example to compute the
                 determinant of a triangular matrix and to evaluate a
                 polynomial when represented by the root product form.
                 It can also be used to compute the integer power of a
                 floating-point number.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "accurate product; computer arithmetic; error analysis;
                 error-free transformations; exponentiation; faithful
                 rounding; finite precision; floating-point arithmetic;
                 numerical algorithms",
}


bibtype: article
filename: fparith.bib
label: Gu:2009:SDB
author: Haihua Gu and Dawu Gu
title: Speeding Up the Double-Base Recoding Algorithm of Scalar Multiplication
journal: j-CRYPTOLOGIA
volume: 33
number: 4
pages: 315--320
year: 2009
CODEN: CRYPE6
ISSN: 0161-1194 (print), 1558-1586 (electronic) OR 01611194 (print), 15581586 (electronic)
ISSNL: 0161-1194 OR 01611194
bibdate: Tue Aug 31 11:44:06 MDT 2010
bibtimestamp: 2010.08.31 11:44:06 MDT
fjournal: Cryptologia
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/ucry20
rawauthor: Haihua Gu and Dawu Gu
rawtitle: Speeding Up the Double-Base Recoding Algorithm of Scalar Multiplication
bibsource:
http://www.tandf.co.uk/journals/titles/01611194.asp; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Gu:2009:SDB,
  author =       "Haihua Gu and Dawu Gu",
  title =        "Speeding Up the Double-Base Recoding Algorithm of
                 Scalar Multiplication",
  journal =      j-CRYPTOLOGIA,
  volume =       "33",
  number =       "4",
  pages =        "315--320",
  year =         "2009",
  CODEN =        "CRYPE6",
  ISSN =         "0161-1194 (print), 1558-1586 (electronic)",
  ISSN-L =       "0161-1194",
  bibdate =      "Tue Aug 31 11:44:06 MDT 2010",
  bibsource =    "http://www.tandf.co.uk/journals/titles/01611194.asp;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Cryptologia",
  journal-URL =  "http://www.tandfonline.com/loi/ucry20",
}


bibtype: inproceedings
filename: fparith.bib
label: Guralnik:2009:ISV
author: Elena Guralnik and Ariel J. Birnbaum and Anatoly Koyfman and Avi Kaplan
title: Implementation Specific Verification of Divide and Square Root Instructions
crossref: Bruguera:2009:PIS
pages: 114--121
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: Elena Guralnik and Ariel J. Birnbaum and Anatoly Koyfman and Avi Kaplan
rawtitle: Implementation Specific Verification of Divide and Square Root Instructions
abstract:
Floating point operations such as divide and square root are typically implemented in microcode rather than dedicated logic. Bugs in these operations missed by generic black-box verification tools, were analyzed. This led to the conclusion that the corner cases, in addition to being implementation dependent, could not be characterized in terms of special input or output values in a straightforward manner.par However, many of those cases can be easily generalized for many known implementations. The typical implementation uses a known iterative approximation algorithm, such as the Newton--Raphson method, to calculate the desired result; thus, it is sufficient to produce the corner cases associated with the specific algorithm.par We investigated the following problem: given an iterative algorithm to compute a binary floating point operation, the iteration number, and an interval, find random inputs for the operation that, after the requested iteration, yield a relative error within the specified interval. This paper describes a method to solve this problem. This method was implemented in a floating-point test generator and is currently being used to verify the floating-point units of several processors.

rawabstract:
Floating point operations such as divide and square root are typically implemented in microcode rather than dedicated logic. Bugs in these operations missed by generic black-box verification tools, were analyzed. This led to the conclusion that the corner cases, in addition to being implementation dependent, could not be characterized in terms of special input or output values in a straightforward manner.\par However, many of those cases can be easily generalized for many known implementations. The typical implementation uses a known iterative approximation algorithm, such as the Newton--Raphson method, to calculate the desired result; thus, it is sufficient to produce the corner cases associated with the specific algorithm.\par We investigated the following problem: given an iterative algorithm to compute a binary floating point operation, the iteration number, and an interval, find random inputs for the operation that, after the requested iteration, yield a relative error within the specified interval. This paper describes a method to solve this problem. This method was implemented in a floating-point test generator and is currently being used to verify the floating-point units of several processors.

entry:
@InProceedings{Guralnik:2009:ISV,
  author =       "Elena Guralnik and Ariel J. Birnbaum and Anatoly
                 Koyfman and Avi Kaplan",
  title =        "Implementation Specific Verification of Divide and
                 Square Root Instructions",
  crossref =     "Bruguera:2009:PIS",
  pages =        "114--121",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating point operations such as divide and square
                 root are typically implemented in microcode rather than
                 dedicated logic. Bugs in these operations missed by
                 generic black-box verification tools, were analyzed.
                 This led to the conclusion that the corner cases, in
                 addition to being implementation dependent, could not
                 be characterized in terms of special input or output
                 values in a straightforward manner.\par

                 However, many of those cases can be easily generalized
                 for many known implementations. The typical
                 implementation uses a known iterative approximation
                 algorithm, such as the Newton--Raphson method, to
                 calculate the desired result; thus, it is sufficient to
                 produce the corner cases associated with the specific
                 algorithm.\par

                 We investigated the following problem: given an
                 iterative algorithm to compute a binary floating point
                 operation, the iteration number, and an interval, find
                 random inputs for the operation that, after the
                 requested iteration, yield a relative error within the
                 specified interval. This paper describes a method to
                 solve this problem. This method was implemented in a
                 floating-point test generator and is currently being
                 used to verify the floating-point units of several
                 processors.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: article
filename: fparith.bib
label: Han:2009:ICS
author: Dong-Guk Han and Dooho Choi and Howon Kim
title: Improved Computation of Square Roots in Specific Finite Fields
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 2
pages: 188--196
month: feb
monthnumber: 2
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.201
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:39 MDT 2011
bibtimestamp: 2011.07.04 11:37:39 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4663058
fjournal: IEEE Transactions on Computers
keywords: cryptography; efficient computation; finite fields; square roots
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Dong-Guk Han and Dooho Choi and Howon Kim
rawtitle: Improved Computation of Square Roots in Specific Finite Fields
abstract:
In this paper, we study exponentiation in the specific finite fields $ F_q $ with very special exponents such as those that occur in algorithms for computing square roots. Here, $q$ is a prime power, $ q = p^k $, where $ k > 1 $, and $k$ is odd. Our algorithmic approach improves the corresponding exponentiation resulted from the better rewritten exponent. To the best of our knowledge, it is the first major improvement to the Tonelli--Shanks algorithm, for example, the number of multiplications can be reduced to at least 60 percent on the average when $ p equiv 1 pmod 16 $. Several numerical examples are given that show the speedup of the proposed methods.

rawabstract:
In this paper, we study exponentiation in the specific finite fields $ F_q $ with very special exponents such as those that occur in algorithms for computing square roots. Here, $q$ is a prime power, $ q = p^k $, where $ k > 1 $, and $k$ is odd. Our algorithmic approach improves the corresponding exponentiation resulted from the better rewritten exponent. To the best of our knowledge, it is the first major improvement to the Tonelli--Shanks algorithm, for example, the number of multiplications can be reduced to at least 60 percent on the average when $ p \equiv 1 \pmod 16 $. Several numerical examples are given that show the speedup of the proposed methods.

entry:
@Article{Han:2009:ICS,
  author =       "Dong-Guk Han and Dooho Choi and Howon Kim",
  title =        "Improved Computation of Square Roots in Specific
                 Finite Fields",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "2",
  pages =        "188--196",
  month =        feb,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.201",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4663058",
  abstract =     "In this paper, we study exponentiation in the specific
                 finite fields $ F_q $ with very special exponents such
                 as those that occur in algorithms for computing square
                 roots. Here, $q$ is a prime power, $ q = p^k $, where $
                 k > 1 $, and $k$ is odd. Our algorithmic approach
                 improves the corresponding exponentiation resulted from
                 the better rewritten exponent. To the best of our
                 knowledge, it is the first major improvement to the
                 Tonelli--Shanks algorithm, for example, the number of
                 multiplications can be reduced to at least 60 percent
                 on the average when $ p \equiv 1 \pmod 16 $. Several
                 numerical examples are given that show the speedup of
                 the proposed methods.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "cryptography; efficient computation; finite fields;
                 square roots",
}


bibtype: article
filename: fparith.bib
label: Hariri:2009:BSB
author: A. Hariri and A. Reyhani-Masoleh
title: Bit-Serial and Bit-Parallel Montgomery Multiplication and Squaring over $ mathrm GF(2^m) $
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 10
pages: 1332--1345
month: oct
monthnumber: 10
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2009.70
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:43 MDT 2011
bibtimestamp: 2011.07.04 11:37:43 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4912195
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Hariri and A. Reyhani-Masoleh
rawtitle: Bit-Serial and Bit-Parallel {Montgomery} Multiplication and Squaring over {$ \mathrm {GF}(2^m) $}
entry:
@Article{Hariri:2009:BSB,
  author =       "A. Hariri and A. Reyhani-Masoleh",
  title =        "Bit-Serial and Bit-Parallel {Montgomery}
                 Multiplication and Squaring over {$ \mathrm {GF}(2^m)
                 $}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "10",
  pages =        "1332--1345",
  month =        oct,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2009.70",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:43 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4912195",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Harrison:2009:DTB
author: John Harrison
title: Decimal Transcendentals via Binary
crossref: Bruguera:2009:PIS
pages: 187--194
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: John Harrison
rawtitle: Decimal Transcendentals via Binary
abstract:
We describe the design and implementation of a comprehensive library of transcendental functions for the new IEEE decimal floating-point formats. In principle, such functions are very much analogous to their binary counterparts, though with a few additional subtleties connected with `scale' (preferred exponent). But our approach has been not to employ direct techniques, but rather to re-use existing binary functions as much as possible, both for greater efficiency and ease of implementation. For some functions the most straightforward approach (convert from decimal to binary, perform binary operation, convert back) works well. In many cases, however, these are insufficiently accurate, and subtler approaches must be used.

rawabstract:
We describe the design and implementation of a comprehensive library of transcendental functions for the new IEEE decimal floating-point formats. In principle, such functions are very much analogous to their binary counterparts, though with a few additional subtleties connected with `scale' (preferred exponent). But our approach has been not to employ direct techniques, but rather to re-use existing binary functions as much as possible, both for greater efficiency and ease of implementation. For some functions the most straightforward approach (convert from decimal to binary, perform binary operation, convert back) works well. In many cases, however, these are insufficiently accurate, and subtler approaches must be used.

entry:
@InProceedings{Harrison:2009:DTB,
  author =       "John Harrison",
  title =        "Decimal Transcendentals via Binary",
  crossref =     "Bruguera:2009:PIS",
  pages =        "187--194",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We describe the design and implementation of a
                 comprehensive library of transcendental functions for
                 the new IEEE decimal floating-point formats. In
                 principle, such functions are very much analogous to
                 their binary counterparts, though with a few additional
                 subtleties connected with `scale' (preferred exponent).
                 But our approach has been not to employ direct
                 techniques, but rather to re-use existing binary
                 functions as much as possible, both for greater
                 efficiency and ease of implementation. For some
                 functions the most straightforward approach (convert
                 from decimal to binary, perform binary operation,
                 convert back) works well. In many cases, however, these
                 are insufficiently accurate, and subtler approaches
                 must be used.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: inproceedings
filename: fparith.bib
label: Harrison:2009:FAB
author: John Harrison
title: Fast and Accurate Bessel Function Computation
crossref: Bruguera:2009:PIS
pages: 104--113
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: $J0(x), J1(1), Y0(x), Y1(1)$; ARITH-19; ordinary Bessel functions of the first and second kinds
acknowledgement: ack-nhfb
rawauthor: John Harrison
rawtitle: Fast and Accurate {Bessel} Function Computation
abstract:
The Bessel functions are considered relatively difficult to compute. Although they have a simple power series expansion that is everywhere convergent, they exhibit approximately periodic behavior which makes the direct use of the power series impractically slow and numerically unstable. We describe an alternative method based on systematic expansion around the zeros, refining existing techniques based on Hankel expansions, which mostly avoids the use of multiprecision arithmetic while yielding accurate results.

rawabstract:
The Bessel functions are considered relatively difficult to compute. Although they have a simple power series expansion that is everywhere convergent, they exhibit approximately periodic behavior which makes the direct use of the power series impractically slow and numerically unstable. We describe an alternative method based on systematic expansion around the zeros, refining existing techniques based on Hankel expansions, which mostly avoids the use of multiprecision arithmetic while yielding accurate results.

entry:
@InProceedings{Harrison:2009:FAB,
  author =       "John Harrison",
  title =        "Fast and Accurate {Bessel} Function Computation",
  crossref =     "Bruguera:2009:PIS",
  pages =        "104--113",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Bessel functions are considered relatively
                 difficult to compute. Although they have a simple power
                 series expansion that is everywhere convergent, they
                 exhibit approximately periodic behavior which makes the
                 direct use of the power series impractically slow and
                 numerically unstable. We describe an alternative method
                 based on systematic expansion around the zeros,
                 refining existing techniques based on Hankel
                 expansions, which mostly avoids the use of
                 multiprecision arithmetic while yielding accurate
                 results.",
  acknowledgement = ack-nhfb,
  keywords =     "$J0(x), J1(1), Y0(x), Y1(1)$; ARITH-19; ordinary
                 Bessel functions of the first and second kinds",
}


bibtype: inproceedings
filename: fparith.bib
label: Hasan:2009:SSC
author: M. A. Hasan and C. Negre
crossref: Bruguera:2009:PIS
pages: 67--75
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19; binary field; double basis; multiplication; subquadratic complexity
acknowledgement: ack-nhfb
rawauthor: M. A. Hasan and C. Negre
title:
Subquadratic Space Complexity Multiplier for a Class of Binary Fields Using Toeplitz Matrix Approach

abstract:
In the recent past, subquadratic space complexity multipliers have been proposed for binary fields defined by irreducible trinomials and some specific pentanomials. For such multipliers, alternative irreducible polynomials can also be used, in particular, nearly all one polynomials (NAOPs) seem to be better than pentanomials (see [7]). For improved efficiency, multiplication modulo an NAOP is performed via modulo a quadrinomial whose degree is one more than that of the original NAOP. In this paper, we present a Toeplitz matrix-vector product based approach for multiplication modulo a quadrinomial. We obtain a fully parallel (nonsequential) multiplier with a subquadratic space complexity, which has the same order of space complexity as that of Fan and Hasan [4].par The Toeplitz matrix-vector product based approach is also interesting in the design of sequential multipliers. In this paper, we present two such multipliers: one with bit serial output and the other bit parallel output.

rawabstract:
In the recent past, subquadratic space complexity multipliers have been proposed for binary fields defined by irreducible trinomials and some specific pentanomials. For such multipliers, alternative irreducible polynomials can also be used, in particular, nearly all one polynomials (NAOPs) seem to be better than pentanomials (see [7]). For improved efficiency, multiplication modulo an NAOP is performed via modulo a quadrinomial whose degree is one more than that of the original NAOP. In this paper, we present a Toeplitz matrix-vector product based approach for multiplication modulo a quadrinomial. We obtain a fully parallel (nonsequential) multiplier with a subquadratic space complexity, which has the same order of space complexity as that of Fan and Hasan [4].\par The Toeplitz matrix-vector product based approach is also interesting in the design of sequential multipliers. In this paper, we present two such multipliers: one with bit serial output and the other bit parallel output.

rawtitle:
Subquadratic Space Complexity Multiplier for a Class of Binary Fields Using {Toeplitz} Matrix Approach

entry:
@InProceedings{Hasan:2009:SSC,
  author =       "M. A. Hasan and C. Negre",
  title =        "Subquadratic Space Complexity Multiplier for a Class
                 of Binary Fields Using {Toeplitz} Matrix Approach",
  crossref =     "Bruguera:2009:PIS",
  pages =        "67--75",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In the recent past, subquadratic space complexity
                 multipliers have been proposed for binary fields
                 defined by irreducible trinomials and some specific
                 pentanomials. For such multipliers, alternative
                 irreducible polynomials can also be used, in
                 particular, nearly all one polynomials (NAOPs) seem to
                 be better than pentanomials (see [7]). For improved
                 efficiency, multiplication modulo an NAOP is performed
                 via modulo a quadrinomial whose degree is one more than
                 that of the original NAOP. In this paper, we present a
                 Toeplitz matrix-vector product based approach for
                 multiplication modulo a quadrinomial. We obtain a fully
                 parallel (nonsequential) multiplier with a subquadratic
                 space complexity, which has the same order of space
                 complexity as that of Fan and Hasan [4].\par

                 The Toeplitz matrix-vector product based approach is
                 also interesting in the design of sequential
                 multipliers. In this paper, we present two such
                 multipliers: one with bit serial output and the other
                 bit parallel output.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19; binary field; double basis; multiplication;
                 subquadratic complexity",
}


bibtype: article
filename: fparith.bib
label: Hinek:2009:ALS
author: M. Jason Hinek and Charles C. Y. Lam
title: Another look at some fast modular arithmetic methods
journal: j-J-MATH-CRYPTOL
volume: 3
number: 2
pages: 165--174
year: 2009
DOI: https://doi.org/10.1515/JMC.2009.008
ISSN: 1862-2976 (print), 1862-2984 (electronic) OR 18622976 (print), 18622984 (electronic)
ISSNL: 1862-2976 OR 18622976
MRclass: 68W40 (94A60)
MRnumber: 2590262
bibdate: Fri Mar 17 08:36:49 2017
bibtimestamp: 2017.03.17 08:36:49 ???
fjournal: Journal of Mathematical Cryptology
acknowledgement: ack-nhfb
journalURL: http://www.degruyter.com/view/j/jmc
rawauthor: M. Jason Hinek and Charles C. Y. Lam
rawtitle: Another look at some fast modular arithmetic methods
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jmathcryptol.bib

entry:
@Article{Hinek:2009:ALS,
  author =       "M. Jason Hinek and Charles C. Y. Lam",
  title =        "Another look at some fast modular arithmetic methods",
  journal =      j-J-MATH-CRYPTOL,
  volume =       "3",
  number =       "2",
  pages =        "165--174",
  year =         "2009",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1515/JMC.2009.008",
  ISSN =         "1862-2976 (print), 1862-2984 (electronic)",
  ISSN-L =       "1862-2976",
  MRclass =      "68W40 (94A60)",
  MRnumber =     "2590262",
  bibdate =      "Fri Mar 17 08:36:49 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jmathcryptol.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Mathematical Cryptology",
  journal-URL =  "http://www.degruyter.com/view/j/jmc",
}


bibtype: article
filename: fparith.bib
label: Ho:2009:FPF
author: C. H. Ho and C. W. Yu and P. Leong and W. Luk and S. J. E. Wilton
title: Floating-point FPGA: architecture and modeling
journal: j-IEEE-TRANS-VLSI-SYST
volume: 17
number: 12
pages: 1709--1718
year: 2009
CODEN: IEVSE9
DOI: https://doi.org/10.1109/TVLSI.2008.2006616
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Thu Mar 24 20:51:13 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.03.24 20:51:13 ???
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: C. H. Ho and C. W. Yu and P. Leong and W. Luk and S. J. E. Wilton
rawtitle: Floating-point {FPGA}: architecture and modeling
entry:
@Article{Ho:2009:FPF,
  author =       "C. H. Ho and C. W. Yu and P. Leong and W. Luk and S.
                 J. E. Wilton",
  title =        "Floating-point {FPGA}: architecture and modeling",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "17",
  number =       "12",
  pages =        "1709--1718",
  year =         "2009",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2008.2006616",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Thu Mar 24 20:51:13 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}


bibtype: book
filename: fparith.bib
label: ISO:2009:IIT
author: International Organization for Standardization
publisher: pub-ISO
address: pub-ISO:adr
pages: 1709--1718
year: 2009
bibdate: Thu Nov 25 08:56:44 2010
bibsource: http://www.iso.org/iso/search.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.11.25 08:56:44 ???
series: Technical report
URL: http://www.iso.org/iso/iso_catalogue/catalogue_tc/catalogue_detail.htm?csnumber=38842
subject: programming languages (electronic computers)
acknowledgement: ack-nhfb
rawauthor: {International Organization for Standardization}
title:
ISO/IEC TR 24732:2009 Information technology --- Programming languages, their environments and system software interfaces --- Extension for the programming language C to support decimal floating-point arithmetic

rawtitle:
{ISO/IEC TR 24732:2009} Information technology --- Programming languages, their environments and system software interfaces --- Extension for the programming language {C} to support decimal floating-point arithmetic

entry:
@Book{ISO:2009:IIT,
  author =       "{International Organization for Standardization}",
  title =        "{ISO/IEC TR 24732:2009} Information technology ---
                 Programming languages, their environments and system
                 software interfaces --- Extension for the programming
                 language {C} to support decimal floating-point
                 arithmetic",
  publisher =    pub-ISO,
  address =      pub-ISO:adr,
  year =         "2009",
  LCCN =         "????",
  bibdate =      "Thu Nov 25 08:56:44 2010",
  bibsource =    "http://www.iso.org/iso/search.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "Technical report",
  URL =          "http://www.iso.org/iso/iso_catalogue/catalogue_tc/catalogue_detail.htm?csnumber=38842",
  acknowledgement = ack-nhfb,
  subject =      "programming languages (electronic computers)",
}


bibtype: article
filename: fparith.bib
label: Jaberipur:2009:ISP
author: G. Jaberipur and A. Kaivani
title: Improving the Speed of Parallel Decimal Multiplication
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 11
pages: 1539--1552
month: nov
monthnumber: 11
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2009.110
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:44 MDT 2011
bibtimestamp: 2011.07.04 11:37:44 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5184812
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: G. Jaberipur and A. Kaivani
rawtitle: Improving the Speed of Parallel Decimal Multiplication
entry:
@Article{Jaberipur:2009:ISP,
  author =       "G. Jaberipur and A. Kaivani",
  title =        "Improving the Speed of Parallel Decimal
                 Multiplication",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "11",
  pages =        "1539--1552",
  month =        nov,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2009.110",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:44 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5184812",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Jaberipur:2009:UAD
author: Ghassem Jaberipur and Behrooz Parhami
crossref: Bruguera:2009:PIS
pages: 57--64
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: Ghassem Jaberipur and Behrooz Parhami
title:
Unified Approach to the Design of Modulo-$ (2^n pm 1) $ Adders Based on Signed-LSB Representation of Residues

abstract:
Moduli of the form $ 2 n pm 1 $, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs for modulo-$ 2 n pm 1 $ adders has rendered the latency of such adders quite competitive with ordinary adders. The next logical step is to approach the problem in a unified and systematic manner that does not require each design to be taken up from scratch and to undergo the error-prone and labor-intensive optimization for high speed and low power dissipation. Accordingly, we devise a new redundant representation of mod-$ 2 n pm 1 $ residues that allows ordinary fast adders and a small amount of peripheral logic to be used for mod-$ 2 n pm 1 $ addition. Advantages of the building-block approach include shorter design time, easier exploration of the design space (area / speed / power tradeoffs), and greater confidence in the correctness of the resulting circuits. Advantages of the unified design include the possibility of fault-tolerant and gracefully degrading RNS circuit realizations with fairly low hardware redundancy.

rawabstract:
Moduli of the form $ 2 n \pm 1 $, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs for modulo-$ 2 n \pm 1 $ adders has rendered the latency of such adders quite competitive with ordinary adders. The next logical step is to approach the problem in a unified and systematic manner that does not require each design to be taken up from scratch and to undergo the error-prone and labor-intensive optimization for high speed and low power dissipation. Accordingly, we devise a new redundant representation of mod-$ 2 n \pm 1 $ residues that allows ordinary fast adders and a small amount of peripheral logic to be used for mod-$ 2 n \pm 1 $ addition. Advantages of the building-block approach include shorter design time, easier exploration of the design space (area\slash speed\slash power tradeoffs), and greater confidence in the correctness of the resulting circuits. Advantages of the unified design include the possibility of fault-tolerant and gracefully degrading RNS circuit realizations with fairly low hardware redundancy.

rawtitle:
Unified Approach to the Design of Modulo-$ (2^n \pm 1) $ Adders Based on Signed-{LSB} Representation of Residues

entry:
@InProceedings{Jaberipur:2009:UAD,
  author =       "Ghassem Jaberipur and Behrooz Parhami",
  title =        "Unified Approach to the Design of Modulo-$ (2^n \pm 1)
                 $ Adders Based on Signed-{LSB} Representation of
                 Residues",
  crossref =     "Bruguera:2009:PIS",
  pages =        "57--64",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Moduli of the form $ 2 n \pm 1 $, which greatly
                 simplify certain arithmetic operations in residue
                 number systems (RNS), have been of longstanding
                 interest. A steady stream of designs for modulo-$ 2 n
                 \pm 1 $ adders has rendered the latency of such adders
                 quite competitive with ordinary adders. The next
                 logical step is to approach the problem in a unified
                 and systematic manner that does not require each design
                 to be taken up from scratch and to undergo the
                 error-prone and labor-intensive optimization for high
                 speed and low power dissipation. Accordingly, we devise
                 a new redundant representation of mod-$ 2 n \pm 1 $
                 residues that allows ordinary fast adders and a small
                 amount of peripheral logic to be used for mod-$ 2 n \pm
                 1 $ addition. Advantages of the building-block approach
                 include shorter design time, easier exploration of the
                 design space (area\slash speed\slash power tradeoffs),
                 and greater confidence in the correctness of the
                 resulting circuits. Advantages of the unified design
                 include the possibility of fault-tolerant and
                 gracefully degrading RNS circuit realizations with
                 fairly low hardware redundancy.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: inproceedings
filename: fparith.bib
label: James:2009:HPL
author: R. K. James and K. P. Jacob and S. Sasi
title: High performance, low latency double digit decimal multiplier on ASIC and FPGA
crossref: Abraham:2009:WCN
pages: 1445--1450
year: 2009
DOI: https://doi.org/10.1109/NABIC.2009.5393703
bibdate: Thu Feb 17 08:43:10 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.17 08:43:10 ???
acknowledgement: ack-nhfb
rawauthor: R. K. James and K. P. Jacob and S. Sasi
rawtitle: High performance, low latency double digit decimal multiplier on {ASIC} and {FPGA}
abstract:
Decimal multiplication is an integral part of financial, commercial, and Internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754-2008 standard.

rawabstract:
Decimal multiplication is an integral part of financial, commercial, and Internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754-2008 standard.

entry:
@InProceedings{James:2009:HPL,
  author =       "R. K. James and K. P. Jacob and S. Sasi",
  title =        "High performance, low latency double digit decimal
                 multiplier on {ASIC} and {FPGA}",
  crossref =     "Abraham:2009:WCN",
  pages =        "1445--1450",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/NABIC.2009.5393703",
  bibdate =      "Thu Feb 17 08:43:10 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Decimal multiplication is an integral part of
                 financial, commercial, and Internet-based computations.
                 This paper presents a novel double digit decimal
                 multiplication (DDDM) technique that offers low latency
                 and high throughput. This design performs two digit
                 multiplications simultaneously in one clock cycle.
                 Double digit fixed point decimal multipliers for
                 7digit, 16 digit and 34 digit are simulated using
                 Leonardo Spectrum from Mentor Graphics Corporation
                 using ASIC Library. The paper also presents area and
                 delay comparisons for these fixed point multipliers on
                 Xilinx, Altera, Actel and Quick logic FPGAs. This
                 multiplier design can be extended to support decimal
                 floating point multiplication for IEEE 754-2008
                 standard.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Jeannerod:2009:NBF
crossref: Bruguera:2009:PIS
pages: 95--103
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
acknowledgement: ack-nhfb
author:
Claude-Pierre Jeannerod and Herve Knochel and Christophe Monat and Guillaume Revy and Gilles Villard

title:
A New Binary Floating-Point Division Algorithm and Its Software Implementation on the ST231 Processor

abstract:
This paper deals with the design and implementation of low latency software for binary floating-point division with correct rounding to nearest. The approach we present here targets a VLIW integer processor of the ST200 family, and is based on fast and accurate programs for evaluating some particular bivariate polynomials. We start by giving approximation and evaluation error conditions that are sufficient to ensure correct rounding. Then we describe the heuristics used to generate such evaluation programs, as well as those used to automatically validate their accuracy. Finally, we propose, for the binary32 format, a complete C implementation of the resulting division algorithm. With the ST200 compiler and compared to previous implementations, the speed-up observed with our approach is by a factor of almost 1.8.

keywords:
ARITH-19; binary floating-point division; code generation and validation; correct rounding; polynomial evaluation; VLIW integer processor

rawabstract:
This paper deals with the design and implementation of low latency software for binary floating-point division with correct rounding to nearest. The approach we present here targets a VLIW integer processor of the ST200 family, and is based on fast and accurate programs for evaluating some particular bivariate polynomials. We start by giving approximation and evaluation error conditions that are sufficient to ensure correct rounding. Then we describe the heuristics used to generate such evaluation programs, as well as those used to automatically validate their accuracy. Finally, we propose, for the binary32 format, a complete C implementation of the resulting division algorithm. With the ST200 compiler and compared to previous implementations, the speed-up observed with our approach is by a factor of almost 1.8.

rawauthor:
Claude-Pierre Jeannerod and Herv{\'e} Knochel and Christophe Monat and Guillaume Revy and Gilles Villard

rawtitle:
A New Binary Floating-Point Division Algorithm and Its Software Implementation on the {ST231} Processor

entry:
@InProceedings{Jeannerod:2009:NBF,
  author =       "Claude-Pierre Jeannerod and Herv{\'e} Knochel and
                 Christophe Monat and Guillaume Revy and Gilles
                 Villard",
  title =        "A New Binary Floating-Point Division Algorithm and Its
                 Software Implementation on the {ST231} Processor",
  crossref =     "Bruguera:2009:PIS",
  pages =        "95--103",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper deals with the design and implementation of
                 low latency software for binary floating-point division
                 with correct rounding to nearest. The approach we
                 present here targets a VLIW integer processor of the
                 ST200 family, and is based on fast and accurate
                 programs for evaluating some particular bivariate
                 polynomials. We start by giving approximation and
                 evaluation error conditions that are sufficient to
                 ensure correct rounding. Then we describe the
                 heuristics used to generate such evaluation programs,
                 as well as those used to automatically validate their
                 accuracy. Finally, we propose, for the binary32 format,
                 a complete C implementation of the resulting division
                 algorithm. With the ST200 compiler and compared to
                 previous implementations, the speed-up observed with
                 our approach is by a factor of almost 1.8.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19; binary floating-point division; code
                 generation and validation; correct rounding; polynomial
                 evaluation; VLIW integer processor",
}


bibtype: article
filename: fparith.bib
label: Jiang:2009:FPA
author: D. Jiang and N. F. Stewart
title: Floating-Point Arithmetic for Computational Geometry Problems with Uncertain Data
journal: j-INT-J-COMPUT-GEOM-APPL
volume: 19
number: 4
pages: 371--385
month: aug
monthnumber: 8
year: 2009
CODEN: IJCAEV
DOI: https://doi.org/10.1142/S0218195909003015
ISSN: 0218-1959 OR 02181959
bibdate: Mon Aug 30 10:25:06 MDT 2010
bibsource: http://ejournals.wspc.com.sg/ijcga/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.08.30 10:25:06 MDT
fjournal: International journal of computational geometry and applications
acknowledgement: ack-nhfb
journalURL: http://www.worldscientific.com/loi/ijcga
rawauthor: D. Jiang and N. F. Stewart
rawtitle: Floating-Point Arithmetic for Computational Geometry Problems with Uncertain Data
entry:
@Article{Jiang:2009:FPA,
  author =       "D. Jiang and N. F. Stewart",
  title =        "Floating-Point Arithmetic for Computational Geometry
                 Problems with Uncertain Data",
  journal =      j-INT-J-COMPUT-GEOM-APPL,
  volume =       "19",
  number =       "4",
  pages =        "371--385",
  month =        aug,
  year =         "2009",
  CODEN =        "IJCAEV",
  DOI =          "https://doi.org/10.1142/S0218195909003015",
  ISSN =         "0218-1959",
  bibdate =      "Mon Aug 30 10:25:06 MDT 2010",
  bibsource =    "http://ejournals.wspc.com.sg/ijcga/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "International journal of computational geometry and
                 applications",
  journal-URL =  "http://www.worldscientific.com/loi/ijcga",
  xxnote =       "Check downcased title string??",
}


bibtype: inproceedings
filename: fparith.bib
label: Kaivola:2009:RTF
crossref: Bouajjani:2009:CAV
pages: 414--429
year: 2009
DOI: https://doi.org/10.1007/978-3-642-02658-4_32
ISBN: 3-642-02658-3 OR 3642026583
ISBN13: 978-3-642-02658-4 OR 9783642026584
bibdate: Fri Dec 8 13:33:33 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 13:33:33 ???
acknowledgement: ack-nhfb
author:
Roope Kaivola and Rajnish Ghughal and Naren Narasimhan and Amber Telfer and Jesse Whittemore and Sudhindra Pandav and Anna Slobodova and Christopher Taylor and Vladimir Frolov and Erik Reeber and Armaghan Naik

title:
Replacing Testing with Formal Verification in Intelreg CoreTM i7 Processor Execution Engine Validation

rawauthor:
Roope Kaivola and Rajnish Ghughal and Naren Narasimhan and Amber Telfer and Jesse Whittemore and Sudhindra Pandav and Anna Slobodov{\'a} and Christopher Taylor and Vladimir Frolov and Erik Reeber and Armaghan Naik

rawtitle:
Replacing Testing with Formal Verification in {Intel{\reg} Core{\TM} i7} Processor Execution Engine Validation

entry:
@InProceedings{Kaivola:2009:RTF,
  author =       "Roope Kaivola and Rajnish Ghughal and Naren Narasimhan
                 and Amber Telfer and Jesse Whittemore and Sudhindra
                 Pandav and Anna Slobodov{\'a} and Christopher Taylor
                 and Vladimir Frolov and Erik Reeber and Armaghan Naik",
  title =        "Replacing Testing with Formal Verification in
                 {Intel{\reg} Core{\TM} i7} Processor Execution Engine
                 Validation",
  crossref =     "Bouajjani:2009:CAV",
  pages =        "414--429",
  year =         "2009",
  DOI =          "https://doi.org/10.1007/978-3-642-02658-4_32",
  ISBN =         "3-642-02658-3",
  ISBN-13 =      "978-3-642-02658-4",
  bibdate =      "Fri Dec 8 13:33:33 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Keaton:2009:IIR
title: As-if Infinitely Ranged Integer Model
type: Technical Note
number: CMU/SEI-2009-TN-023
institution: Carnegie-Mellon University Software Engineering Institute
address: Pittsburgh, PA, USA
pages: 414--429
month: jul
monthnumber: 7
year: 2009
bibdate: Fri Aug 23 08:27:41 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.08.23 08:27:41 ???
keywords: integer overflow; integer wraparound
acknowledgement: ack-nhfb
rawtitle: As-if Infinitely Ranged Integer Model
author:
David Keaton and Thomas Plum and Robert C. Seacord and David Svoboda and Alex Volkovitsky and Timothy Wilson

URL:
https://resources.sei.cmu.edu/asset_files/TechnicalNote/2009_004_001_15074.pdf; https://resources.sei.cmu.edu/library/asset-view.cfm?assetid=9019

abstract:
Integer overflow and wraparound are major causes of software vulnerabilities in the C and C++ programming languages. In this paper we present the as-if infinitely ranged (AIR) integer model, which provides a largely automated mechanism for eliminating integer overflow and integer truncation. The AIR integer model either produces a value equivalent to one that would have been obtained using infinitely ranged integers or results in a runtime constraint violation. Unlike previous integer models, AIR integers do not require precise traps, and consequently do not break or inhibit most existing optimizations.

rawabstract:
Integer overflow and wraparound are major causes of software vulnerabilities in the C and C++ programming languages. In this paper we present the as-if infinitely ranged (AIR) integer model, which provides a largely automated mechanism for eliminating integer overflow and integer truncation. The AIR integer model either produces a value equivalent to one that would have been obtained using infinitely ranged integers or results in a runtime constraint violation. Unlike previous integer models, AIR integers do not require precise traps, and consequently do not break or inhibit most existing optimizations.

rawauthor:
David Keaton and Thomas Plum and Robert C. Seacord and David Svoboda and Alex Volkovitsky and Timothy Wilson

entry:
@TechReport{Keaton:2009:IIR,
  author =       "David Keaton and Thomas Plum and Robert C. Seacord and
                 David Svoboda and Alex Volkovitsky and Timothy Wilson",
  title =        "As-if Infinitely Ranged Integer Model",
  type =         "Technical Note",
  number =       "CMU/SEI-2009-TN-023",
  institution =  "Carnegie-Mellon University Software Engineering
                 Institute",
  address =      "Pittsburgh, PA, USA",
  month =        jul,
  year =         "2009",
  bibdate =      "Fri Aug 23 08:27:41 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://resources.sei.cmu.edu/asset_files/TechnicalNote/2009_004_001_15074.pdf;
                 https://resources.sei.cmu.edu/library/asset-view.cfm?assetid=9019",
  abstract =     "Integer overflow and wraparound are major causes of
                 software vulnerabilities in the C and C++ programming
                 languages. In this paper we present the as-if
                 infinitely ranged (AIR) integer model, which provides a
                 largely automated mechanism for eliminating integer
                 overflow and integer truncation. The AIR integer model
                 either produces a value equivalent to one that would
                 have been obtained using infinitely ranged integers or
                 results in a runtime constraint violation. Unlike
                 previous integer models, AIR integers do not require
                 precise traps, and consequently do not break or inhibit
                 most existing optimizations.",
  acknowledgement = ack-nhfb,
  keywords =     "integer overflow; integer wraparound",
}


bibtype: article
filename: fparith.bib
label: Kim:2009:FPU
author: Donghyun Kim and Lee-Sup Kim
title: A Floating-Point Unit for $4$D Vector Inner Product with Reduced Latency
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 7
pages: 890--901
month: jul
monthnumber: 7
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.210
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:42 MDT 2011
bibtimestamp: 2011.07.04 11:37:42 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4674343
fjournal: IEEE Transactions on Computers
keywords: 3D graphics; DP4; floating point arithmetic; graphics processors; vector inner product
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Donghyun Kim and Lee-Sup Kim
rawtitle: A Floating-Point Unit for {$4$D} Vector Inner Product with Reduced Latency
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib

abstract:
This paper presents the algorithm and implementation of a new high-performance functional unit for floating-point four-dimensional vector inner product (4D dot product; DP4), which is most frequently performed in 3D graphics application. The proposed IEEE-compliant DP4 unit computes $ rm Z = rm AB + rm CD + rm EF + rm GH $ in one path and keeps the intermediate rounding by IEEE-754 rounding to nearest even. The intermediate rounding is merged with shift alignment, and intermediate carry-propagated addition and normalization are omitted to reduce latency in the proposed architecture. The proposed DP4 unit is implemented with 0.18-$ mu $ m CMOS technology and has 12.8-ns critical path delay, which is reduced by 45.5 percent compared to a previous DP4 implementation using discrete multipliers and adders. The proposed DP4 unit also reduces the cycle time of 3D graphics applications by 12.4 percent on the average compared to the usual 3D graphics FPU based on four-way multiply-add-fused units.

rawabstract:
This paper presents the algorithm and implementation of a new high-performance functional unit for floating-point four-dimensional vector inner product (4D dot product; DP4), which is most frequently performed in 3D graphics application. The proposed IEEE-compliant DP4 unit computes $ {\rm Z} = {\rm AB} + {rm CD} + {\rm EF} + {\rm GH} $ in one path and keeps the intermediate rounding by IEEE-754 rounding to nearest even. The intermediate rounding is merged with shift alignment, and intermediate carry-propagated addition and normalization are omitted to reduce latency in the proposed architecture. The proposed DP4 unit is implemented with 0.18-$ \mu $ m CMOS technology and has 12.8-ns critical path delay, which is reduced by 45.5 percent compared to a previous DP4 implementation using discrete multipliers and adders. The proposed DP4 unit also reduces the cycle time of 3D graphics applications by 12.4 percent on the average compared to the usual 3D graphics FPU based on four-way multiply-add-fused units.

entry:
@Article{Kim:2009:FPU,
  author =       "Donghyun Kim and Lee-Sup Kim",
  title =        "A Floating-Point Unit for {$4$D} Vector Inner Product
                 with Reduced Latency",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "7",
  pages =        "890--901",
  month =        jul,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.210",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:42 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4674343",
  abstract =     "This paper presents the algorithm and implementation
                 of a new high-performance functional unit for
                 floating-point four-dimensional vector inner product
                 (4D dot product; DP4), which is most frequently
                 performed in 3D graphics application. The proposed
                 IEEE-compliant DP4 unit computes $ {\rm Z} = {\rm AB} +
                 {rm CD} + {\rm EF} + {\rm GH} $ in one path and keeps
                 the intermediate rounding by IEEE-754 rounding to
                 nearest even. The intermediate rounding is merged with
                 shift alignment, and intermediate carry-propagated
                 addition and normalization are omitted to reduce
                 latency in the proposed architecture. The proposed DP4
                 unit is implemented with 0.18-$ \mu $ m CMOS technology
                 and has 12.8-ns critical path delay, which is reduced
                 by 45.5 percent compared to a previous DP4
                 implementation using discrete multipliers and adders.
                 The proposed DP4 unit also reduces the cycle time of 3D
                 graphics applications by 12.4 percent on the average
                 compared to the usual 3D graphics FPU based on four-way
                 multiply-add-fused units.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "3D graphics; DP4; floating point arithmetic; graphics
                 processors; vector inner product",
}


bibtype: inproceedings
filename: fparith.bib
label: Kornerup:2009:CCR
author: P. Kornerup and V. Lefevre and N. Louvet and Jean-Michel Muller
title: On the Computation of Correctly-Rounded Sums
crossref: Bruguera:2009:PIS
pages: 155--160
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
acknowledgement: ack-nhfb
rawauthor: P. Kornerup and V. Lef{\`e}vre and N. Louvet and Jean-Michel Muller
rawtitle: On the Computation of Correctly-Rounded Sums
abstract:
This paper presents a study of some basic blocks needed in the design of floating-point summation algorithms. In particular, we show that among the set of the algorithms with no comparisons performing only floating-point additions / subtractions, the 2Sum algorithm introduced by Knuth is minimal, both in terms of number of operations and depth of the dependency graph. Under reasonable conditions, we also prove that no algorithms performing only round-to-nearest additions / subtractions exist to compute the round-to-nearest sum of at least three floating-point numbers. Starting from an algorithm due to Boldo and Melquiond, we also present new results about the computation of the correctly-rounded sum of three floating-point numbers.

keywords:
2Sum and Fast2Sum algorithms; ARITH-19; correct rounding; floating-point arithmetic; summation algorithms

rawabstract:
This paper presents a study of some basic blocks needed in the design of floating-point summation algorithms. In particular, we show that among the set of the algorithms with no comparisons performing only floating-point additions\slash subtractions, the 2Sum algorithm introduced by Knuth is minimal, both in terms of number of operations and depth of the dependency graph. Under reasonable conditions, we also prove that no algorithms performing only round-to-nearest additions\slash subtractions exist to compute the round-to-nearest sum of at least three floating-point numbers. Starting from an algorithm due to Boldo and Melquiond, we also present new results about the computation of the correctly-rounded sum of three floating-point numbers.

entry:
@InProceedings{Kornerup:2009:CCR,
  author =       "P. Kornerup and V. Lef{\`e}vre and N. Louvet and
                 Jean-Michel Muller",
  title =        "On the Computation of Correctly-Rounded Sums",
  crossref =     "Bruguera:2009:PIS",
  pages =        "155--160",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents a study of some basic blocks
                 needed in the design of floating-point summation
                 algorithms. In particular, we show that among the set
                 of the algorithms with no comparisons performing only
                 floating-point additions\slash subtractions, the 2Sum
                 algorithm introduced by Knuth is minimal, both in terms
                 of number of operations and depth of the dependency
                 graph. Under reasonable conditions, we also prove that
                 no algorithms performing only round-to-nearest
                 additions\slash subtractions exist to compute the
                 round-to-nearest sum of at least three floating-point
                 numbers. Starting from an algorithm due to Boldo and
                 Melquiond, we also present new results about the
                 computation of the correctly-rounded sum of three
                 floating-point numbers.",
  acknowledgement = ack-nhfb,
  keywords =     "2Sum and Fast2Sum algorithms; ARITH-19; correct
                 rounding; floating-point arithmetic; summation
                 algorithms",
}


bibtype: article
filename: fparith.bib
label: Kornerup:2009:GEI
author: Peter Kornerup and Paolo Montuschi and Jean-Michel Muller and Eric Schwarz
title: Guest Editors' Introduction: Special Section on Computer Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 2
pages: 145--147
month: feb
monthnumber: 2
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2009.11
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:39 MDT 2011
bibtimestamp: 2011.07.04 11:37:39 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4740165
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Peter Kornerup and Paolo Montuschi and Jean-Michel Muller and Eric Schwarz
rawtitle: {Guest Editors}' Introduction: Special Section on Computer Arithmetic
entry:
@Article{Kornerup:2009:GEI,
  author =       "Peter Kornerup and Paolo Montuschi and Jean-Michel
                 Muller and Eric Schwarz",
  title =        "{Guest Editors}' Introduction: Special Section on
                 Computer Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "2",
  pages =        "145--147",
  month =        feb,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2009.11",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4740165",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Lang:2009:DUB
author: T. Lang and A. Nannarelli
title: Division Unit for Binary Integer Decimals
crossref: IEEE:2009:IICa
pages: 1--7
year: 2009
DOI: https://doi.org/10.1109/ASAP.2009.42
bibdate: Sat Dec 04 06:56:17 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.12.04 06:56:17 ???
acknowledgement: ack-nhfb
rawauthor: T. Lang and A. Nannarelli
rawtitle: Division Unit for Binary Integer Decimals
abstract:
In this work, we present a radix-10 division unit that is based on the digit-recurrence algorithm and implements binary encodings (binary integer decimal or BID) for significands. Recent decimal division designs are all based on the binary coded decimal (BCD) encoding. We adapt the radix-10 digit-recurrence algorithm to BID representation and implement the division unit in standard cell technology. The implementation of the proposed BID division unit is compared to that of a BCD based unit implementing the same algorithm. The comparison shows that for normalized operands the BID unit has the same latency as the BCD unit and reduced area, but the normalization is more expensive when implemented in BID.

keywords:
adders; BID floating-point adder; BID floating-point multiplier; binary coded decimal encoding; binary integer decimals; computer arithmetic; decimal arithmetic; decimal division designs; digit-recurrence algorithm; digital arithmetic; division; multiplying circuits; radix-10 digit-recurrence algorithm; radix-10 division unit

rawabstract:
In this work, we present a radix-10 division unit that is based on the digit-recurrence algorithm and implements binary encodings (binary integer decimal or BID) for significands. Recent decimal division designs are all based on the binary coded decimal (BCD) encoding. We adapt the radix-10 digit-recurrence algorithm to BID representation and implement the division unit in standard cell technology. The implementation of the proposed BID division unit is compared to that of a BCD based unit implementing the same algorithm. The comparison shows that for normalized operands the BID unit has the same latency as the BCD unit and reduced area, but the normalization is more expensive when implemented in BID.

entry:
@InProceedings{Lang:2009:DUB,
  author =       "T. Lang and A. Nannarelli",
  title =        "Division Unit for Binary Integer Decimals",
  crossref =     "IEEE:2009:IICa",
  pages =        "1--7",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ASAP.2009.42",
  bibdate =      "Sat Dec 04 06:56:17 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this work, we present a radix-10 division unit that
                 is based on the digit-recurrence algorithm and
                 implements binary encodings (binary integer decimal or
                 BID) for significands. Recent decimal division designs
                 are all based on the binary coded decimal (BCD)
                 encoding. We adapt the radix-10 digit-recurrence
                 algorithm to BID representation and implement the
                 division unit in standard cell technology. The
                 implementation of the proposed BID division unit is
                 compared to that of a BCD based unit implementing the
                 same algorithm. The comparison shows that for
                 normalized operands the BID unit has the same latency
                 as the BCD unit and reduced area, but the normalization
                 is more expensive when implemented in BID.",
  acknowledgement = ack-nhfb,
  keywords =     "adders; BID floating-point adder; BID floating-point
                 multiplier; binary coded decimal encoding; binary
                 integer decimals; computer arithmetic; decimal
                 arithmetic; decimal division designs; digit-recurrence
                 algorithm; digital arithmetic; division; multiplying
                 circuits; radix-10 digit-recurrence algorithm; radix-10
                 division unit",
}


bibtype: article
filename: fparith.bib
label: Lauter:2009:ERB
author: C. Q. Lauter and V. Lefevre
title: An Efficient Rounding Boundary Test for tt pow(x, y) in Double Precision
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 2
pages: 197--207
month: feb
monthnumber: 2
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.202
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:39 MDT 2011
bibtimestamp: 2011.07.04 11:37:39 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4663059
fjournal: IEEE Transactions on Computers
keywords: correct rounding; floating-point arithmetic; power function.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: C. Q. Lauter and V. Lefevre
rawtitle: An Efficient Rounding Boundary Test for {\tt pow(x, y)} in Double Precision
abstract:
The correct rounding of the function $ textrm pow : (x, y) rightarrow x^y $ is currently based on Ziv's iterative approximation process. In order to ensure its termination, cases when $ x^y $ falls on a rounding-boundary must be filtered out. Such rounding-boundaries are floating-point numbers and midpoints between two consecutive floating-point numbers. Detecting rounding-boundaries for pow is a difficult problem. Previous approaches use repeated square root extraction followed by repeated square and multiply. This paper presents a new rounding-boundary test for pow in double precision, which reduces this to a few comparisons with precomputed constants. These constants are deduced from worst cases for the Table Maker's Dilemma, searched over a small subset of the input domain. This is a novel use of such worst-case bounds. The resulting algorithm has been designed for a fast-on-average correctly rounded implementation of pow, considering the scarcity of rounding-boundary cases. It does not stall average computations for rounding-boundary detection. This paper includes its correctness proof and experimental results.

rawabstract:
The correct rounding of the function $ \textrm {pow} : (x, y) \rightarrow x^y $ is currently based on Ziv's iterative approximation process. In order to ensure its termination, cases when $ x^y $ falls on a rounding-boundary must be filtered out. Such rounding-boundaries are floating-point numbers and midpoints between two consecutive floating-point numbers. Detecting rounding-boundaries for pow is a difficult problem. Previous approaches use repeated square root extraction followed by repeated square and multiply. This paper presents a new rounding-boundary test for pow in double precision, which reduces this to a few comparisons with precomputed constants. These constants are deduced from worst cases for the Table Maker's Dilemma, searched over a small subset of the input domain. This is a novel use of such worst-case bounds. The resulting algorithm has been designed for a fast-on-average correctly rounded implementation of pow, considering the scarcity of rounding-boundary cases. It does not stall average computations for rounding-boundary detection. This paper includes its correctness proof and experimental results.

entry:
@Article{Lauter:2009:ERB,
  author =       "C. Q. Lauter and V. Lefevre",
  title =        "An Efficient Rounding Boundary Test for {\tt pow(x,
                 y)} in Double Precision",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "2",
  pages =        "197--207",
  month =        feb,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.202",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4663059",
  abstract =     "The correct rounding of the function $ \textrm {pow} :
                 (x, y) \rightarrow x^y $ is currently based on Ziv's
                 iterative approximation process. In order to ensure its
                 termination, cases when $ x^y $ falls on a
                 rounding-boundary must be filtered out. Such
                 rounding-boundaries are floating-point numbers and
                 midpoints between two consecutive floating-point
                 numbers. Detecting rounding-boundaries for pow is a
                 difficult problem. Previous approaches use repeated
                 square root extraction followed by repeated square and
                 multiply. This paper presents a new rounding-boundary
                 test for pow in double precision, which reduces this to
                 a few comparisons with precomputed constants. These
                 constants are deduced from worst cases for the Table
                 Maker's Dilemma, searched over a small subset of the
                 input domain. This is a novel use of such worst-case
                 bounds. The resulting algorithm has been designed for a
                 fast-on-average correctly rounded implementation of
                 pow, considering the scarcity of rounding-boundary
                 cases. It does not stall average computations for
                 rounding-boundary detection. This paper includes its
                 correctness proof and experimental results.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "correct rounding; floating-point arithmetic; power
                 function.",
}


bibtype: article
filename: fparith.bib
label: Li:2009:FAT
author: Xin Li and Marc Moreno Maza and Eric Schost
title: Fast arithmetic for triangular sets: From theory to practice
journal: j-J-SYMBOLIC-COMP
volume: 44
number: 7
pages: 891--907
month: jul
monthnumber: 7
year: 2009
CODEN: JSYCEH
ISSN: 0747-7171 (print), 1095-855X (electronic) OR 07477171 (print), 1095855X (electronic)
ISSNL: 0747-7171 OR 07477171
bibdate: Wed Aug 25 20:13:19 MDT 2010
bibtimestamp: 2010.08.25 20:13:19 MDT
fjournal: Journal of Symbolic Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07477171
rawauthor: Xin Li and Marc Moreno Maza and {\'E}ric Schost
rawtitle: Fast arithmetic for triangular sets: From theory to practice
bibsource:
http://www.sciencedirect.com/science/journal/07477171; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Li:2009:FAT,
  author =       "Xin Li and Marc Moreno Maza and {\'E}ric Schost",
  title =        "Fast arithmetic for triangular sets: From theory to
                 practice",
  journal =      j-J-SYMBOLIC-COMP,
  volume =       "44",
  number =       "7",
  pages =        "891--907",
  month =        jul,
  year =         "2009",
  CODEN =        "JSYCEH",
  ISSN =         "0747-7171 (print), 1095-855X (electronic)",
  ISSN-L =       "0747-7171",
  bibdate =      "Wed Aug 25 20:13:19 MDT 2010",
  bibsource =    "http://www.sciencedirect.com/science/journal/07477171;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Symbolic Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07477171",
}


bibtype: techreport
filename: fparith.bib
label: Maclaren:2009:HCH
author: N. M. Maclaren
title: How Computers Handle Numbers: a.k.a. Computer Arithmetic Uncovered
type: Course notes
institution: Cambridge University Computing Service
address: Cambridge, UK
pages: 891--907
month: jul
monthnumber: 7
year: 2009
bibdate: Tue Apr 27 09:48:59 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.04.27 09:48:59 ???
URL: http://www-uxsup.csx.cam.ac.uk/courses/Arithmetic/notes.pdf
acknowledgement: ack-nhfb
rawauthor: N. M. Maclaren
rawtitle: How Computers Handle Numbers: a.k.a. Computer Arithmetic Uncovered
entry:
@TechReport{Maclaren:2009:HCH,
  author =       "N. M. Maclaren",
  title =        "How Computers Handle Numbers: a.k.a. Computer
                 Arithmetic Uncovered",
  type =         "Course notes",
  institution =  "Cambridge University Computing Service",
  address =      "Cambridge, UK",
  month =        jul,
  year =         "2009",
  bibdate =      "Tue Apr 27 09:48:59 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www-uxsup.csx.cam.ac.uk/courses/Arithmetic/notes.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Martel:2009:PTN
author: Matthieu Martel
editor: German Puebla
title: Program transformation for numerical precision
publisher: ACM Press
pages: 101--110
year: 2009
DOI: https://doi.org/10.1145/1480945.1480960
ISBN: 1-60558-327-8 OR 1605583278
ISBN13: 978-1-60558-327-3 OR 9781605583273
bibdate: Thu Oct 17 05:52:02 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 05:52:02 ???
URL: https://dl.acm.org/citation.cfm?doid=1480945.1480960
acknowledgement: ack-nhfb
rawauthor: Matthieu Martel
raweditor: Germ{\'a}n Puebla
rawtitle: Program transformation for numerical precision
booktitle:
Proceedings of the 2009 ACM SIGPLAN Workshop on Partial Evaluation and Program Manipulation --- PEPM'09: Savannah, Georgia, USA, January 19--20, 2009

abstract:
This article introduces a new program transformation in order to enhance the numerical accuracy of floating-point computations. We consider that a program would return an exact result if the computations were carried out using real numbers. In practice, roundoff errors due to the finite representation of values arise during the execution. These errors are closely related to the way formulas are evaluated. Indeed, mathematically equivalent formulas, obtained using laws like associativity, distributivity, etc., may lead to very different numerical results in the computer arithmetic. We propose a semantics-based transformation in order to optimize the numerical accuracy of programs. This transformation is expressed in the abstract interpretation framework and it aims at rewriting pieces of numerical codes in order to obtain results closer to what the computer would output if it used the exact arithmetic.

rawabstract:
This article introduces a new program transformation in order to enhance the numerical accuracy of floating-point computations. We consider that a program would return an exact result if the computations were carried out using real numbers. In practice, roundoff errors due to the finite representation of values arise during the execution. These errors are closely related to the way formulas are evaluated. Indeed, mathematically equivalent formulas, obtained using laws like associativity, distributivity, etc., may lead to very different numerical results in the computer arithmetic. We propose a semantics-based transformation in order to optimize the numerical accuracy of programs. This transformation is expressed in the abstract interpretation framework and it aims at rewriting pieces of numerical codes in order to obtain results closer to what the computer would output if it used the exact arithmetic.

rawbooktitle:
{Proceedings of the 2009 ACM SIGPLAN Workshop on Partial Evaluation and Program Manipulation --- PEPM'09: Savannah, Georgia, USA, January 19--20, 2009}

entry:
@InProceedings{Martel:2009:PTN,
  author =       "Matthieu Martel",
  editor =       "Germ{\'a}n Puebla",
  booktitle =    "{Proceedings of the 2009 ACM SIGPLAN Workshop on
                 Partial Evaluation and Program Manipulation ---
                 PEPM'09: Savannah, Georgia, USA, January 19--20,
                 2009}",
  title =        "Program transformation for numerical precision",
  publisher =    "{ACM} Press",
  pages =        "101--110",
  year =         "2009",
  DOI =          "https://doi.org/10.1145/1480945.1480960",
  ISBN =         "1-60558-327-8",
  ISBN-13 =      "978-1-60558-327-3",
  bibdate =      "Thu Oct 17 05:52:02 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://dl.acm.org/citation.cfm?doid=1480945.1480960",
  abstract =     "This article introduces a new program transformation
                 in order to enhance the numerical accuracy of
                 floating-point computations. We consider that a program
                 would return an exact result if the computations were
                 carried out using real numbers. In practice, roundoff
                 errors due to the finite representation of values arise
                 during the execution. These errors are closely related
                 to the way formulas are evaluated. Indeed,
                 mathematically equivalent formulas, obtained using laws
                 like associativity, distributivity, etc., may lead to
                 very different numerical results in the computer
                 arithmetic. We propose a semantics-based transformation
                 in order to optimize the numerical accuracy of
                 programs. This transformation is expressed in the
                 abstract interpretation framework and it aims at
                 rewriting pieces of numerical codes in order to obtain
                 results closer to what the computer would output if it
                 used the exact arithmetic.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Matula:2009:HRS
author: David W. Matula
title: Higher Radix Squaring Operations Employing Left-to-Right Dual Recoding
crossref: Bruguera:2009:PIS
pages: 39--47
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
acknowledgement: ack-nhfb
rawauthor: David W. Matula
rawtitle: Higher Radix Squaring Operations Employing Left-to-Right Dual Recoding
abstract:
We introduce a novel left-to-right leading digit first dual recoding of an operand for the purpose of designing the squaring operation on that operand. Our dual recoding yields an array of non-negative partial squares of size essentially one half that of a comparable multiplier partial product array for both radix-4 and radix-8 designs. For radix-8 design the 128-bit square of a 64-bit operand can be obtained from a consolidated partial square array of just 11 rows. We describe advantages of our left-to-right recoding compared to a previous right-to-left Booth-folding encoding applicable to radix-4. We also show simplifications available to the designs of a rounded floating point square operation and to a low precision approximate square.

keywords:
ARITH-19; Booth multiplier recoding; Booth-folding; partial products; partial squares; sign extension.; squarer

rawabstract:
We introduce a novel left-to-right leading digit first dual recoding of an operand for the purpose of designing the squaring operation on that operand. Our dual recoding yields an array of non-negative partial squares of size essentially one half that of a comparable multiplier partial product array for both radix-4 and radix-8 designs. For radix-8 design the 128-bit square of a 64-bit operand can be obtained from a consolidated partial square array of just 11 rows. We describe advantages of our left-to-right recoding compared to a previous right-to-left Booth-folding encoding applicable to radix-4. We also show simplifications available to the designs of a rounded floating point square operation and to a low precision approximate square.

entry:
@InProceedings{Matula:2009:HRS,
  author =       "David W. Matula",
  title =        "Higher Radix Squaring Operations Employing
                 Left-to-Right Dual Recoding",
  crossref =     "Bruguera:2009:PIS",
  pages =        "39--47",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We introduce a novel left-to-right leading digit first
                 dual recoding of an operand for the purpose of
                 designing the squaring operation on that operand. Our
                 dual recoding yields an array of non-negative partial
                 squares of size essentially one half that of a
                 comparable multiplier partial product array for both
                 radix-4 and radix-8 designs. For radix-8 design the
                 128-bit square of a 64-bit operand can be obtained from
                 a consolidated partial square array of just 11 rows. We
                 describe advantages of our left-to-right recoding
                 compared to a previous right-to-left Booth-folding
                 encoding applicable to radix-4. We also show
                 simplifications available to the designs of a rounded
                 floating point square operation and to a low precision
                 approximate square.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19; Booth multiplier recoding; Booth-folding;
                 partial products; partial squares; sign extension.;
                 squarer",
}


bibtype: inproceedings
filename: fparith.bib
label: Mazor:2009:HPC
author: Stanley Mazor
title: A Historical Perspective on Computer Arithmetic
crossref: Bruguera:2009:PIS
pages: 35--35
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19; Intel 4004; Intel 8080
remark: Only abstract published.
acknowledgement: ack-nhfb
rawauthor: Stanley Mazor
rawtitle: A Historical Perspective on Computer Arithmetic
entry:
@InProceedings{Mazor:2009:HPC,
  author =       "Stanley Mazor",
  title =        "A Historical Perspective on Computer Arithmetic",
  crossref =     "Bruguera:2009:PIS",
  pages =        "35--35",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19; Intel 4004; Intel 8080",
  remark =       "Only abstract published.",
}


bibtype: book
filename: fparith.bib
label: Miller:2009:RNR
editor: Frederic P. Miller and Agnes F. Vandome and John McBrewster
publisher: Alphascript Publishing
address: 17 Rue Meldrum, Beau Bassin, 1713-01 Mauritius
pages: 88 (est.)
year: 2009
ISBN: 613-0-06480-2 OR 6130064802
ISBN13: 978-613-0-06480-8 OR 9786130064808
bibdate: Wed Oct 28 09:06:59 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.10.28 09:06:59 ???
acknowledgement: ack-nhfb
raweditor: Frederic P. Miller and Agnes F. Vandome and John McBrewster
title:
Roman Numerals: Roman numeral analysis, Roman arithmetic, Roman abacus, Kharosthi, Unicode numerals, Etruscan numerals, Positional notation, Arabic numerals, Districts of Turku

rawtitle:
Roman Numerals: Roman numeral analysis, Roman arithmetic, Roman abacus, {Kharosthi}, {Unicode} numerals, {Etruscan} numerals, Positional notation, Arabic numerals, Districts of {Turku}

entry:
@Book{Miller:2009:RNR,
  editor =       "Frederic P. Miller and Agnes F. Vandome and John
                 McBrewster",
  title =        "Roman Numerals: Roman numeral analysis, Roman
                 arithmetic, Roman abacus, {Kharosthi}, {Unicode}
                 numerals, {Etruscan} numerals, Positional notation,
                 Arabic numerals, Districts of {Turku}",
  publisher =    "Alphascript Publishing",
  address =      "17 Rue Meldrum, Beau Bassin, 1713-01 Mauritius",
  pages =        "88 (est.)",
  year =         "2009",
  ISBN =         "613-0-06480-2",
  ISBN-13 =      "978-613-0-06480-8",
  LCCN =         "????",
  bibdate =      "Wed Oct 28 09:06:59 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "US\$50",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Minchola:2009:FID
author: C. Minchola and G. Sutter
title: A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier
crossref: Cumplido:2009:RPI
pages: 59--64
year: 2009
DOI: https://doi.org/10.1109/ReConFig.2009.34
bibdate: Thu Feb 17 08:36:13 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.17 08:36:13 ???
acknowledgement: ack-nhfb
rawauthor: C. Minchola and G. Sutter
rawtitle: A {FPGA} {IEEE-754-2008} {Decimal64} Floating-Point Multiplier
entry:
@InProceedings{Minchola:2009:FID,
  author =       "C. Minchola and G. Sutter",
  title =        "A {FPGA} {IEEE-754-2008} {Decimal64} Floating-Point
                 Multiplier",
  crossref =     "Cumplido:2009:RPI",
  pages =        "59--64",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ReConFig.2009.34",
  bibdate =      "Thu Feb 17 08:36:13 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Monniaux:2009:UFPa
author: David Monniaux
title: On using floating-point computations to help an exact linear arithmetic decision procedure
journal: arXiv.org
pages: ??--??
day: 22
month: apr
monthnumber: 4
year: 2009
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/0904.3525
subject: Logic in Computer Science (cs.LO); Numerical Analysis (cs.NA)
acknowledgement: ack-nhfb
rawauthor: David Monniaux
rawtitle: On using floating-point computations to help an exact linear arithmetic decision procedure
abstract:
We consider the decision problem for quantifier-free formulas whose atoms are linear inequalities interpreted over the reals or rationals. This problem may be decided using satisfiability modulo theory (SMT), using a mixture of a SAT solver and a simplex-based decision procedure for conjunctions. State-of-the-art SMT solvers use simplex implementations over rational numbers, which perform well for typical problems arising from model-checking and program analysis (sparse inequalities, small coefficients) but are slow for other applications (denser problems, larger coefficients). We propose a simple preprocessing phase that can be adapted on existing SMT solvers and that may be optionally triggered. Despite using floating-point computations, our method is sound and complete --- it merely affects efficiency. We implemented the method and provide benchmarks showing that this change brings a naive and slow decision procedure (''textbook simplex'' with rational numbers) up to the efficiency of recent SMT solvers, over test cases arising from model-checking, and makes it definitely faster than state-of-the-art SMT solvers on dense examples.

rawabstract:
We consider the decision problem for quantifier-free formulas whose atoms are linear inequalities interpreted over the reals or rationals. This problem may be decided using satisfiability modulo theory (SMT), using a mixture of a SAT solver and a simplex-based decision procedure for conjunctions. State-of-the-art SMT solvers use simplex implementations over rational numbers, which perform well for typical problems arising from model-checking and program analysis (sparse inequalities, small coefficients) but are slow for other applications (denser problems, larger coefficients). We propose a simple preprocessing phase that can be adapted on existing SMT solvers and that may be optionally triggered. Despite using floating-point computations, our method is sound and complete --- it merely affects efficiency. We implemented the method and provide benchmarks showing that this change brings a naive and slow decision procedure (''textbook simplex'' with rational numbers) up to the efficiency of recent SMT solvers, over test cases arising from model-checking, and makes it definitely faster than state-of-the-art SMT solvers on dense examples.

entry:
@Article{Monniaux:2009:UFPa,
  author =       "David Monniaux",
  title =        "On using floating-point computations to help an exact
                 linear arithmetic decision procedure",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "22",
  month =        apr,
  year =         "2009",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/0904.3525",
  abstract =     "We consider the decision problem for quantifier-free
                 formulas whose atoms are linear inequalities
                 interpreted over the reals or rationals. This problem
                 may be decided using satisfiability modulo theory
                 (SMT), using a mixture of a SAT solver and a
                 simplex-based decision procedure for conjunctions.
                 State-of-the-art SMT solvers use simplex
                 implementations over rational numbers, which perform
                 well for typical problems arising from model-checking
                 and program analysis (sparse inequalities, small
                 coefficients) but are slow for other applications
                 (denser problems, larger coefficients). We propose a
                 simple preprocessing phase that can be adapted on
                 existing SMT solvers and that may be optionally
                 triggered. Despite using floating-point computations,
                 our method is sound and complete --- it merely affects
                 efficiency. We implemented the method and provide
                 benchmarks showing that this change brings a naive and
                 slow decision procedure (''textbook simplex'' with
                 rational numbers) up to the efficiency of recent SMT
                 solvers, over test cases arising from model-checking,
                 and makes it definitely faster than state-of-the-art
                 SMT solvers on dense examples.",
  acknowledgement = ack-nhfb,
  subject =      "Logic in Computer Science (cs.LO); Numerical Analysis
                 (cs.NA)",
}


bibtype: inproceedings
filename: fparith.bib
label: Monniaux:2009:UFPb
author: David Monniaux
title: On Using Floating-Point Computations to Help an Exact Linear Arithmetic Decision Procedure
crossref: Bouajjani:2009:CAV
pages: 570--583
year: 2009
DOI: https://doi.org/10.1007/978-3-642-02658-4_42
bibdate: Fri Dec 8 14:29:46 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 14:29:46 ???
acknowledgement: ack-nhfb
rawauthor: David Monniaux
rawtitle: On Using Floating-Point Computations to Help an Exact Linear Arithmetic Decision Procedure
entry:
@InProceedings{Monniaux:2009:UFPb,
  author =       "David Monniaux",
  title =        "On Using Floating-Point Computations to Help an Exact
                 Linear Arithmetic Decision Procedure",
  crossref =     "Bouajjani:2009:CAV",
  pages =        "570--583",
  year =         "2009",
  DOI =          "https://doi.org/10.1007/978-3-642-02658-4_42",
  bibdate =      "Fri Dec 8 14:29:46 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Mosbach:2009:QPI
author: Sebastian Mosbach and Amanda G. Turner
journal: j-COMPUT-MATH-APPL
volume: 57
number: 7
pages: 1157--1167
month: apr
monthnumber: 4
year: 2009
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 21:50:24 MST 2017
bibtimestamp: 2017.03.01 21:50:24 MST
URL: http://www.sciencedirect.com/science/article/pii/S0898122109000431
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: Sebastian Mosbach and Amanda G. Turner
title:
A quantitative probabilistic investigation into the accumulation of rounding errors in numerical ODE solution

rawtitle:
A quantitative probabilistic investigation into the accumulation of rounding errors in numerical {ODE} solution

entry:
@Article{Mosbach:2009:QPI,
  author =       "Sebastian Mosbach and Amanda G. Turner",
  title =        "A quantitative probabilistic investigation into the
                 accumulation of rounding errors in numerical {ODE}
                 solution",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "57",
  number =       "7",
  pages =        "1157--1167",
  month =        apr,
  year =         "2009",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 21:50:24 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0898122109000431",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: article
filename: fparith.bib
label: Murakami:2009:CFT
author: Hiroshi Murakami
journal: j-ACM-COMM-COMP-ALGEBRA
volume: 43
number: 3
pages: 88--90
month: sep
monthnumber: 9
year: 2009
DOI: https://doi.org/10.1145/1823931.1823943
ISSN: 1932-2232 (print), 1932-2240 (electronic) OR 19322232 (print), 19322240 (electronic)
ISSNL: 1932-2232 OR 19322232
bibdate: Tue Jul 6 14:14:27 MDT 2010
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.07.06 14:14:27 MDT
fjournal: ACM Communications in Computer Algebra
keywords: approximation; continued fraction; interval; rational number
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J1000
issue: 169
rawauthor: Hiroshi Murakami
title:
A continued fraction type method to find a rational number in a given closed interval whose denominator is minimal

abstract:
We show a fast algorithm to find a rational number in a given real interval whose denominator is minimal. The algorithm is similar to the regular continued fraction expansion for a real number.

rawabstract:
We show a fast algorithm to find a rational number in a given real interval whose denominator is minimal. The algorithm is similar to the regular continued fraction expansion for a real number.

rawtitle:
A continued fraction type method to find a rational number in a given closed interval whose denominator is minimal

entry:
@Article{Murakami:2009:CFT,
  author =       "Hiroshi Murakami",
  title =        "A continued fraction type method to find a rational
                 number in a given closed interval whose denominator is
                 minimal",
  journal =      j-ACM-COMM-COMP-ALGEBRA,
  volume =       "43",
  number =       "3",
  pages =        "88--90",
  month =        sep,
  year =         "2009",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/1823931.1823943",
  ISSN =         "1932-2232 (print), 1932-2240 (electronic)",
  ISSN-L =       "1932-2232",
  bibdate =      "Tue Jul 6 14:14:27 MDT 2010",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We show a fast algorithm to find a rational number in
                 a given real interval whose denominator is minimal. The
                 algorithm is similar to the regular continued fraction
                 expansion for a real number.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Communications in Computer Algebra",
  issue =        "169",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J1000",
  keywords =     "approximation; continued fraction; interval; rational
                 number",
}


bibtype: article
filename: fparith.bib
label: Pan:2009:NEF
author: V. Y. Pan and B. Murphy and G. Qian and R. E. Rosholt
title: A new error-free floating-point summation algorithm
journal: j-COMPUT-MATH-APPL
volume: 57
number: 4
pages: 560--564
month: feb
monthnumber: 2
year: 2009
CODEN: CMAPDK
DOI: https://doi.org/10.1016/j.camwa.2008.09.051
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 21:50:22 MST 2017
bibtimestamp: 2017.03.01 21:50:22 MST
URL: http://www.sciencedirect.com/science/article/pii/S0898122108006718
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: V. Y. Pan and B. Murphy and G. Qian and R. E. Rosholt
rawtitle: A new error-free floating-point summation algorithm
entry:
@Article{Pan:2009:NEF,
  author =       "V. Y. Pan and B. Murphy and G. Qian and R. E.
                 Rosholt",
  title =        "A new error-free floating-point summation algorithm",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "57",
  number =       "4",
  pages =        "560--564",
  month =        feb,
  year =         "2009",
  CODEN =        "CMAPDK",
  DOI =          "https://doi.org/10.1016/j.camwa.2008.09.051",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 21:50:22 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0898122108006718",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: article
filename: fparith.bib
label: Papadantonakis:2009:PSA
author: K. Papadantonakis and N. Kapre and S. Chan and A. DeHon
title: Pipelining Saturated Accumulation
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 2
pages: 208--219
month: feb
monthnumber: 2
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.110
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jun 12 08:51:00 MDT 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 08:51:00 MDT
fjournal: IEEE Transactions on Computers
remark: Extended version of ARITH-18 article cite .
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: K. Papadantonakis and N. Kapre and S. Chan and A. DeHon
rawtitle: Pipelining Saturated Accumulation
abstract:
Aggressive pipelining and spatial parallelism allow integrated circuits (e.g., custom VLSI, ASICs, and FPGAs) to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit parallelism and reduce the efficiency and speed of an implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. We show how to reformulate saturated addition as an associative operation so that we can use a parallel-prefix calculation to perform saturated accumulation at any data rate supported by the device. This allows us, for example, to design a 16-bit saturated accumulator which can operate at 280 MHz on a Xilinx Spartan-3 (XC3S-5000-4) FPGA, the maximum frequency supported by the component's DCM.

keywords:
accumulation; high-speed arithmetic; parallel prefix.; pipeline and parallel arithmetic and logic structures; saturated arithmetic

rawabstract:
Aggressive pipelining and spatial parallelism allow integrated circuits (e.g., custom VLSI, ASICs, and FPGAs) to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit parallelism and reduce the efficiency and speed of an implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. We show how to reformulate saturated addition as an associative operation so that we can use a parallel-prefix calculation to perform saturated accumulation at any data rate supported by the device. This allows us, for example, to design a 16-bit saturated accumulator which can operate at 280 MHz on a Xilinx Spartan-3 (XC3S-5000-4) FPGA, the maximum frequency supported by the component's DCM.

entry:
@Article{Papadantonakis:2009:PSA,
  author =       "K. Papadantonakis and N. Kapre and S. Chan and A.
                 DeHon",
  title =        "Pipelining Saturated Accumulation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "2",
  pages =        "208--219",
  month =        feb,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.110",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jun 12 08:51:00 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Aggressive pipelining and spatial parallelism allow
                 integrated circuits (e.g., custom VLSI, ASICs, and
                 FPGAs) to achieve high throughput on many Digital
                 Signal Processing applications. However, cyclic data
                 dependencies in the computation can limit parallelism
                 and reduce the efficiency and speed of an
                 implementation. Saturated accumulation is an important
                 example where such a cycle limits the throughput of
                 signal processing applications. We show how to
                 reformulate saturated addition as an associative
                 operation so that we can use a parallel-prefix
                 calculation to perform saturated accumulation at any
                 data rate supported by the device. This allows us, for
                 example, to design a 16-bit saturated accumulator which
                 can operate at 280 MHz on a Xilinx Spartan-3
                 (XC3S-5000-4) FPGA, the maximum frequency supported by
                 the component's DCM.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "accumulation; high-speed arithmetic; parallel prefix.;
                 pipeline and parallel arithmetic and logic structures;
                 saturated arithmetic",
  remark =       "Extended version of ARITH-18 article \cite{}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Preiss:2009:ACS
author: Jochen Preiss and Maarten Boersma and Silvia Melitta Mueller
title: Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units
crossref: Bruguera:2009:PIS
pages: 48--56
year: 2009
DOI: https://doi.org/10.1109/ARITH.2009.17
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
acknowledgement: ack-nhfb
rawauthor: Jochen Preiss and Maarten Boersma and Silvia Melitta Mueller
rawtitle: Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units
abstract:
The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating-point units (FPU). The clockgating is based on instruction type, precision and operand values. The presented schemes focus on reducing the power at peak performance, where each FPU stage is used in nearly every cycle and conventional schemes have little impact on the power consumption. Depending on the instruction mix, the schemes allow to turn off 18% to 74% of the register bits. Even for the worst case instruction 18% to 37% of the FPU are shut down depending on the data patterns.

keywords:
ARITH-19; clockgating; floating-point hardware; fused multiply-add; IEEE 754 Standard; power reduction

rawabstract:
The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating-point units (FPU). The clockgating is based on instruction type, precision and operand values. The presented schemes focus on reducing the power at peak performance, where each FPU stage is used in nearly every cycle and conventional schemes have little impact on the power consumption. Depending on the instruction mix, the schemes allow to turn off 18\% to 74\% of the register bits. Even for the worst case instruction 18\% to 37\% of the FPU are shut down depending on the data patterns.

entry:
@InProceedings{Preiss:2009:ACS,
  author =       "Jochen Preiss and Maarten Boersma and Silvia Melitta
                 Mueller",
  title =        "Advanced Clockgating Schemes for
                 Fused-Multiply-Add-Type Floating-Point Units",
  crossref =     "Bruguera:2009:PIS",
  pages =        "48--56",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ARITH.2009.17",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The paper introduces fine-grain clockgating schemes
                 for fused multiply-add-type floating-point units (FPU).
                 The clockgating is based on instruction type, precision
                 and operand values. The presented schemes focus on
                 reducing the power at peak performance, where each FPU
                 stage is used in nearly every cycle and conventional
                 schemes have little impact on the power consumption.
                 Depending on the instruction mix, the schemes allow to
                 turn off 18\% to 74\% of the register bits. Even for
                 the worst case instruction 18\% to 37\% of the FPU are
                 shut down depending on the data patterns.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19; clockgating; floating-point hardware; fused
                 multiply-add; IEEE 754 Standard; power reduction",
}


bibtype: article
filename: fparith.bib
label: Rump:2009:CPS
author: Siegfried M. Rump and Paul Zimmermann and Sylvie Boldo and Guillaume Melquiond
title: Computing predecessor and successor in rounding to nearest
journal: j-BIT-NUM-MATH
volume: 49
number: 2
pages: 419--431
month: jun
monthnumber: 6
year: 2009
CODEN: BITTEL, NBITAB
DOI: https://doi.org/10.1007/s10543-009-0218-z
ISSN: 0006-3835 (print), 1572-9125 (electronic) OR 00063835 (print), 15729125 (electronic)
ISSNL: 0006-3835 OR 00063835
bibdate: Mon May 24 15:36:43 MDT 2010
bibtimestamp: 2010.05.24 15:36:43 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0006-3835&volume=49&issue=2&spage=419
fjournal: BIT. Numerical Mathematics
keywords: directed rounding; floating-point arithmetic; predecessor; rounding to nearest; successor
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10543
rawauthor: Siegfried M. Rump and Paul Zimmermann and Sylvie Boldo and Guillaume Melquiond
rawtitle: Computing predecessor and successor in rounding to nearest
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0006-3835&volume=49&issue=2; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We give simple and efficient methods to compute and/or estimate the predecessor and successor of a floating-point number using only floating-point operations in rounding to nearest. This may be used to simulate interval operations, in which case the quality in terms of the diameter of the result is significantly improved compared to existing approaches.

rawabstract:
We give simple and efficient methods to compute and/or estimate the predecessor and successor of a floating-point number using only floating-point operations in rounding to nearest. This may be used to simulate interval operations, in which case the quality in terms of the diameter of the result is significantly improved compared to existing approaches.

entry:
@Article{Rump:2009:CPS,
  author =       "Siegfried M. Rump and Paul Zimmermann and Sylvie Boldo
                 and Guillaume Melquiond",
  title =        "Computing predecessor and successor in rounding to
                 nearest",
  journal =      j-BIT-NUM-MATH,
  volume =       "49",
  number =       "2",
  pages =        "419--431",
  month =        jun,
  year =         "2009",
  CODEN =        "BITTEL, NBITAB",
  DOI =          "https://doi.org/10.1007/s10543-009-0218-z",
  ISSN =         "0006-3835 (print), 1572-9125 (electronic)",
  ISSN-L =       "0006-3835",
  bibdate =      "Mon May 24 15:36:43 MDT 2010",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0006-3835&volume=49&issue=2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0006-3835&volume=49&issue=2&spage=419",
  abstract =     "We give simple and efficient methods to compute and/or
                 estimate the predecessor and successor of a
                 floating-point number using only floating-point
                 operations in rounding to nearest. This may be used to
                 simulate interval operations, in which case the quality
                 in terms of the diameter of the result is significantly
                 improved compared to existing approaches.",
  acknowledgement = ack-nhfb,
  fjournal =     "BIT. Numerical Mathematics",
  journal-URL =  "http://link.springer.com/journal/10543",
  keywords =     "directed rounding; floating-point arithmetic;
                 predecessor; rounding to nearest; successor",
}


bibtype: article
filename: fparith.bib
label: Rump:2009:UFA
author: Siegfried M. Rump
title: Ultimately Fast Accurate Summation
journal: j-SIAM-J-SCI-COMP
volume: 31
number: 5
pages: 3466--3502
year: 2009
CODEN: SJOCE3
DOI: https://doi.org/10.1137/080738490
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Wed May 19 10:44:20 MDT 2010
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/SISC/31/5; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.19 10:44:20 MDT
fjournal: SIAM Journal on Scientific Computing
keywords: accurate floating-point summation; distillation
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: Siegfried M. Rump
rawtitle: Ultimately Fast Accurate Summation
abstract:
We present two new algorithms FastAccSum and FastPrecSum, one to compute a faithful rounding of the sum of floating-point numbers and the other for a result ``as if'' computed in $K$-fold precision. Faithful rounding means the computed result either is one of the immediate floating-point neighbors of the exact result or is equal to the exact sum if this is a floating-point number. The algorithms are based on our previous algorithms AccSum and PrecSum and improve them by up to 25%. The first algorithm adapts to the condition number of the sum; i.e., the computing time is proportional to the difficulty of the problem. The second algorithm does not need extra memory, and the computing time depends only on the number of summands and $K$. Both algorithms are the fastest known in terms of flops. They allow good instruction-level parallelism so that they are also fast in terms of measured computing time. The algorithms require only standard floating-point addition, subtraction, and multiplication in one working precision, for example, double precision.

rawabstract:
We present two new algorithms FastAccSum and FastPrecSum, one to compute a faithful rounding of the sum of floating-point numbers and the other for a result ``as if'' computed in $K$-fold precision. Faithful rounding means the computed result either is one of the immediate floating-point neighbors of the exact result or is equal to the exact sum if this is a floating-point number. The algorithms are based on our previous algorithms AccSum and PrecSum and improve them by up to 25\%. The first algorithm adapts to the condition number of the sum; i.e., the computing time is proportional to the difficulty of the problem. The second algorithm does not need extra memory, and the computing time depends only on the number of summands and $K$. Both algorithms are the fastest known in terms of flops. They allow good instruction-level parallelism so that they are also fast in terms of measured computing time. The algorithms require only standard floating-point addition, subtraction, and multiplication in one working precision, for example, double precision.

entry:
@Article{Rump:2009:UFA,
  author =       "Siegfried M. Rump",
  title =        "Ultimately Fast Accurate Summation",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "31",
  number =       "5",
  pages =        "3466--3502",
  month =        "????",
  year =         "2009",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/080738490",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Wed May 19 10:44:20 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/31/5;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present two new algorithms FastAccSum and
                 FastPrecSum, one to compute a faithful rounding of the
                 sum of floating-point numbers and the other for a
                 result ``as if'' computed in $K$-fold precision.
                 Faithful rounding means the computed result either is
                 one of the immediate floating-point neighbors of the
                 exact result or is equal to the exact sum if this is a
                 floating-point number. The algorithms are based on our
                 previous algorithms AccSum and PrecSum and improve them
                 by up to 25\%. The first algorithm adapts to the
                 condition number of the sum; i.e., the computing time
                 is proportional to the difficulty of the problem. The
                 second algorithm does not need extra memory, and the
                 computing time depends only on the number of summands
                 and $K$. Both algorithms are the fastest known in terms
                 of flops. They allow good instruction-level parallelism
                 so that they are also fast in terms of measured
                 computing time. The algorithms require only standard
                 floating-point addition, subtraction, and
                 multiplication in one working precision, for example,
                 double precision.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "accurate floating-point summation; distillation",
}


bibtype: article
filename: fparith.bib
label: Schwarz:2009:DFP
author: E. M. Schwarz and J. S. Kapernick and M. F. Cowlishaw
title: Decimal floating-point support on the IBM System z10 processor
journal: j-IBM-JRD
volume: 53
number: 1
pages: 4:1--4:10
month: jan
monthnumber: 1
year: 2009
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Thu Jan 29 14:25:32 MST 2009
bibsource: http://www.research.ibm.com/journal/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.01.29 14:25:32 MST
URL: http://www.research.ibm.com/journal/rd/531/schwarz.pdf
fjournal: IBM Journal of Research and Development
keywords: ARITH-19
remark: Extended version of ARITH-18 article cite .
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawauthor: E. M. Schwarz and J. S. Kapernick and M. F. Cowlishaw
rawtitle: Decimal floating-point support on the {IBM System z10} processor
abstract:
The latest IBM zSeries processor, the IBM System z10 processor, provides hardware support for the decimal floating-point (DFP) facility that was introduced on the IBM System z9 processor. The z9 processor implements the facility with a mixture of low-level software and hardware assists. Recently, the IBM POWER6 processor-based System p 570 server introduced a hardware implementation of the DFP facility. The latest zSeries processor includes a decimal floating-point unit based on the POWER6 processor DFP unit that has been enhanced to also support the traditional zSeries decimal fixed-point instruction set. This paper explains the hardware implementation to support both decimal fixed point and DFP and the new software support for the DFP facility, including IBM z/OS, Java JIT, and C/C++ compilers, as well as support in IBM DB2 and middleware.

rawabstract:
The latest IBM zSeries processor, the IBM System z10 processor, provides hardware support for the decimal floating-point (DFP) facility that was introduced on the IBM System z9 processor. The z9 processor implements the facility with a mixture of low-level software and hardware assists. Recently, the IBM POWER6 processor-based System p 570 server introduced a hardware implementation of the DFP facility. The latest zSeries processor includes a decimal floating-point unit based on the POWER6 processor DFP unit that has been enhanced to also support the traditional zSeries decimal fixed-point instruction set. This paper explains the hardware implementation to support both decimal fixed point and DFP and the new software support for the DFP facility, including IBM z/OS, Java JIT, and C/C++ compilers, as well as support in IBM DB2 and middleware.

entry:
@Article{Schwarz:2009:DFP,
  author =       "E. M. Schwarz and J. S. Kapernick and M. F.
                 Cowlishaw",
  title =        "Decimal floating-point support on the {IBM System z10}
                 processor",
  journal =      j-IBM-JRD,
  volume =       "53",
  number =       "1",
  pages =        "4:1--4:10",
  month =        jan # "\slash " # feb,
  year =         "2009",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Thu Jan 29 14:25:32 MST 2009",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.research.ibm.com/journal/rd/531/schwarz.pdf",
  abstract =     "The latest IBM zSeries processor, the IBM System z10
                 processor, provides hardware support for the decimal
                 floating-point (DFP) facility that was introduced on
                 the IBM System z9 processor. The z9 processor
                 implements the facility with a mixture of low-level
                 software and hardware assists. Recently, the IBM POWER6
                 processor-based System p 570 server introduced a
                 hardware implementation of the DFP facility. The latest
                 zSeries processor includes a decimal floating-point
                 unit based on the POWER6 processor DFP unit that has
                 been enhanced to also support the traditional zSeries
                 decimal fixed-point instruction set. This paper
                 explains the hardware implementation to support both
                 decimal fixed point and DFP and the new software
                 support for the DFP facility, including IBM z/OS, Java
                 JIT, and C/C++ compilers, as well as support in IBM DB2
                 and middleware.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "ARITH-19",
  remark =       "Extended version of ARITH-18 article \cite{}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Shaw:2009:ASM
author: David E. Shaw
title: Anton: a Specialized Machine for Millisecond-Scale Molecular Dynamics Simulations of Proteins
crossref: Bruguera:2009:PIS
pages: 3--3
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: David E. Shaw
rawtitle: {Anton}: a Specialized Machine for Millisecond-Scale Molecular Dynamics Simulations of Proteins
entry:
@InProceedings{Shaw:2009:ASM,
  author =       "David E. Shaw",
  title =        "{Anton}: a Specialized Machine for Millisecond-Scale
                 Molecular Dynamics Simulations of Proteins",
  crossref =     "Bruguera:2009:PIS",
  pages =        "3--3",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: article
filename: fparith.bib
label: Shpilka:2009:IDA
author: Amir Shpilka
title: Interpolation of Depth-3 Arithmetic Circuits with Two Multiplication Gates
journal: j-SIAM-J-COMPUT
volume: 38
number: 6
pages: 2130--2161
year: 2009
CODEN: SMJCAT
ISSN: 0097-5397 (print), 1095-7111 (electronic) OR 00975397 (print), 10957111 (electronic)
ISSNL: 0097-5397 OR 00975397
bibdate: Tue May 18 08:22:06 MDT 2010
bibtimestamp: 2010.05.18 08:22:06 MDT
fjournal: SIAM Journal on Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sicomp
rawauthor: Amir Shpilka
rawtitle: Interpolation of Depth-3 Arithmetic Circuits with Two Multiplication Gates
bibsource:
http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/38/6; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Shpilka:2009:IDA,
  author =       "Amir Shpilka",
  title =        "Interpolation of Depth-3 Arithmetic Circuits with Two
                 Multiplication Gates",
  journal =      j-SIAM-J-COMPUT,
  volume =       "38",
  number =       "6",
  pages =        "2130--2161",
  month =        "????",
  year =         "2009",
  CODEN =        "SMJCAT",
  DOI =          "",
  ISSN =         "0097-5397 (print), 1095-7111 (electronic)",
  ISSN-L =       "0097-5397",
  bibdate =      "Tue May 18 08:22:06 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/38/6;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Computing",
  journal-URL =  "http://epubs.siam.org/sicomp",
}


bibtype: techreport
filename: fparith.bib
label: Stewart:2009:FMP
author: G. W. Stewart
title: Flap: a Matlab Package for Adjustable Precision Floating-Point Arithmetic
type: Report
institution: Department of Computer Science, University of Maryland
address: College Park, MD, USA
pages: 2130--2161
year: 2009
bibdate: Sun Jun 19 13:11:45 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.06.19 13:11:45 ???
URL: http://www.cs.umd.edu/~stewart/flap/flap.html
acknowledgement: ack-nhfb
rawauthor: G. W. Stewart
rawtitle: {Flap}: a {Matlab} Package for Adjustable Precision Floating-Point Arithmetic
abstract:
Flap is a package to implement floating-point arithmetic with adjustable precision. Specifically, operations are performed on Matlab doubles but are rounded to a user specified number of decimal digits after each operation. The number can be changed dynamically. Flap is intended to make it easy to generate examples of the effects of rounding error for classroom use.

rawabstract:
Flap is a package to implement floating-point arithmetic with adjustable precision. Specifically, operations are performed on Matlab doubles but are rounded to a user specified number of decimal digits after each operation. The number can be changed dynamically. Flap is intended to make it easy to generate examples of the effects of rounding error for classroom use.

entry:
@TechReport{Stewart:2009:FMP,
  author =       "G. W. Stewart",
  title =        "{Flap}: a {Matlab} Package for Adjustable Precision
                 Floating-Point Arithmetic",
  type =         "Report",
  institution =  "Department of Computer Science, University of
                 Maryland",
  address =      "College Park, MD, USA",
  year =         "2009",
  bibdate =      "Sun Jun 19 13:11:45 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.umd.edu/~stewart/flap/flap.html",
  abstract =     "Flap is a package to implement floating-point
                 arithmetic with adjustable precision. Specifically,
                 operations are performed on Matlab doubles but are
                 rounded to a user specified number of decimal digits
                 after each operation. The number can be changed
                 dynamically. Flap is intended to make it easy to
                 generate examples of the effects of rounding error for
                 classroom use.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Tajallipour:2009:FCD
author: R. Tajallipour and D. Teng and Seok-Bum Ko and K. Wahid
title: On the fast computation of decimal logarithm
crossref: ICCIT:2009:ICC
pages: 32--36
year: 2009
DOI: https://doi.org/10.1109/ICCIT.2009.5407171
bibdate: Thu Feb 17 08:28:37 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.17 08:28:37 ???
acknowledgement: ack-nhfb
rawauthor: R. Tajallipour and D. Teng and Seok-Bum Ko and K. Wahid
rawtitle: On the fast computation of decimal logarithm
abstract:
The paper presents a new and fast algorithm to efficiently compute radix-10 logarithm of a decimal number. The algorithm uses 32-bit floating-point arithmetic, and is based on a digit-by-digit iterative computation that does not require look-up tables, curve fitting, decimal-binary conversion, or division operations; the number of iterations depends on the user defined precision. The algorithm produces error-free (infinite precision) results up to 7 decimal digits. A numerical example is shown for the purpose of illustration. The accuracy is analyzed for several decimal digits showing compliance with the IEEE 754-2008 Standard. When implemented on to the Xilinx VirtexII FPGA, the architecture costs only 1,053 logic cells, runs at a maximum frequency of 44 MHz, and consumes 79 mW of power.

rawabstract:
The paper presents a new and fast algorithm to efficiently compute radix-10 logarithm of a decimal number. The algorithm uses 32-bit floating-point arithmetic, and is based on a digit-by-digit iterative computation that does not require look-up tables, curve fitting, decimal-binary conversion, or division operations; the number of iterations depends on the user defined precision. The algorithm produces error-free (infinite precision) results up to 7 decimal digits. A numerical example is shown for the purpose of illustration. The accuracy is analyzed for several decimal digits showing compliance with the IEEE 754-2008 Standard. When implemented on to the Xilinx VirtexII FPGA, the architecture costs only 1,053 logic cells, runs at a maximum frequency of 44 MHz, and consumes 79 mW of power.

entry:
@InProceedings{Tajallipour:2009:FCD,
  author =       "R. Tajallipour and D. Teng and Seok-Bum Ko and K.
                 Wahid",
  title =        "On the fast computation of decimal logarithm",
  crossref =     "ICCIT:2009:ICC",
  pages =        "32--36",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ICCIT.2009.5407171",
  bibdate =      "Thu Feb 17 08:28:37 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The paper presents a new and fast algorithm to
                 efficiently compute radix-10 logarithm of a decimal
                 number. The algorithm uses 32-bit floating-point
                 arithmetic, and is based on a digit-by-digit iterative
                 computation that does not require look-up tables, curve
                 fitting, decimal-binary conversion, or division
                 operations; the number of iterations depends on the
                 user defined precision. The algorithm produces
                 error-free (infinite precision) results up to 7 decimal
                 digits. A numerical example is shown for the purpose of
                 illustration. The accuracy is analyzed for several
                 decimal digits showing compliance with the IEEE
                 754-2008 Standard. When implemented on to the Xilinx
                 VirtexII FPGA, the architecture costs only 1,053 logic
                 cells, runs at a maximum frequency of 44 MHz, and
                 consumes 79 mW of power.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Tan:2009:LPM
author: D. Tan and C. E. Lemonds and Michael J. Schulte
title: Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 2
pages: 175--187
month: feb
monthnumber: 2
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.203
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:39 MDT 2011
bibtimestamp: 2011.07.04 11:37:39 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4663060
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. Tan and C. E. Lemonds and Michael J. Schulte
rawtitle: Low-Power Multiple-Precision Iterative Floating-Point Multiplier with {SIMD} Support
abstract:
The demand for improved SIMD floating-point performance on general-purpose x86-compatible microprocessors is rising. At the same time, there is a conflicting demand in the low-power computing market for a reduction in power consumption. Along with this, there is the absolute necessity of backward compatibility for x86-compatible microprocessors, which includes the support of x87 scientific floating-point instructions. The combined effect is that there is a need for low-power, low-cost floating-point units that are still capable of delivering good SIMD performance while maintaining full x86 functionality. This paper presents the design of an x86-compatible floating-point multiplier (FPM) that is compliant with the IEEE-754 Standard for Binary Floating-Point Arithmetic [12] and is specifically tailored to provide good SIMD performance in a low-cost, low-power solution while maintaining full x87 backward compatibility. The FPM efficiently supports multiple precisions using an iterative rectangular multiplier. The FPM can perform two parallel single-precision multiplies every cycle with a latency of two cycles, one double-precision multiply every two cycles with a latency of four cycles, or one extended-double-precision multiply every three cycles with a latency of five cycles. The iterative FPM also supports division, square-root, and transcendental functions. Compared to a previous design with similar functionality, the proposed iterative FPM has 60 percent less area and 59 percent less dynamic power dissipation.

keywords:
Computer arithmetic; floating-point arithmetic; low-power; multimedia; multiplying circuits; rectangular multiplier; very-large-scale integration

rawabstract:
The demand for improved SIMD floating-point performance on general-purpose x86-compatible microprocessors is rising. At the same time, there is a conflicting demand in the low-power computing market for a reduction in power consumption. Along with this, there is the absolute necessity of backward compatibility for x86-compatible microprocessors, which includes the support of x87 scientific floating-point instructions. The combined effect is that there is a need for low-power, low-cost floating-point units that are still capable of delivering good SIMD performance while maintaining full x86 functionality. This paper presents the design of an x86-compatible floating-point multiplier (FPM) that is compliant with the IEEE-754 Standard for Binary Floating-Point Arithmetic [12] and is specifically tailored to provide good SIMD performance in a low-cost, low-power solution while maintaining full x87 backward compatibility. The FPM efficiently supports multiple precisions using an iterative rectangular multiplier. The FPM can perform two parallel single-precision multiplies every cycle with a latency of two cycles, one double-precision multiply every two cycles with a latency of four cycles, or one extended-double-precision multiply every three cycles with a latency of five cycles. The iterative FPM also supports division, square-root, and transcendental functions. Compared to a previous design with similar functionality, the proposed iterative FPM has 60 percent less area and 59 percent less dynamic power dissipation.

entry:
@Article{Tan:2009:LPM,
  author =       "D. Tan and C. E. Lemonds and Michael J. Schulte",
  title =        "Low-Power Multiple-Precision Iterative Floating-Point
                 Multiplier with {SIMD} Support",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "2",
  pages =        "175--187",
  month =        feb,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.203",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4663060",
  abstract =     "The demand for improved SIMD floating-point
                 performance on general-purpose x86-compatible
                 microprocessors is rising. At the same time, there is a
                 conflicting demand in the low-power computing market
                 for a reduction in power consumption. Along with this,
                 there is the absolute necessity of backward
                 compatibility for x86-compatible microprocessors, which
                 includes the support of x87 scientific floating-point
                 instructions. The combined effect is that there is a
                 need for low-power, low-cost floating-point units that
                 are still capable of delivering good SIMD performance
                 while maintaining full x86 functionality. This paper
                 presents the design of an x86-compatible floating-point
                 multiplier (FPM) that is compliant with the IEEE-754
                 Standard for Binary Floating-Point Arithmetic [12] and
                 is specifically tailored to provide good SIMD
                 performance in a low-cost, low-power solution while
                 maintaining full x87 backward compatibility. The FPM
                 efficiently supports multiple precisions using an
                 iterative rectangular multiplier. The FPM can perform
                 two parallel single-precision multiplies every cycle
                 with a latency of two cycles, one double-precision
                 multiply every two cycles with a latency of four
                 cycles, or one extended-double-precision multiply every
                 three cycles with a latency of five cycles. The
                 iterative FPM also supports division, square-root, and
                 transcendental functions. Compared to a previous design
                 with similar functionality, the proposed iterative FPM
                 has 60 percent less area and 59 percent less dynamic
                 power dissipation.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Computer arithmetic; floating-point arithmetic;
                 low-power; multimedia; multiplying circuits;
                 rectangular multiplier; very-large-scale integration",
}


bibtype: inproceedings
filename: fparith.bib
label: Tenca:2009:MOF
author: Alexandre F. Tenca
title: Multi-operand Floating-Point Addition
crossref: Bruguera:2009:PIS
pages: 161--168
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: Alexandre F. Tenca
rawtitle: Multi-operand Floating-Point Addition
abstract:
The design of a component to perform parallel addition of multiple floating-point (FP) operands is explored in this work. In particular, a 3-input FP adder is discussed in more detail, but the main concepts and ideas presented in this work are valid for FP adders with more inputs. The proposed design is more accurate than conventional FP addition using a network of 2-operand FP adders and it may have competitive area and delay depending on the number of input operands. Implementation results of a 3-operand FP adder are presented to compare its performance to a network of 2-input FP adders.

rawabstract:
The design of a component to perform parallel addition of multiple floating-point (FP) operands is explored in this work. In particular, a 3-input FP adder is discussed in more detail, but the main concepts and ideas presented in this work are valid for FP adders with more inputs. The proposed design is more accurate than conventional FP addition using a network of 2-operand FP adders and it may have competitive area and delay depending on the number of input operands. Implementation results of a 3-operand FP adder are presented to compare its performance to a network of 2-input FP adders.

entry:
@InProceedings{Tenca:2009:MOF,
  author =       "Alexandre F. Tenca",
  title =        "Multi-operand Floating-Point Addition",
  crossref =     "Bruguera:2009:PIS",
  pages =        "161--168",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The design of a component to perform parallel addition
                 of multiple floating-point (FP) operands is explored in
                 this work. In particular, a 3-input FP adder is
                 discussed in more detail, but the main concepts and
                 ideas presented in this work are valid for FP adders
                 with more inputs. The proposed design is more accurate
                 than conventional FP addition using a network of
                 2-operand FP adders and it may have competitive area
                 and delay depending on the number of input operands.
                 Implementation results of a 3-operand FP adder are
                 presented to compare its performance to a network of
                 2-input FP adders.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: inproceedings
filename: fparith.bib
label: Tsen:2009:CDB
title: A Combined Decimal and Binary Floating-Point Multiplier
crossref: IEEE:2009:IICa
pages: 8--15
year: 2009
DOI: https://doi.org/10.1109/ASAP.2009.28
bibdate: Sat Dec 04 07:01:08 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.12.04 07:01:08 ???
acknowledgement: ack-nhfb
rawtitle: A Combined Decimal and Binary Floating-Point Multiplier
author:
Charles Tsen and Sonia Gonzalez-Navarro and Michael J. Schulte and Brian Hickmann and Katherine Compton

abstract:
In this paper, we describe the first hardware design of a combined binary and decimal floating-point multiplier, based on specifications in the IEEE 754-2008 floating-point standard. The multiplier design operates on either (1) 64-bit binary encoded decimal floating-point (DFP) numbers or (2) 64-bit binary floating-point (BFP) numbers. It returns properly rounded results for the rounding modes specified in IEEE 754-2008. The design shares the following hardware resources between the two floating-point datatypes: a 54-bit by 54-bit binary multiplier, portions of the operand encoding/decoding, a 54-bit right shifter, exponent calculation logic, and rounding logic. Our synthesis results show that hardware sharing is feasible and has a reasonable impact on area, latency, and delay. The combined BFP and DFP multiplier occupies only 58% of the total area that would be required by separate BFP and DFP units. Furthermore, the critical path delay of a combined multiplier has a negligible increase over a standalone DFP multiplier, without increasing the number of cycles to perform either BFP or DFP multiplication.

keywords:
binary encoded decimal floating-point; binary floating-point multiplier; combined decimal floating-point multiplier design; Commercial Applications; Computer Arithmetic; Decimal Floating-point; exponent calculation logic; floating point arithmetic; Floating-point; Hardware; hardware design; Hardware Reuse; IEEE 754-2008; IEEE 754-2008 floating-point standard; logic design; Multiplication; multiplying circuits; Register-Transfer-Level Implementation; right shifter; rounding logic

rawabstract:
In this paper, we describe the first hardware design of a combined binary and decimal floating-point multiplier, based on specifications in the IEEE 754-2008 floating-point standard. The multiplier design operates on either (1) 64-bit binary encoded decimal floating-point (DFP) numbers or (2) 64-bit binary floating-point (BFP) numbers. It returns properly rounded results for the rounding modes specified in IEEE 754-2008. The design shares the following hardware resources between the two floating-point datatypes: a 54-bit by 54-bit binary multiplier, portions of the operand encoding/decoding, a 54-bit right shifter, exponent calculation logic, and rounding logic. Our synthesis results show that hardware sharing is feasible and has a reasonable impact on area, latency, and delay. The combined BFP and DFP multiplier occupies only 58\% of the total area that would be required by separate BFP and DFP units. Furthermore, the critical path delay of a combined multiplier has a negligible increase over a standalone DFP multiplier, without increasing the number of cycles to perform either BFP or DFP multiplication.

rawauthor:
Charles Tsen and Sonia Gonzalez-Navarro and Michael J. Schulte and Brian Hickmann and Katherine Compton

entry:
@InProceedings{Tsen:2009:CDB,
  author =       "Charles Tsen and Sonia Gonzalez-Navarro and Michael J.
                 Schulte and Brian Hickmann and Katherine Compton",
  title =        "A Combined Decimal and Binary Floating-Point
                 Multiplier",
  crossref =     "IEEE:2009:IICa",
  pages =        "8--15",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ASAP.2009.28",
  bibdate =      "Sat Dec 04 07:01:08 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper, we describe the first hardware design
                 of a combined binary and decimal floating-point
                 multiplier, based on specifications in the IEEE
                 754-2008 floating-point standard. The multiplier design
                 operates on either (1) 64-bit binary encoded decimal
                 floating-point (DFP) numbers or (2) 64-bit binary
                 floating-point (BFP) numbers. It returns properly
                 rounded results for the rounding modes specified in
                 IEEE 754-2008. The design shares the following hardware
                 resources between the two floating-point datatypes: a
                 54-bit by 54-bit binary multiplier, portions of the
                 operand encoding/decoding, a 54-bit right shifter,
                 exponent calculation logic, and rounding logic. Our
                 synthesis results show that hardware sharing is
                 feasible and has a reasonable impact on area, latency,
                 and delay. The combined BFP and DFP multiplier occupies
                 only 58\% of the total area that would be required by
                 separate BFP and DFP units. Furthermore, the critical
                 path delay of a combined multiplier has a negligible
                 increase over a standalone DFP multiplier, without
                 increasing the number of cycles to perform either BFP
                 or DFP multiplication.",
  acknowledgement = ack-nhfb,
  keywords =     "binary encoded decimal floating-point; binary
                 floating-point multiplier; combined decimal
                 floating-point multiplier design; Commercial
                 Applications; Computer Arithmetic; Decimal
                 Floating-point; exponent calculation logic; floating
                 point arithmetic; Floating-point; Hardware; hardware
                 design; Hardware Reuse; IEEE 754-2008; IEEE 754-2008
                 floating-point standard; logic design; Multiplication;
                 multiplying circuits; Register-Transfer-Level
                 Implementation; right shifter; rounding logic",
}


bibtype: techreport
filename: fparith.bib
label: Tydeman:2009:CMC
author: Fred J. Tydeman
type: Report
number: WG14 N1399
pages: 8--15
day: 25
month: sep
monthnumber: 9
year: 2009
bibdate: Mon Sep 30 09:48:02 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.09.30 09:48:02 ???
URL: https://www.open-std.org/jtc1/sc22/wg14/www/docs/n1399.htm
acknowledgement: ack-nhfb
rawauthor: Fred J. Tydeman
title:
Complex Multiply and Complex Divide, taking into account IEEE-754 (IEC 60559) signed zeros, signed infinities, NaN, and C99 _Imaginary_I

rawtitle:
Complex Multiply and Complex Divide, taking into account {IEEE-754 (IEC 60559)} signed zeros, signed infinities, {NaN}, and {C99 \_Imaginary\_I}

entry:
@TechReport{Tydeman:2009:CMC,
  author =       "Fred J. Tydeman",
  title =        "Complex Multiply and Complex Divide, taking into
                 account {IEEE-754 (IEC 60559)} signed zeros, signed
                 infinities, {NaN}, and {C99 \_Imaginary\_I}",
  type =         "Report",
  number =       "WG14 N1399",
  institution =  "????",
  address =      "????",
  day =          "25",
  month =        sep,
  year =         "2009",
  bibdate =      "Mon Sep 30 09:48:02 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.open-std.org/jtc1/sc22/wg14/www/docs/n1399.htm",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Usselmann:2009:FPU
author: R. Usselmann
title: Floating point unit
type: Web report
institution: Algotronix Ltd.
address: Edinburgh EH8 8YB, UK
pages: 8--15
day: 20
month: dec
monthnumber: 12
year: 2009
bibdate: Thu Mar 24 21:02:16 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.03.24 21:02:16 ???
URL: http://opencores.org/project,fpu
remark: Creatred 25-Sep-2001
acknowledgement: ack-nhfb
rawauthor: R. Usselmann
rawtitle: Floating point unit
abstract:
This is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add / Sub, Mul and Divide operations, as well as integer to floating point and floating point to integer conversions. It supports four rounding modes: Round to Nearest Even, Round to Zero, Round to +INF and Round to INF. There is now also a separate FP compare unit. It is located in the tt fpu/fcmp directory.

rawabstract:
This is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add\slash Sub, Mul and Divide operations, as well as integer to floating point and floating point to integer conversions. It supports four rounding modes: Round to Nearest Even, Round to Zero, Round to +INF and Round to INF. There is now also a separate FP compare unit. It is located in the {\tt fpu/fcmp} directory.

entry:
@TechReport{Usselmann:2009:FPU,
  author =       "R. Usselmann",
  title =        "Floating point unit",
  type =         "Web report",
  institution =  "Algotronix Ltd.",
  address =      "Edinburgh EH8 8YB, UK",
  day =          "20",
  month =        dec,
  year =         "2009",
  bibdate =      "Thu Mar 24 21:02:16 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://opencores.org/project,fpu",
  abstract =     "This is a single precision floating point unit. It is
                 fully IEEE 754 compliant. It can currently perform
                 Add\slash Sub, Mul and Divide operations, as well as
                 integer to floating point and floating point to integer
                 conversions. It supports four rounding modes: Round to
                 Nearest Even, Round to Zero, Round to +INF and Round to
                 INF. There is now also a separate FP compare unit. It
                 is located in the {\tt fpu/fcmp} directory.",
  acknowledgement = ack-nhfb,
  remark =       "Creatred 25-Sep-2001",
}


bibtype: article
filename: fparith.bib
label: Van:2009:PEP
author: Lan-Da Van and Jin-Hao Tu
title: Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh--Wooley Multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 10
pages: 1346--1355
month: oct
monthnumber: 10
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2009.89
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:43 MDT 2011
bibtimestamp: 2011.07.04 11:37:43 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5156495
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Lan-Da Van and Jin-Hao Tu
rawtitle: Power-Efficient Pipelined Reconfigurable Fixed-Width {Baugh--Wooley} Multipliers
entry:
@Article{Van:2009:PEP,
  author =       "Lan-Da Van and Jin-Hao Tu",
  title =        "Power-Efficient Pipelined Reconfigurable Fixed-Width
                 {Baugh--Wooley} Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "10",
  pages =        "1346--1355",
  month =        oct,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2009.89",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:43 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5156495",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: VanDenDries:2009:AC
author: Lou Van Den Dries and Yiannis N. Moschovakis
title: Arithmetic complexity
journal: j-TOCL
volume: 10
number: 1
pages: 2:1--2:??
month: jan
monthnumber: 1
year: 2009
DOI: https://doi.org/10.1145/1459010.1459012
ISSN: 1529-3785 (print), 1557-945X (electronic) OR 15293785 (print), 1557945X (electronic)
ISSNL: 1529-3785 OR 15293785
bibdate: Mon Jan 26 18:05:23 MST 2009
bibsource: http://www.acm.org/pubs/contents/journals/tocl/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.01.26 18:05:23 MST
fjournal: ACM Transactions on Computational Logic
keywords: coprimeness; greatest common divisor; Lower bounds for arithmetical problems; recursive programs
acknowledgement: ack-nhfb
articleno: 2
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J773
rawauthor: Lou {Van Den Dries} and Yiannis N. Moschovakis
rawtitle: Arithmetic complexity
abstract:
We obtain em lower bounds on the cost of computing various arithmetic functions and deciding various arithmetic relations from specified primitives. This includes lower bounds for computing the greatest common divisor and deciding coprimeness of two integers, from primitives like addition, subtraction, division with remainder and multiplication. Some of our results are in terms of recursive programs, but they generalize directly to most (plausibly all) algorithms from the specified primitives. Our methods involve some elementary number theory as well as the development of some basic notions and facts about recursive algorithms.

rawabstract:
We obtain {\em lower bounds\/} on the cost of computing various arithmetic functions and deciding various arithmetic relations from specified primitives. This includes lower bounds for computing the greatest common divisor and deciding coprimeness of two integers, from primitives like addition, subtraction, division with remainder and multiplication. Some of our results are in terms of recursive programs, but they generalize directly to most (plausibly all) algorithms from the specified primitives. Our methods involve some elementary number theory as well as the development of some basic notions and facts about recursive algorithms.

entry:
@Article{VanDenDries:2009:AC,
  author =       "Lou {Van Den Dries} and Yiannis N. Moschovakis",
  title =        "Arithmetic complexity",
  journal =      j-TOCL,
  volume =       "10",
  number =       "1",
  pages =        "2:1--2:??",
  month =        jan,
  year =         "2009",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/1459010.1459012",
  ISSN =         "1529-3785 (print), 1557-945X (electronic)",
  ISSN-L =       "1529-3785",
  bibdate =      "Mon Jan 26 18:05:23 MST 2009",
  bibsource =    "http://www.acm.org/pubs/contents/journals/tocl/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We obtain {\em lower bounds\/} on the cost of
                 computing various arithmetic functions and deciding
                 various arithmetic relations from specified primitives.
                 This includes lower bounds for computing the greatest
                 common divisor and deciding coprimeness of two
                 integers, from primitives like addition, subtraction,
                 division with remainder and multiplication. Some of our
                 results are in terms of recursive programs, but they
                 generalize directly to most (plausibly all) algorithms
                 from the specified primitives. Our methods involve some
                 elementary number theory as well as the development of
                 some basic notions and facts about recursive
                 algorithms.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Transactions on Computational Logic",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J773",
  keywords =     "coprimeness; greatest common divisor; Lower bounds for
                 arithmetical problems; recursive programs",
}


bibtype: inproceedings
filename: fparith.bib
label: Vazquez:2009:CDT
author: Alvaro Vazquez and Julio Villalba and Elisardo Antelo
title: Computation of Decimal Transcendental Functions Using the CORDIC Algorithm
crossref: Bruguera:2009:PIS
pages: 179--186
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: {\'A}lvaro V{\'a}zquez and Julio Villalba and Elisardo Antelo
rawtitle: Computation of Decimal Transcendental Functions Using the {CORDIC} Algorithm
abstract:
In this work we propose new decimal floating-point CORDIC algorithms for transcendental function evaluation. We show how these algorithms are mapped to a state of the art Decimal Floating-Point Unit (DFPU), both considering the use of a carry-propagate adder or a carry-save redundant adder. We compared with previous decimal CORDIC proposals and with table-driven algorithms, and we concluded that our approach have significant potential advantages for transcendental function evaluation in state of the art DFPUs with minor modifications of the hardware.

rawabstract:
In this work we propose new decimal floating-point CORDIC algorithms for transcendental function evaluation. We show how these algorithms are mapped to a state of the art Decimal Floating-Point Unit (DFPU), both considering the use of a carry-propagate adder or a carry-save redundant adder. We compared with previous decimal CORDIC proposals and with table-driven algorithms, and we concluded that our approach have significant potential advantages for transcendental function evaluation in state of the art DFPUs with minor modifications of the hardware.

entry:
@InProceedings{Vazquez:2009:CDT,
  author =       "{\'A}lvaro V{\'a}zquez and Julio Villalba and Elisardo
                 Antelo",
  title =        "Computation of Decimal Transcendental Functions Using
                 the {CORDIC} Algorithm",
  crossref =     "Bruguera:2009:PIS",
  pages =        "179--186",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this work we propose new decimal floating-point
                 CORDIC algorithms for transcendental function
                 evaluation. We show how these algorithms are mapped to
                 a state of the art Decimal Floating-Point Unit (DFPU),
                 both considering the use of a carry-propagate adder or
                 a carry-save redundant adder. We compared with previous
                 decimal CORDIC proposals and with table-driven
                 algorithms, and we concluded that our approach have
                 significant potential advantages for transcendental
                 function evaluation in state of the art DFPUs with
                 minor modifications of the hardware.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: inproceedings
filename: fparith.bib
label: Vazquez:2009:HPS
author: Alvaro Vazquez and Elisardo Antelo
title: A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding
crossref: Bruguera:2009:PIS
pages: 135--144
year: 2009
DOI: https://doi.org/10.1109/ARITH.2009.30
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: {\'A}lvaro V{\'a}zquez and Elisardo Antelo
rawtitle: A High-Performance Significand {BCD} Adder with {IEEE 754-2008} Decimal Rounding
abstract:
We present a new method and architecture to merge efficiently IEEE 754-2008 decimal rounding with significand BCD addition and subtraction. This is a key component to improve several decimal floating-point operations such as addition, multiplication and fused multiply-add. The decimal rounding unit is based on a direct implementation of the IEEE 754-2008 rounding modes. We show that the resultant implementations for IEEE 754-2008 Decimal64 (16 precision digits) and Decimal128 (34 precision digits) formats reduce significantly the area and latency required for significand BCD addition/subtraction and decimal rounding in previous high-performance decimal floating-point adders.

rawabstract:
We present a new method and architecture to merge efficiently IEEE 754-2008 decimal rounding with significand BCD addition and subtraction. This is a key component to improve several decimal floating-point operations such as addition, multiplication and fused multiply-add. The decimal rounding unit is based on a direct implementation of the IEEE 754-2008 rounding modes. We show that the resultant implementations for IEEE 754-2008 Decimal64 (16 precision digits) and Decimal128 (34 precision digits) formats reduce significantly the area and latency required for significand BCD addition/subtraction and decimal rounding in previous high-performance decimal floating-point adders.

entry:
@InProceedings{Vazquez:2009:HPS,
  author =       "{\'A}lvaro V{\'a}zquez and Elisardo Antelo",
  title =        "A High-Performance Significand {BCD} Adder with {IEEE
                 754-2008} Decimal Rounding",
  crossref =     "Bruguera:2009:PIS",
  pages =        "135--144",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ARITH.2009.30",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a new method and architecture to merge
                 efficiently IEEE 754-2008 decimal rounding with
                 significand BCD addition and subtraction. This is a key
                 component to improve several decimal floating-point
                 operations such as addition, multiplication and fused
                 multiply-add. The decimal rounding unit is based on a
                 direct implementation of the IEEE 754-2008 rounding
                 modes. We show that the resultant implementations for
                 IEEE 754-2008 Decimal64 (16 precision digits) and
                 Decimal128 (34 precision digits) formats reduce
                 significantly the area and latency required for
                 significand BCD addition/subtraction and decimal
                 rounding in previous high-performance decimal
                 floating-point adders.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: inproceedings
filename: fparith.bib
label: Verma:2009:CAO
author: Ajay K. Verma and Philip Brisk and Paolo Ienne
title: Challenges in Automatic Optimization of Arithmetic Circuits
crossref: Bruguera:2009:PIS
pages: 213--218
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: Ajay K. Verma and Philip Brisk and Paolo Ienne
rawtitle: Challenges in Automatic Optimization of Arithmetic Circuits
abstract:
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, especially for arithmetic circuits. In many cases, the outcome of even the most advanced synthesis techniques is highly dependent on the input description of the circuit, and the optimizations themselves barely modify the architecture of the circuit itself. Once the input description is converted to an appropriate architecture, logic synthesis performs local optimizations quite effectively; however, finding the best architecture up front is a nontrivial problem. This paper reviews recent results in arithmetic logic synthesis that the authors have published in recent years. Progress has clearly been made, but much further work is still needed to narrow the gap between the effectiveness of logic synthesis techniques for arithmetic and control-oriented circuits.

rawabstract:
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, especially for arithmetic circuits. In many cases, the outcome of even the most advanced synthesis techniques is highly dependent on the input description of the circuit, and the optimizations themselves barely modify the architecture of the circuit itself. Once the input description is converted to an appropriate architecture, logic synthesis performs local optimizations quite effectively; however, finding the best architecture up front is a nontrivial problem. This paper reviews recent results in arithmetic logic synthesis that the authors have published in recent years. Progress has clearly been made, but much further work is still needed to narrow the gap between the effectiveness of logic synthesis techniques for arithmetic and control-oriented circuits.

entry:
@InProceedings{Verma:2009:CAO,
  author =       "Ajay K. Verma and Philip Brisk and Paolo Ienne",
  title =        "Challenges in Automatic Optimization of Arithmetic
                 Circuits",
  crossref =     "Bruguera:2009:PIS",
  pages =        "213--218",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Despite the impressive progress of logic synthesis in
                 the past decade, finding the best architecture for a
                 given circuit still remains an open and largely
                 unsolved problem, especially for arithmetic circuits.
                 In many cases, the outcome of even the most advanced
                 synthesis techniques is highly dependent on the input
                 description of the circuit, and the optimizations
                 themselves barely modify the architecture of the
                 circuit itself. Once the input description is converted
                 to an appropriate architecture, logic synthesis
                 performs local optimizations quite effectively;
                 however, finding the best architecture up front is a
                 nontrivial problem. This paper reviews recent results
                 in arithmetic logic synthesis that the authors have
                 published in recent years. Progress has clearly been
                 made, but much further work is still needed to narrow
                 the gap between the effectiveness of logic synthesis
                 techniques for arithmetic and control-oriented
                 circuits.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: inproceedings
filename: fparith.bib
label: Vuillemin:2009:EDS
author: Jean E. Vuillemin
title: Efficient Data Structure and Algorithms for Sparse Integers, Sets and Predicates
crossref: Bruguera:2009:PIS
pages: 7--14
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
acknowledgement: ack-nhfb
rawauthor: Jean E. Vuillemin
rawtitle: Efficient Data Structure and Algorithms for Sparse Integers, Sets and Predicates
abstract:
We construct a natural number $ n > 1 $ by trichotomy $$ n = g + x_p d, x_p = 2^2^p, 0 leq g < x_p, 0 < d < x_p $$ applied recursively, and by systematically sharing nodes with equal integer value. The resulting Integer Decision Diagram IDD is a directed acyclic graph DAG which represents $n$ by $ S(n) $ nodes in computer memory. IDDs compete with bit-arrays, which represent the consecutive bits of $n$ within roughly $ l(n) $ contiguous bits in memory. Unlike the binary length $ l(n) $, the size $ S(n) $ is not monotonic. Most integers are dense: their size is near worst & average. The IDD size of sparse integers is arbitrarily smaller.par Over dense numbers, the worst / average time / space complexity of IDDs arithmetic operations is proportional to that of bit-arrays. Yet, equality testing is performed in unit time with IDDs and the time / space complexity of some operations (e.g. $ textrm sign(n - m), n pm 2^m, 2^2^n $) are (at least) exponentially better with IDDs than with bit-arrays, even over dense operands. Over sparse operands, the time and space complexity of all ALU operations $ cap , cup , oplus , +, - $ are (in general) arbitrarily better with IDDs than bit-arrays.par The coding powers of integers lets IDDs implement integer sets and predicates as well as arithmetics. The IDD package is a one-shop alternative to 3 (and more) successful yet rather different packages for processing large numbers, dictionaries and Boolean functions. Performance levels are comparable over dense structures, and IDDs prove best in class over sparse structures.

keywords:
ARITH-19; boolean functions; decision diagrams IDD/BDD/BMD/ZDD; dictionaries; integer dichotomy and trichotomy; sparse numbers; store/compute/code once

rawabstract:
We construct a natural number $ n > 1 $ by trichotomy $$ n = g + x_p d, x_p = 2^{2^p}, 0 \leq g < x_p, 0 < d < x_p $$ applied recursively, and by systematically sharing nodes with equal integer value. The resulting Integer Decision Diagram IDD is a directed acyclic graph DAG which represents $n$ by $ S(n) $ nodes in computer memory. IDDs compete with bit-arrays, which represent the consecutive bits of $n$ within roughly $ l(n) $ contiguous bits in memory. Unlike the binary length $ l(n) $, the size $ S(n) $ is not monotonic. Most integers are dense: their size is near worst & average. The IDD size of sparse integers is arbitrarily smaller.\par Over dense numbers, the worst\slash average time\slash space complexity of IDDs arithmetic operations is proportional to that of bit-arrays. Yet, equality testing is performed in unit time with IDDs and the time\slash space complexity of some operations (e.g. $ \textrm {sign}(n - m), n \pm 2^m, 2^{2^n} $) are (at least) exponentially better with IDDs than with bit-arrays, even over dense operands. Over sparse operands, the time and space complexity of all ALU operations $ \{ \cap, \cup, \oplus, +, - \} $ are (in general) arbitrarily better with IDDs than bit-arrays.\par The coding powers of integers lets IDDs implement integer sets and predicates as well as arithmetics. The IDD package is a one-shop alternative to 3 (and more) successful yet rather different packages for processing large numbers, dictionaries and Boolean functions. Performance levels are comparable over dense structures, and IDDs prove best in class over sparse structures.

entry:
@InProceedings{Vuillemin:2009:EDS,
  author =       "Jean E. Vuillemin",
  title =        "Efficient Data Structure and Algorithms for Sparse
                 Integers, Sets and Predicates",
  crossref =     "Bruguera:2009:PIS",
  pages =        "7--14",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We construct a natural number $ n > 1 $ by trichotomy
                 $$ n = g + x_p d, x_p = 2^{2^p}, 0 \leq g < x_p, 0 < d
                 < x_p $$ applied recursively, and by systematically
                 sharing nodes with equal integer value. The resulting
                 Integer Decision Diagram IDD is a directed acyclic
                 graph DAG which represents $n$ by $ S(n) $ nodes in
                 computer memory. IDDs compete with bit-arrays, which
                 represent the consecutive bits of $n$ within roughly $
                 l(n) $ contiguous bits in memory. Unlike the binary
                 length $ l(n) $, the size $ S(n) $ is not monotonic.
                 Most integers are dense: their size is near worst &
                 average. The IDD size of sparse integers is arbitrarily
                 smaller.\par

                 Over dense numbers, the worst\slash average time\slash
                 space complexity of IDDs arithmetic operations is
                 proportional to that of bit-arrays. Yet, equality
                 testing is performed in unit time with IDDs and the
                 time\slash space complexity of some operations (e.g. $
                 \textrm {sign}(n - m), n \pm 2^m, 2^{2^n} $) are (at
                 least) exponentially better with IDDs than with
                 bit-arrays, even over dense operands.

                 Over sparse operands, the time and space complexity of
                 all ALU operations $ \{ \cap, \cup, \oplus, +, - \} $
                 are (in general) arbitrarily better with IDDs than
                 bit-arrays.\par

                 The coding powers of integers lets IDDs implement
                 integer sets and predicates as well as arithmetics. The
                 IDD package is a one-shop alternative to 3 (and more)
                 successful yet rather different packages for processing
                 large numbers, dictionaries and Boolean functions.
                 Performance levels are comparable over dense
                 structures, and IDDs prove best in class over sparse
                 structures.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19; boolean functions; decision diagrams
                 IDD/BDD/BMD/ZDD; dictionaries; integer dichotomy and
                 trichotomy; sparse numbers; store/compute/code once",
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:2009:DFP
author: Liang-Kai Wang and Michael J. Schulte
title: A Decimal Floating-Point Adder with Decoded Operands and a Decimal Leading-Zero Anticipator
crossref: Bruguera:2009:PIS
pages: 125--134
year: 2009
DOI: https://doi.org/10.1109/ARITH.2009.9
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: Liang-Kai Wang and Michael J. Schulte
rawtitle: A Decimal Floating-Point Adder with Decoded Operands and a Decimal Leading-Zero Anticipator
abstract:
The IEEE 754-2008 Standard for Floating-Point Arithmetic was of officially approved this year. One of the most important revisions to IEEE 754-1985 is the introduction of decimal floating-point (DFP) formats and operations. Since IEEE 754-1985 was revised, major microprocessor vendors have been working on hardware designs and software libraries for decimal arithmetic. Because the new standard has been approved, many software vendors are planning to adapt the new decimal formats into their applications. Therefore, it is important to investigate efficient algorithms and hardware designs for common DFP arithmetic operations to improve the performance of these applications. This paper presents a novel DFP adder with decoded operands and a decimal leading-zero anticipator (LZA). The DFP adder is based on a previous DFP adder design with several new features, including a new internal format, an improved operand pre-correction stage, and a novel decimal LZA to obtain better timing for decimal addition and subtraction. Synthesis results show that the new DFP adder is roughly 14% faster than the previous design.

rawabstract:
The IEEE 754-2008 Standard for Floating-Point Arithmetic was of officially approved this year. One of the most important revisions to IEEE 754-1985 is the introduction of decimal floating-point (DFP) formats and operations. Since IEEE 754-1985 was revised, major microprocessor vendors have been working on hardware designs and software libraries for decimal arithmetic. Because the new standard has been approved, many software vendors are planning to adapt the new decimal formats into their applications. Therefore, it is important to investigate efficient algorithms and hardware designs for common DFP arithmetic operations to improve the performance of these applications. This paper presents a novel DFP adder with decoded operands and a decimal leading-zero anticipator (LZA). The DFP adder is based on a previous DFP adder design with several new features, including a new internal format, an improved operand pre-correction stage, and a novel decimal LZA to obtain better timing for decimal addition and subtraction. Synthesis results show that the new DFP adder is roughly 14\% faster than the previous design.

entry:
@InProceedings{Wang:2009:DFP,
  author =       "Liang-Kai Wang and Michael J. Schulte",
  title =        "A Decimal Floating-Point Adder with Decoded Operands
                 and a Decimal Leading-Zero Anticipator",
  crossref =     "Bruguera:2009:PIS",
  pages =        "125--134",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ARITH.2009.9",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The IEEE 754-2008 Standard for Floating-Point
                 Arithmetic was of officially approved this year. One of
                 the most important revisions to IEEE 754-1985 is the
                 introduction of decimal floating-point (DFP) formats
                 and operations. Since IEEE 754-1985 was revised, major
                 microprocessor vendors have been working on hardware
                 designs and software libraries for decimal arithmetic.
                 Because the new standard has been approved, many
                 software vendors are planning to adapt the new decimal
                 formats into their applications. Therefore, it is
                 important to investigate efficient algorithms and
                 hardware designs for common DFP arithmetic operations
                 to improve the performance of these applications. This
                 paper presents a novel DFP adder with decoded operands
                 and a decimal leading-zero anticipator (LZA). The DFP
                 adder is based on a previous DFP adder design with
                 several new features, including a new internal format,
                 an improved operand pre-correction stage, and a novel
                 decimal LZA to obtain better timing for decimal
                 addition and subtraction. Synthesis results show that
                 the new DFP adder is roughly 14\% faster than the
                 previous design.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: article
filename: fparith.bib
label: Wang:2009:HDD
author: Liang-Kai Wang and Michael J. Schulte and J. D. Thompson and N. Jairam
title: Hardware Designs for Decimal Floating-Point Addition and Related Operations
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 3
pages: 322--335
month: mar
monthnumber: 3
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.147
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:40 MDT 2011
bibtimestamp: 2011.07.04 11:37:40 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4599577
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Liang-Kai Wang and Michael J. Schulte and J. D. Thompson and N. Jairam
rawtitle: Hardware Designs for Decimal Floating-Point Addition and Related Operations
abstract:
Decimal arithmetic is often used in commercial, financial, and Internet-based applications. Due to the growing importance of decimal floating-point (DFP) arithmetic, the IEEE 754-2008 Standard for Floating-Point Arithmetic (IEEE 754-2008) includes specifications for DFP arithmetic. IBM recently announced adding DFP instructions to their POWER6, z9, and z10 microprocessor architectures. As processor support for DFP arithmetic emerges, it is important to investigate efficient arithmetic algorithms and hardware designs for common DFP arithmetic operations. This paper gives an overview of DFP arithmetic in IEEE 754-2008 and discusses previous research on decimal fixed-point and floating-point addition. It also presents novel designs for a DFP adder and a DFP multifunction unit (DFP MFU) that comply with IEEE 754-2008. To reduce their delay, the DFP adder and MFU use decimal injection-based rounding, a new form of decimal operand alignment, and a fast flag-based method for rounding and overflow detection. Synthesis results indicate that the proposed DFP adder is roughly 21 percent faster and 1.6 percent smaller than a previous DFP adder design, when implemented in the same technology. Compared to the DFP adder, the DFP MFU provides six additional operations, yet only has 2.8 percent more delay and 9.7 percent more area. A pipelined version of the DFP MFU has a latency of six cycles, a throughput of one result per cycle, an estimated critical path delay of 12.9 fanout-of-four (FO4) inverter delays, and an estimated area of 45,681 NAND2 equivalent gates.

keywords:
addition; computer arithmetic; Decimal; floating-point; logic design; multifunction unit; subtraction

rawabstract:
Decimal arithmetic is often used in commercial, financial, and Internet-based applications. Due to the growing importance of decimal floating-point (DFP) arithmetic, the IEEE 754-2008 Standard for Floating-Point Arithmetic (IEEE 754-2008) includes specifications for DFP arithmetic. IBM recently announced adding DFP instructions to their POWER6, z9, and z10 microprocessor architectures. As processor support for DFP arithmetic emerges, it is important to investigate efficient arithmetic algorithms and hardware designs for common DFP arithmetic operations. This paper gives an overview of DFP arithmetic in IEEE 754-2008 and discusses previous research on decimal fixed-point and floating-point addition. It also presents novel designs for a DFP adder and a DFP multifunction unit (DFP MFU) that comply with IEEE 754-2008. To reduce their delay, the DFP adder and MFU use decimal injection-based rounding, a new form of decimal operand alignment, and a fast flag-based method for rounding and overflow detection. Synthesis results indicate that the proposed DFP adder is roughly 21 percent faster and 1.6 percent smaller than a previous DFP adder design, when implemented in the same technology. Compared to the DFP adder, the DFP MFU provides six additional operations, yet only has 2.8 percent more delay and 9.7 percent more area. A pipelined version of the DFP MFU has a latency of six cycles, a throughput of one result per cycle, an estimated critical path delay of 12.9 fanout-of-four (FO4) inverter delays, and an estimated area of 45,681 NAND2 equivalent gates.

entry:
@Article{Wang:2009:HDD,
  author =       "Liang-Kai Wang and Michael J. Schulte and J. D.
                 Thompson and N. Jairam",
  title =        "Hardware Designs for Decimal Floating-Point Addition
                 and Related Operations",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "3",
  pages =        "322--335",
  month =        mar,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.147",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:40 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4599577",
  abstract =     "Decimal arithmetic is often used in commercial,
                 financial, and Internet-based applications. Due to the
                 growing importance of decimal floating-point (DFP)
                 arithmetic, the IEEE 754-2008 Standard for
                 Floating-Point Arithmetic (IEEE 754-2008) includes
                 specifications for DFP arithmetic. IBM recently
                 announced adding DFP instructions to their POWER6, z9,
                 and z10 microprocessor architectures. As processor
                 support for DFP arithmetic emerges, it is important to
                 investigate efficient arithmetic algorithms and
                 hardware designs for common DFP arithmetic operations.
                 This paper gives an overview of DFP arithmetic in IEEE
                 754-2008 and discusses previous research on decimal
                 fixed-point and floating-point addition. It also
                 presents novel designs for a DFP adder and a DFP
                 multifunction unit (DFP MFU) that comply with IEEE
                 754-2008. To reduce their delay, the DFP adder and MFU
                 use decimal injection-based rounding, a new form of
                 decimal operand alignment, and a fast flag-based method
                 for rounding and overflow detection. Synthesis results
                 indicate that the proposed DFP adder is roughly 21
                 percent faster and 1.6 percent smaller than a previous
                 DFP adder design, when implemented in the same
                 technology. Compared to the DFP adder, the DFP MFU
                 provides six additional operations, yet only has 2.8
                 percent more delay and 9.7 percent more area. A
                 pipelined version of the DFP MFU has a latency of six
                 cycles, a throughput of one result per cycle, an
                 estimated critical path delay of 12.9 fanout-of-four
                 (FO4) inverter delays, and an estimated area of 45,681
                 NAND2 equivalent gates.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "addition; computer arithmetic; Decimal;
                 floating-point; logic design; multifunction unit;
                 subtraction",
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:2009:RCD
author: Dong Wang and M. D. Ercegovac and Nanning Zheng
title: A radix-8 complex divider for FPGA implementation
crossref: IEEE:2009:ICF
pages: 236--241
year: 2009
DOI: https://doi.org/10.1109/FPL.2009.5272300
bibdate: Fri Dec 03 15:33:08 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.12.03 15:33:08 ???
acknowledgement: ack-nhfb
rawauthor: Dong Wang and M. D. Ercegovac and Nanning Zheng
rawtitle: A radix-8 complex divider for {FPGA} implementation
abstract:
We present a design of a radix-8 complex division for fixed-point operands suitable for FPGA implementation. The design, consisting of operands' prescaling and digit recurrence, shares logic resources and optimizes the use of 6-input LUTs of FPGA devices for efficient design. An optimized single table for prescaling factors is developed. The design is implemented in Altera Stratix-II FPGA for several operands precisions and compared in cost, latency and power with a design using non-shared resources and with an IP-based design. The results show advantages of the proposed design in cost, delay, and power.

keywords:
Altera Stratix-II FPGA; digit recurrence; dividing circuits; field programmable gate arrays; IP-based design; logic resources; non-shared resources; operand prescaling; radix-8 complex divider

rawabstract:
We present a design of a radix-8 complex division for fixed-point operands suitable for FPGA implementation. The design, consisting of operands' prescaling and digit recurrence, shares logic resources and optimizes the use of 6-input LUTs of FPGA devices for efficient design. An optimized single table for prescaling factors is developed. The design is implemented in Altera Stratix-II FPGA for several operands precisions and compared in cost, latency and power with a design using non-shared resources and with an IP-based design. The results show advantages of the proposed design in cost, delay, and power.

entry:
@InProceedings{Wang:2009:RCD,
  author =       "Dong Wang and M. D. Ercegovac and Nanning Zheng",
  title =        "A radix-8 complex divider for {FPGA} implementation",
  crossref =     "IEEE:2009:ICF",
  pages =        "236--241",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/FPL.2009.5272300",
  bibdate =      "Fri Dec 03 15:33:08 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a design of a radix-8 complex division for
                 fixed-point operands suitable for FPGA implementation.
                 The design, consisting of operands' prescaling and
                 digit recurrence, shares logic resources and optimizes
                 the use of 6-input LUTs of FPGA devices for efficient
                 design. An optimized single table for prescaling
                 factors is developed. The design is implemented in
                 Altera Stratix-II FPGA for several operands precisions
                 and compared in cost, latency and power with a design
                 using non-shared resources and with an IP-based design.
                 The results show advantages of the proposed design in
                 cost, delay, and power.",
  acknowledgement = ack-nhfb,
  keywords =     "Altera Stratix-II FPGA; digit recurrence; dividing
                 circuits; field programmable gate arrays; IP-based
                 design; logic resources; non-shared resources; operand
                 prescaling; radix-8 complex divider",
}


bibtype: manual
filename: fparith.bib
label: XILINX:2009:XLF
author: XILINX
title: XILINX LogiCORE floating-point operator v5.0 product specification
organization: Xilinx, Inc.
pages: 236--241
day: 24
month: jun
monthnumber: 6
year: 2009
bibdate: Sat Oct 9 13:09:37 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 13:09:37 ???
URL: http://www.xilinx.com/support/documentation/ip_documentation/floating_point_ds335.pdf
acknowledgement: ack-nhfb
rawauthor: {XILINX}
rawtitle: {XILINX LogiCORE} floating-point operator v5.0 product specification
entry:
@Manual{XILINX:2009:XLF,
  author =       "{XILINX}",
  title =        "{XILINX LogiCORE} floating-point operator v5.0 product
                 specification",
  organization = "Xilinx, Inc.",
  day =          "24",
  month =        jun,
  year =         "2009",
  bibdate =      "Sat Oct 9 13:09:37 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.xilinx.com/support/documentation/ip_documentation/floating_point_ds335.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Zhu:2009:CRH
author: Yong-Kang Zhu and Wayne B. Hayes
title: Correct Rounding and a Hybrid Approach to Exact Floating-Point Summation
journal: j-SIAM-J-SCI-COMP
volume: 31
number: 4
pages: 2981--3001
year: 2009
CODEN: SJOCE3
DOI: https://doi.org/10.1137/070710020
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Wed May 19 10:44:18 MDT 2010
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/SISC/31/4; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.19 10:44:18 MDT
fjournal: SIAM Journal on Scientific Computing
keywords: accurate floating-point summation; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: Yong-Kang Zhu and Wayne B. Hayes
rawtitle: Correct Rounding and a Hybrid Approach to Exact Floating-Point Summation
abstract:
We present two algorithms for computing correctly rounded sums of arrays of floating-point numbers. First, iFastSum improves upon our previous FastSum by requiring no additional space beyond the original array, which is destroyed. It runs about 20% faster than FastSum in the general case and two times faster when extremely ill-conditioned data are used. The second algorithm is HybridSum, which combines three summation ideas together: splitting the mantissa, radix sorting, and using iFastSum. The result is that when the number of summands is greater than about $ 10^4 $, for a given $n$ its running time is almost a constant, independent of the condition number. It runs almost as fast as iFastSum in the general case and much faster than iFastSum when ill-conditioned data are used. HybridSum requires only one pass through the input array and uses constant storage, and it is thus suitable for exact summation as an ``online'' algorithm. Neither algorithm requires extra precision accumulators, and both work in any base. Their accuracy is guaranteed independent of the condition number and the number of summands.

rawabstract:
We present two algorithms for computing correctly rounded sums of arrays of floating-point numbers. First, iFastSum improves upon our previous FastSum by requiring no additional space beyond the original array, which is destroyed. It runs about 20\% faster than FastSum in the general case and two times faster when extremely ill-conditioned data are used. The second algorithm is HybridSum, which combines three summation ideas together: splitting the mantissa, radix sorting, and using iFastSum. The result is that when the number of summands is greater than about $ 10^4 $, for a given $n$ its running time is almost a constant, independent of the condition number. It runs almost as fast as iFastSum in the general case and much faster than iFastSum when ill-conditioned data are used. HybridSum requires only one pass through the input array and uses constant storage, and it is thus suitable for exact summation as an ``online'' algorithm. Neither algorithm requires extra precision accumulators, and both work in any base. Their accuracy is guaranteed independent of the condition number and the number of summands.

entry:
@Article{Zhu:2009:CRH,
  author =       "Yong-Kang Zhu and Wayne B. Hayes",
  title =        "Correct Rounding and a Hybrid Approach to Exact
                 Floating-Point Summation",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "31",
  number =       "4",
  pages =        "2981--3001",
  month =        "????",
  year =         "2009",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/070710020",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Wed May 19 10:44:18 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/31/4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present two algorithms for computing correctly
                 rounded sums of arrays of floating-point numbers.
                 First, iFastSum improves upon our previous FastSum by
                 requiring no additional space beyond the original
                 array, which is destroyed. It runs about 20\% faster
                 than FastSum in the general case and two times faster
                 when extremely ill-conditioned data are used. The
                 second algorithm is HybridSum, which combines three
                 summation ideas together: splitting the mantissa, radix
                 sorting, and using iFastSum. The result is that when
                 the number of summands is greater than about $ 10^4 $,
                 for a given $n$ its running time is almost a constant,
                 independent of the condition number. It runs almost as
                 fast as iFastSum in the general case and much faster
                 than iFastSum when ill-conditioned data are used.
                 HybridSum requires only one pass through the input
                 array and uses constant storage, and it is thus
                 suitable for exact summation as an ``online''
                 algorithm. Neither algorithm requires extra precision
                 accumulators, and both work in any base. Their accuracy
                 is guaranteed independent of the condition number and
                 the number of summands.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "accurate floating-point summation; correct rounding;
                 floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Zimmermann:2009:DSS
author: Reto Zimmermann
title: Datapath Synthesis for Standard-Cell Design
crossref: Bruguera:2009:PIS
pages: 207--211
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: Reto Zimmermann
rawtitle: Datapath Synthesis for Standard-Cell Design
abstract:
Datapath synthesis for standard-cell design goes through extraction of arithmetic operations from RTL code, high-level arithmetic optimizations and netlist generation. Numerous architectures and optimization strategies exist that result in circuit implementations with very different performance characteristics. This work summarizes the circuit architectures and techniques used in a commercial synthesis tool to optimize cell-based datapath netlists for timing, area and power.

rawabstract:
Datapath synthesis for standard-cell design goes through extraction of arithmetic operations from RTL code, high-level arithmetic optimizations and netlist generation. Numerous architectures and optimization strategies exist that result in circuit implementations with very different performance characteristics. This work summarizes the circuit architectures and techniques used in a commercial synthesis tool to optimize cell-based datapath netlists for timing, area and power.

entry:
@InProceedings{Zimmermann:2009:DSS,
  author =       "Reto Zimmermann",
  title =        "Datapath Synthesis for Standard-Cell Design",
  crossref =     "Bruguera:2009:PIS",
  pages =        "207--211",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Datapath synthesis for standard-cell design goes
                 through extraction of arithmetic operations from RTL
                 code, high-level arithmetic optimizations and netlist
                 generation. Numerous architectures and optimization
                 strategies exist that result in circuit implementations
                 with very different performance characteristics. This
                 work summarizes the circuit architectures and
                 techniques used in a commercial synthesis tool to
                 optimize cell-based datapath netlists for timing, area
                 and power.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: article
filename: fparith.bib
label: Akbarpour:2010:VSI
author: Behzad Akbarpour and Amr T. Abdel-Hamid and Sofiene Tahar and John Harrison
title: Verifying a Synthesized Implementation of IEEE-754 Floating-Point Exponential Function using HOL
journal: j-COMP-J
volume: 53
number: 4
pages: 465--488
month: may
monthnumber: 5
year: 2010
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxp023
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Wed Apr 28 14:33:36 MDT 2010
bibtimestamp: 2010.04.28 14:33:36 MDT
fjournal: The Computer Journal
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: Behzad Akbarpour and Amr T. Abdel-Hamid and Sofi{\`e}ne Tahar and John Harrison
bibsource:
http://comjnl.oxfordjournals.org/content/vol53/issue4/index.dtl; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://comjnl.oxfordjournals.org/cgi/content/abstract/53/4/465; http://comjnl.oxfordjournals.org/cgi/reprint/53/4/465

rawtitle:
Verifying a Synthesized Implementation of {IEEE-754} Floating-Point Exponential Function using {HOL}

entry:
@Article{Akbarpour:2010:VSI,
  author =       "Behzad Akbarpour and Amr T. Abdel-Hamid and
                 Sofi{\`e}ne Tahar and John Harrison",
  title =        "Verifying a Synthesized Implementation of {IEEE-754}
                 Floating-Point Exponential Function using {HOL}",
  journal =      j-COMP-J,
  volume =       "53",
  number =       "4",
  pages =        "465--488",
  month =        may,
  year =         "2010",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxp023",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Wed Apr 28 14:33:36 MDT 2010",
  bibsource =    "http://comjnl.oxfordjournals.org/content/vol53/issue4/index.dtl;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://comjnl.oxfordjournals.org/cgi/content/abstract/53/4/465;
                 http://comjnl.oxfordjournals.org/cgi/reprint/53/4/465",
  acknowledgement = ack-nhfb,
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
}


bibtype: article
filename: fparith.bib
label: Aldous:2010:WCO
author: David Aldous and Tung Phan
title: When Can One Test an Explanation? Compare and Contras Benford's Law and the Fuzzy CLT
journal: j-AMER-STAT
volume: 64
number: 3
pages: 221--227
month: aug
monthnumber: 8
year: 2010
CODEN: ASTAAJ
DOI: https://doi.org/10.1198/tast.2010.09098
ISSN: 0003-1305 (print), 1537-2731 (electronic) OR 00031305 (print), 15372731 (electronic)
ISSNL: 0003-1305 OR 00031305
bibdate: Thu Aug 26 21:48:27 MDT 2010
bibtimestamp: 2010.08.26 21:48:27 MDT
fjournal: The American Statistician
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/utas20
rawauthor: David Aldous and Tung Phan
rawtitle: When Can One Test an Explanation? Compare and Contras {Benford's Law} and the Fuzzy {CLT}
bibsource:
http://www.amstat.org/publications/tas/; https://www.math.utah.edu/pub/tex/bib/amstat.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Aldous:2010:WCO,
  author =       "David Aldous and Tung Phan",
  title =        "When Can One Test an Explanation? Compare and Contras
                 {Benford's Law} and the Fuzzy {CLT}",
  journal =      j-AMER-STAT,
  volume =       "64",
  number =       "3",
  pages =        "221--227",
  month =        aug,
  year =         "2010",
  CODEN =        "ASTAAJ",
  DOI =          "https://doi.org/10.1198/tast.2010.09098",
  ISSN =         "0003-1305 (print), 1537-2731 (electronic)",
  ISSN-L =       "0003-1305",
  bibdate =      "Thu Aug 26 21:48:27 MDT 2010",
  bibsource =    "http://www.amstat.org/publications/tas/;
                 https://www.math.utah.edu/pub/tex/bib/amstat.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The American Statistician",
  journal-URL =  "http://www.tandfonline.com/loi/utas20",
}


bibtype: article
filename: fparith.bib
label: Alimohammad:2010:UAA
author: A. Alimohammad and S. F. Fard and B. F. Cockburn
journal: j-IEEE-TRANS-COMPUT
volume: 59
number: 4
pages: 449--456
year: 2010
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2009.169
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sun Jul 3 11:52:27 MDT 2011
bibtimestamp: 2011.07.03 11:52:27 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5313801
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Alimohammad and S. F. Fard and B. F. Cockburn
title:
A Unified Architecture for the Accurate and High-Throughput Implementation of Six Key Elementary Functions

abstract:
This paper presents a unified architecture for the compact implementation of several key elementary functions, including reciprocal, square root, and logarithm, in single-precision floating-point arithmetic. The proposed high-throughput design is based on uniform domain segmentation and curve fitting techniques. Numerically accurate least-squares regression is utilized to calculate the polynomial coefficients. The architecture is optimized by analyzing the trade-off between the size of the required memory and the precision of intermediate variables to achieve the minimum 23-bit accuracy required for single-precision floating-point representation. The efficiency of the proposed unified data path is demonstrated on a common field-programmable gate array.

rawabstract:
This paper presents a unified architecture for the compact implementation of several key elementary functions, including reciprocal, square root, and logarithm, in single-precision floating-point arithmetic. The proposed high-throughput design is based on uniform domain segmentation and curve fitting techniques. Numerically accurate least-squares regression is utilized to calculate the polynomial coefficients. The architecture is optimized by analyzing the trade-off between the size of the required memory and the precision of intermediate variables to achieve the minimum 23-bit accuracy required for single-precision floating-point representation. The efficiency of the proposed unified data path is demonstrated on a common field-programmable gate array.

rawtitle:
A Unified Architecture for the Accurate and High-Throughput Implementation of Six Key Elementary Functions

entry:
@Article{Alimohammad:2010:UAA,
  author =       "A. Alimohammad and S. F. Fard and B. F. Cockburn",
  title =        "A Unified Architecture for the Accurate and
                 High-Throughput Implementation of Six Key Elementary
                 Functions",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "59",
  number =       "4",
  pages =        "449--456",
  month =        "????",
  year =         "2010",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2009.169",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sun Jul 3 11:52:27 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5313801",
  abstract =     "This paper presents a unified architecture for the
                 compact implementation of several key elementary
                 functions, including reciprocal, square root, and
                 logarithm, in single-precision floating-point
                 arithmetic. The proposed high-throughput design is
                 based on uniform domain segmentation and curve fitting
                 techniques. Numerically accurate least-squares
                 regression is utilized to calculate the polynomial
                 coefficients. The architecture is optimized by
                 analyzing the trade-off between the size of the
                 required memory and the precision of intermediate
                 variables to achieve the minimum 23-bit accuracy
                 required for single-precision floating-point
                 representation. The efficiency of the proposed unified
                 data path is demonstrated on a common
                 field-programmable gate array.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Amin:2010:HRM
author: Alaaeldin Amin and Waleed Shinwari
title: High-Radix Multiplier-Dividers: Theory, Design, and Hardware
journal: j-IEEE-TRANS-COMPUT
volume: 59
number: 8
pages: 1009--1022
year: 2010
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2010.78
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sun Jul 3 11:52:30 MDT 2011
bibtimestamp: 2011.07.03 11:52:30 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5453337
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Alaaeldin Amin and Waleed Shinwari
rawtitle: High-Radix Multiplier-Dividers: Theory, Design, and Hardware
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib

entry:
@Article{Amin:2010:HRM,
  author =       "Alaaeldin Amin and Waleed Shinwari",
  title =        "High-Radix Multiplier-Dividers: Theory, Design, and
                 Hardware",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "59",
  number =       "8",
  pages =        "1009--1022",
  month =        "????",
  year =         "2010",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2010.78",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sun Jul 3 11:52:30 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5453337",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Banescu:2010:MFP
author: Sebastian Banescu and Florent de Dinechin and Bogdan Pasca and Radu Tudoran
title: Multipliers for floating-point double precision and beyond on FPGAs
journal: j-COMP-ARCH-NEWS
volume: 38
number: 4
pages: 73--79
month: sep
monthnumber: 9
year: 2010
CODEN: CANED2
DOI: https://doi.org/10.1145/1926367.1926380
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Thu Jan 20 14:27:03 MST 2011
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.01.20 14:27:03 MST
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J89
rawauthor: Sebastian Banescu and Florent de Dinechin and Bogdan Pasca and Radu Tudoran
rawtitle: Multipliers for floating-point double precision and beyond on {FPGAs}
abstract:
The implementation of high-precision floating-point applications on reconfigurable hardware requires large multipliers. Full multipliers are the core of floating-point multipliers. Truncated multipliers, trading resources for a well-controlled accuracy degradation, are useful building blocks in situations where a full multiplier is not needed.par This work studies the automated generation of such multipliers using the embedded multipliers and adders present in the DSP blocks of current FPGAs. The optimization of such multipliers is expressed as a tiling problem, where a tile represents a hardware multiplier, and super-tiles represent combinations of several hardware multipliers and adders, making efficient use of the DSP internal resources. This tiling technique is shown to adapt to full or truncated multipliers. It addresses arbitrary precisions including single, double but also the quadruple precision introduced by the IEEE-754-2008 standard and currently unsupported by processor hardware. An open-source implementation is provided in the FloPoCo project.

rawabstract:
The implementation of high-precision floating-point applications on reconfigurable hardware requires large multipliers. Full multipliers are the core of floating-point multipliers. Truncated multipliers, trading resources for a well-controlled accuracy degradation, are useful building blocks in situations where a full multiplier is not needed.\par This work studies the automated generation of such multipliers using the embedded multipliers and adders present in the DSP blocks of current FPGAs. The optimization of such multipliers is expressed as a tiling problem, where a tile represents a hardware multiplier, and super-tiles represent combinations of several hardware multipliers and adders, making efficient use of the DSP internal resources. This tiling technique is shown to adapt to full or truncated multipliers. It addresses arbitrary precisions including single, double but also the quadruple precision introduced by the IEEE-754-2008 standard and currently unsupported by processor hardware. An open-source implementation is provided in the FloPoCo project.

entry:
@Article{Banescu:2010:MFP,
  author =       "Sebastian Banescu and Florent de Dinechin and Bogdan
                 Pasca and Radu Tudoran",
  title =        "Multipliers for floating-point double precision and
                 beyond on {FPGAs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "38",
  number =       "4",
  pages =        "73--79",
  month =        sep,
  year =         "2010",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1926367.1926380",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Thu Jan 20 14:27:03 MST 2011",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The implementation of high-precision floating-point
                 applications on reconfigurable hardware requires large
                 multipliers. Full multipliers are the core of
                 floating-point multipliers. Truncated multipliers,
                 trading resources for a well-controlled accuracy
                 degradation, are useful building blocks in situations
                 where a full multiplier is not needed.\par

                 This work studies the automated generation of such
                 multipliers using the embedded multipliers and adders
                 present in the DSP blocks of current FPGAs. The
                 optimization of such multipliers is expressed as a
                 tiling problem, where a tile represents a hardware
                 multiplier, and super-tiles represent combinations of
                 several hardware multipliers and adders, making
                 efficient use of the DSP internal resources. This
                 tiling technique is shown to adapt to full or truncated
                 multipliers. It addresses arbitrary precisions
                 including single, double but also the quadruple
                 precision introduced by the IEEE-754-2008 standard and
                 currently unsupported by processor hardware. An
                 open-source implementation is provided in the FloPoCo
                 project.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
}


bibtype: article
filename: fparith.bib
label: Block:2010:GEB
author: Henry W. Block and Thomas H. Savits
title: A General Example for Benford Data
journal: j-AMER-STAT
volume: 64
number: 4
pages: 335--339
month: nov
monthnumber: 11
year: 2010
CODEN: ASTAAJ
DOI: https://doi.org/10.1198/tast.2010.09169
ISSN: 0003-1305 (print), 1537-2731 (electronic) OR 00031305 (print), 15372731 (electronic)
ISSNL: 0003-1305 OR 00031305
bibdate: Wed Nov 9 17:20:17 MST 2011
bibtimestamp: 2011.11.09 17:20:17 MST
fjournal: The American Statistician
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/utas20
rawauthor: Henry W. Block and Thomas H. Savits
rawtitle: A General Example for {Benford} Data
abstract:
Benford's Law deals, among other things, with the proportion of numbers whose first significant digit is a $1$ (e.g., $ 0.00131 $ and $ 19668 $ both have first significant digit $1$) in a variety of datasets. In these datasets, which arise in various compendiums or as mixtures of various sets of numbers, the proportion of numbers with first significant digit one is $ 0.3010 $ which is much higher than the commonsense value of $ 1 / 9 $. The reasons for this occurrence have been elusive. Mathematical attempts to explain this phenomenon have been relatively fruitless. Methods involving probability have been somewhat more successful. In this article we give some simple reasons for this occurrence and also give an example of a general mixture of distributions which exactly satisfies this Law. Various other examples and counterexamples are also given.

rawabstract:
Benford's Law deals, among other things, with the proportion of numbers whose first significant digit is a $1$ (e.g., $ 0.00131 $ and $ 19668 $ both have first significant digit $1$) in a variety of datasets. In these datasets, which arise in various compendiums or as mixtures of various sets of numbers, the proportion of numbers with first significant digit one is $ 0.3010 $ which is much higher than the commonsense value of $ 1 / 9 $. The reasons for this occurrence have been elusive. Mathematical attempts to explain this phenomenon have been relatively fruitless. Methods involving probability have been somewhat more successful. In this article we give some simple reasons for this occurrence and also give an example of a general mixture of distributions which exactly satisfies this Law. Various other examples and counterexamples are also given.

entry:
@Article{Block:2010:GEB,
  author =       "Henry W. Block and Thomas H. Savits",
  title =        "A General Example for {Benford} Data",
  journal =      j-AMER-STAT,
  volume =       "64",
  number =       "4",
  pages =        "335--339",
  month =        nov,
  year =         "2010",
  CODEN =        "ASTAAJ",
  DOI =          "https://doi.org/10.1198/tast.2010.09169",
  ISSN =         "0003-1305 (print), 1537-2731 (electronic)",
  ISSN-L =       "0003-1305",
  bibdate =      "Wed Nov 9 17:20:17 MST 2011",
  bibsource =    "http://www.amstat.org/publications/tas/;
                 https://www.math.utah.edu/pub/tex/bib/amstat.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Benford's Law deals, among other things, with the
                 proportion of numbers whose first significant digit is
                 a $1$ (e.g., $ 0.00131 $ and $ 19668 $ both have first
                 significant digit $1$) in a variety of datasets. In
                 these datasets, which arise in various compendiums or
                 as mixtures of various sets of numbers, the proportion
                 of numbers with first significant digit one is $ 0.3010
                 $ which is much higher than the commonsense value of $
                 1 / 9 $. The reasons for this occurrence have been
                 elusive. Mathematical attempts to explain this
                 phenomenon have been relatively fruitless. Methods
                 involving probability have been somewhat more
                 successful. In this article we give some simple reasons
                 for this occurrence and also give an example of a
                 general mixture of distributions which exactly
                 satisfies this Law. Various other examples and
                 counterexamples are also given.",
  acknowledgement = ack-nhfb,
  fjournal =     "The American Statistician",
  journal-URL =  "http://www.tandfonline.com/loi/utas20",
}


bibtype: article
filename: fparith.bib
label: Brent:2010:PAV
author: Richard P. Brent
title: On the precision attainable with various floating-point number systems
journal: arXiv.org
pages: ??--??
day: 20
month: apr
monthnumber: 4
year: 2010
MRclass: 65Y04
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1004.3374
remark: Published in IEEE Transactions on Computers bf C-22 (1973), 601--607.
subject: Numerical Analysis (cs.NA); Numerical Analysis (math.NA)
acknowledgement: ack-nhfb
rawauthor: Richard P. Brent
rawtitle: On the precision attainable with various floating-point number systems
abstract:
For scientific computations on a digital computer the set of real number is usually approximated by a finite set $F$ of ``floating-point'' numbers. We compare the numerical accuracy possible with difference choices of $F$ having approximately the same range and requiring the same word length. In particular, we compare different choices of base (or radix) in the usual floating-point systems. The emphasis is on the choice of $F$, not on the details of the number representation or the arithmetic, but both rounded and truncated arithmetic are considered. Theoretical results are given, and some simulations of typical floating-point computations (forming sums, solving systems of linear equations, finding eigenvalues) are described. If the leading fraction bit of a normalized base 2 number is not stored explicitly (saving a bit), and the criterion is to minimize the mean square roundoff error, then base 2 is best. If unnormalized numbers are allowed, so the first bit must be stored explicitly, then base 4 (or sometimes base 8) is the best of the usual systems.

rawabstract:
For scientific computations on a digital computer the set of real number is usually approximated by a finite set $F$ of ``floating-point'' numbers. We compare the numerical accuracy possible with difference choices of $F$ having approximately the same range and requiring the same word length. In particular, we compare different choices of base (or radix) in the usual floating-point systems. The emphasis is on the choice of $F$, not on the details of the number representation or the arithmetic, but both rounded and truncated arithmetic are considered. Theoretical results are given, and some simulations of typical floating-point computations (forming sums, solving systems of linear equations, finding eigenvalues) are described. If the leading fraction bit of a normalized base 2 number is not stored explicitly (saving a bit), and the criterion is to minimize the mean square roundoff error, then base 2 is best. If unnormalized numbers are allowed, so the first bit must be stored explicitly, then base 4 (or sometimes base 8) is the best of the usual systems.

entry:
@Article{Brent:2010:PAV,
  author =       "Richard P. Brent",
  title =        "On the precision attainable with various
                 floating-point number systems",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "20",
  month =        apr,
  year =         "2010",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  MRclass =      "65Y04",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1004.3374",
  abstract =     "For scientific computations on a digital computer the
                 set of real number is usually approximated by a finite
                 set $F$ of ``floating-point'' numbers. We compare the
                 numerical accuracy possible with difference choices of
                 $F$ having approximately the same range and requiring
                 the same word length. In particular, we compare
                 different choices of base (or radix) in the usual
                 floating-point systems. The emphasis is on the choice
                 of $F$, not on the details of the number representation
                 or the arithmetic, but both rounded and truncated
                 arithmetic are considered. Theoretical results are
                 given, and some simulations of typical floating-point
                 computations (forming sums, solving systems of linear
                 equations, finding eigenvalues) are described. If the
                 leading fraction bit of a normalized base 2 number is
                 not stored explicitly (saving a bit), and the criterion
                 is to minimize the mean square roundoff error, then
                 base 2 is best. If unnormalized numbers are allowed, so
                 the first bit must be stored explicitly, then base 4
                 (or sometimes base 8) is the best of the usual
                 systems.",
  acknowledgement = ack-nhfb,
  remark =       "Published in IEEE Transactions on Computers {\bf C-22}
                 (1973), 601--607.",
  subject =      "Numerical Analysis (cs.NA); Numerical Analysis
                 (math.NA)",
}


bibtype: inproceedings
filename: fparith.bib
label: Brisebarre:2010:IDF
editor: Francois Charot and Frank Hannig and Jurgen Teich and Christophe Wolinski
title: Implementing decimal floating-point arithmetic through binary: Some suggestions
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 317--320
year: 2010
DOI: https://doi.org/10.1109/ASAP.2010.5540969
ISBN: 1-4244-6967-8 OR 1424469678
ISBN13: 978-1-4244-6967-3 OR 9781424469673
ISSN: 1063-6862 OR 10636862
ISSNL: 1063-6862 OR 10636862
bibdate: Fri Sep 29 10:41:24 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 10:41:24 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
raweditor: Fran{\c{c}}ois Charot and Frank Hannig and J{\"u}rgen Teich and Christophe Wolinski
rawtitle: Implementing decimal floating-point arithmetic through binary: Some suggestions
author:
Nicolas Brisebarre and Nicolas Louvet and Erik Martin-Dorel and Jean-Michel Muller and Adrien Panhaleux and Milo D. Ercegovac

booktitle:
ASAP 2010 --- 21st IEEE International Conference on Application-specific Systems, Architectures and Processors. July 7--9, 2010. Rennes, France

rawauthor:
Nicolas Brisebarre and Nicolas Louvet and {\'E}rik Martin-Dorel and Jean-Michel Muller and Adrien Panhaleux and Milo D. Ercegovac

rawbooktitle:
{ASAP 2010 --- 21st IEEE International Conference on Application-specific Systems, Architectures and Processors. July 7--9, 2010. Rennes, France}

entry:
@InProceedings{Brisebarre:2010:IDF,
  author =       "Nicolas Brisebarre and Nicolas Louvet and {\'E}rik
                 Martin-Dorel and Jean-Michel Muller and Adrien
                 Panhaleux and Milo D. Ercegovac",
  editor =       "Fran{\c{c}}ois Charot and Frank Hannig and J{\"u}rgen
                 Teich and Christophe Wolinski",
  booktitle =    "{ASAP 2010 --- 21st IEEE International Conference on
                 Application-specific Systems, Architectures and
                 Processors. July 7--9, 2010. Rennes, France}",
  title =        "Implementing decimal floating-point arithmetic through
                 binary: Some suggestions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "317--320",
  year =         "2010",
  DOI =          "https://doi.org/10.1109/ASAP.2010.5540969",
  ISBN =         "1-4244-6967-8",
  ISBN-13 =      "978-1-4244-6967-3",
  ISSN =         "1063-6862",
  ISSN-L =       "1063-6862",
  bibdate =      "Fri Sep 29 10:41:24 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Chapoutot:2010:ISN
author: Alexandre Chapoutot
title: Interval Slopes as Numerical Abstract Domain for Floating-Point Variables
journal: arXiv.org
pages: ??--??
day: 1
month: apr
monthnumber: 4
year: 2010
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1004.0202
subject: Programming Languages (cs.PL); Numerical Analysis (cs.NA)
acknowledgement: ack-nhfb
rawauthor: Alexandre Chapoutot
rawtitle: Interval Slopes as Numerical Abstract Domain for Floating-Point Variables
abstract:
The design of embedded control systems is mainly done with model-based tools such as Matlab/Simulink. Numerical simulation is the central technique of development and verification of such tools. Floating-point arithmetic, that is well-known to only provide approximated results, is omnipresent in this activity. In order to validate the behaviors of numerical simulations using abstract interpretation-based static analysis, we present, theoretically and with experiments, a new partially relational abstract domain dedicated to floating-point variables. It comes from interval expansion of non-linear functions using slopes and it is able to mimic all the behaviors of the floating-point arithmetic. Hence it is adapted to prove the absence of run-time errors or to analyze the numerical precision of embedded control systems.

rawabstract:
The design of embedded control systems is mainly done with model-based tools such as Matlab/Simulink. Numerical simulation is the central technique of development and verification of such tools. Floating-point arithmetic, that is well-known to only provide approximated results, is omnipresent in this activity. In order to validate the behaviors of numerical simulations using abstract interpretation-based static analysis, we present, theoretically and with experiments, a new partially relational abstract domain dedicated to floating-point variables. It comes from interval expansion of non-linear functions using slopes and it is able to mimic all the behaviors of the floating-point arithmetic. Hence it is adapted to prove the absence of run-time errors or to analyze the numerical precision of embedded control systems.

entry:
@Article{Chapoutot:2010:ISN,
  author =       "Alexandre Chapoutot",
  title =        "Interval Slopes as Numerical Abstract Domain for
                 Floating-Point Variables",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "1",
  month =        apr,
  year =         "2010",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1004.0202",
  abstract =     "The design of embedded control systems is mainly done
                 with model-based tools such as Matlab/Simulink.
                 Numerical simulation is the central technique of
                 development and verification of such tools.
                 Floating-point arithmetic, that is well-known to only
                 provide approximated results, is omnipresent in this
                 activity. In order to validate the behaviors of
                 numerical simulations using abstract
                 interpretation-based static analysis, we present,
                 theoretically and with experiments, a new partially
                 relational abstract domain dedicated to floating-point
                 variables. It comes from interval expansion of
                 non-linear functions using slopes and it is able to
                 mimic all the behaviors of the floating-point
                 arithmetic. Hence it is adapted to prove the absence of
                 run-time errors or to analyze the numerical precision
                 of embedded control systems.",
  acknowledgement = ack-nhfb,
  subject =      "Programming Languages (cs.PL); Numerical Analysis
                 (cs.NA)",
}


bibtype: article
filename: fparith.bib
label: Cheng:2010:BSS
author: Qi Cheng and Xianmeng Meng and Celi Sun and Jiazhe Chen
title: Bounding the sum of square roots via lattice reduction
journal: j-MATH-COMPUT
volume: 79
number: 270
pages: 1109--1122
month: apr
monthnumber: 4
year: 2010
CODEN: MCMPAF
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Fri May 14 06:21:06 MDT 2010
bibtimestamp: 2010.05.14 06:21:06 MDT
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Qi Cheng and Xianmeng Meng and Celi Sun and Jiazhe Chen
rawtitle: Bounding the sum of square roots via lattice reduction
bibsource:
http://www.ams.org/mcom/2010-79-270; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib

URL:
http://www.ams.org/journals/mcom/2010-79-270/S0025-5718-09-02304-7/home.html; http://www.ams.org/journals/mcom/2010-79-270/S0025-5718-09-02304-7/S0025-5718-09-02304-7.pdf

entry:
@Article{Cheng:2010:BSS,
  author =       "Qi Cheng and Xianmeng Meng and Celi Sun and Jiazhe
                 Chen",
  title =        "Bounding the sum of square roots via lattice
                 reduction",
  journal =      j-MATH-COMPUT,
  volume =       "79",
  number =       "270",
  pages =        "1109--1122",
  month =        apr,
  year =         "2010",
  CODEN =        "MCMPAF",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Fri May 14 06:21:06 MDT 2010",
  bibsource =    "http://www.ams.org/mcom/2010-79-270;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib",
  URL =          "http://www.ams.org/journals/mcom/2010-79-270/S0025-5718-09-02304-7/home.html;
                 http://www.ams.org/journals/mcom/2010-79-270/S0025-5718-09-02304-7/S0025-5718-09-02304-7.pdf",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
}


bibtype: inproceedings
filename: fparith.bib
label: Chevillard:2010:SED
author: Sylvain Chevillard and Mioara Jolde and Christoph Lauter
title: Sollya: An Environment for the Development of Numerical Codes
crossref: Fukuda:2010:MSI
pages: 28--31
year: 2010
DOI: https://doi.org/10.1007/978-3-642-15582-6_5
bibdate: Sat Sep 23 06:20:46 2023
bibtimestamp: 2023.09.23 06:20:46 ???
URL: http://link.springer.com/content/pdf/10.1007/978-3-642-15582-6_5.pdf
acknowledgement: ack-nhfb
rawauthor: Sylvain Chevillard and Mioara Jolde and Christoph Lauter
rawtitle: {Sollya}: An Environment for the Development of Numerical Codes
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2010a.bib

entry:
@InProceedings{Chevillard:2010:SED,
  author =       "Sylvain Chevillard and Mioara Jolde and Christoph
                 Lauter",
  title =        "{Sollya}: An Environment for the Development of
                 Numerical Codes",
  crossref =     "Fukuda:2010:MSI",
  pages =        "28--31",
  year =         "2010",
  DOI =          "https://doi.org/10.1007/978-3-642-15582-6_5",
  bibdate =      "Sat Sep 23 06:20:46 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2010a.bib",
  URL =          "http://link.springer.com/content/pdf/10.1007/978-3-642-15582-6_5.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Cuyt:2010:VSF
author: Annie Cuyt and Franky Backeljauw and Stefan Becuwe and Joris Van Deun
title: Validated Special Functions Software
crossref: Fukuda:2010:MSI
pages: 32--34
year: 2010
DOI: https://doi.org/10.1007/978-3-642-15582-6_6
bibdate: Sat Sep 23 06:20:46 2023
bibtimestamp: 2023.09.23 06:20:46 ???
acknowledgement: ack-nhfb
rawauthor: Annie Cuyt and Franky Backeljauw and Stefan Becuwe and Joris {Van Deun}
rawtitle: Validated Special Functions Software
entry:
@InProceedings{Cuyt:2010:VSF,
  author =       "Annie Cuyt and Franky Backeljauw and Stefan Becuwe and
                 Joris {Van Deun}",
  title =        "Validated Special Functions Software",
  crossref =     "Fukuda:2010:MSI",
  pages =        "32--34",
  year =         "2010",
  DOI =          "https://doi.org/10.1007/978-3-642-15582-6_6",
  bibdate =      "Sat Sep 23 06:20:46 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Daumas:2010:CBE
author: Marc Daumas and Guillaume Melquiond
title: Certification of bounds on expressions involving rounded operators
journal: j-TOMS
volume: 37
number: 1
pages: 2:1--2:20
month: jan
monthnumber: 1
year: 2010
CODEN: ACMSCU
DOI: https://doi.org/10.1145/1644001.1644003
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Mon Mar 15 10:45:33 MDT 2010
bibsource: http://www.acm.org/pubs/contents/journals/toms/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.03.15 10:45:33 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 2
journalURL: https://dl.acm.org/loi/toms
rawauthor: Marc Daumas and Guillaume Melquiond
rawtitle: Certification of bounds on expressions involving rounded operators
abstract:
Gappa is a tool designed to formally verify the correctness of numerical software and hardware. It uses interval arithmetic and forward error analysis to bound mathematical expressions that involve rounded as well as exact operators. It then generates a theorem and its proof for each verified enclosure. This proof can be automatically checked with a proof assistant, such as Coq or HOL Light. It relies on a large companion library of facts that we have developed. This Coq library provides theorems dealing with addition, multiplication, division, and square root, for both fixed- and floating-point arithmetics. Gappa uses multiple-precision dyadic fractions for the endpoints of intervals and performs forward error analysis on rounded operators when necessary. When asked, Gappa reports the best bounds it is able to reach for a given expression in a given context. This feature can be used to identify where the set of facts and automatic techniques implemented in Gappa becomes insufficient. Gappa handles seamlessly additional properties expressed as interval properties or rewriting rules in order to establish more intricate bounds. Recent work showed that Gappa is suited to discharge proof obligations generated for small pieces of software. They may be produced by third-party tools and the first applications of Gappa use proof obligations written by designers or obtained from traces of execution.

keywords:
Coq; correct rounding; dyadic fraction; floating-point arithmetic; Forward error analysis; HOL Light; interval arithmetic; proof obligation; proof system; PVS

rawabstract:
Gappa is a tool designed to formally verify the correctness of numerical software and hardware. It uses interval arithmetic and forward error analysis to bound mathematical expressions that involve rounded as well as exact operators. It then generates a theorem and its proof for each verified enclosure. This proof can be automatically checked with a proof assistant, such as Coq or HOL Light. It relies on a large companion library of facts that we have developed. This Coq library provides theorems dealing with addition, multiplication, division, and square root, for both fixed- and floating-point arithmetics. Gappa uses multiple-precision dyadic fractions for the endpoints of intervals and performs forward error analysis on rounded operators when necessary. When asked, Gappa reports the best bounds it is able to reach for a given expression in a given context. This feature can be used to identify where the set of facts and automatic techniques implemented in Gappa becomes insufficient. Gappa handles seamlessly additional properties expressed as interval properties or rewriting rules in order to establish more intricate bounds. Recent work showed that Gappa is suited to discharge proof obligations generated for small pieces of software. They may be produced by third-party tools and the first applications of Gappa use proof obligations written by designers or obtained from traces of execution.

entry:
@Article{Daumas:2010:CBE,
  author =       "Marc Daumas and Guillaume Melquiond",
  title =        "Certification of bounds on expressions involving
                 rounded operators",
  journal =      j-TOMS,
  volume =       "37",
  number =       "1",
  pages =        "2:1--2:20",
  month =        jan,
  year =         "2010",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/1644001.1644003",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Mon Mar 15 10:45:33 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Gappa is a tool designed to formally verify the
                 correctness of numerical software and hardware. It uses
                 interval arithmetic and forward error analysis to bound
                 mathematical expressions that involve rounded as well
                 as exact operators. It then generates a theorem and its
                 proof for each verified enclosure. This proof can be
                 automatically checked with a proof assistant, such as
                 Coq or HOL Light. It relies on a large companion
                 library of facts that we have developed. This Coq
                 library provides theorems dealing with addition,
                 multiplication, division, and square root, for both
                 fixed- and floating-point arithmetics. Gappa uses
                 multiple-precision dyadic fractions for the endpoints
                 of intervals and performs forward error analysis on
                 rounded operators when necessary. When asked, Gappa
                 reports the best bounds it is able to reach for a given
                 expression in a given context. This feature can be used
                 to identify where the set of facts and automatic
                 techniques implemented in Gappa becomes insufficient.
                 Gappa handles seamlessly additional properties
                 expressed as interval properties or rewriting rules in
                 order to establish more intricate bounds. Recent work
                 showed that Gappa is suited to discharge proof
                 obligations generated for small pieces of software.
                 They may be produced by third-party tools and the first
                 applications of Gappa use proof obligations written by
                 designers or obtained from traces of execution.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "Coq; correct rounding; dyadic fraction; floating-point
                 arithmetic; Forward error analysis; HOL Light; interval
                 arithmetic; proof obligation; proof system; PVS",
}


bibtype: misc
filename: fparith.bib
label: deDinechin:2010:FGA
author: Florent de Dinechin and Bogdan Pasca
pages: 2:1--2:20
day: 10
month: aug
monthnumber: 8
year: 2010
bibdate: Sat Oct 9 14:27:50 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 14:27:50 ???
acknowledgement: ack-nhfb
howpublished: Web site and source code.
rawauthor: Florent de Dinechin and Bogdan Pasca
title:
FloPoCo: generator of arithmetic cores (Floating-Point Cores, but not only) for FPGAs (but not only)

abstract:
The purpose of the FloPoCo project is to explore the many ways in which the flexibility of the FPGA target can be exploited in the arithmetic realm, with a focus on floating-point.par The philosophy of FloPoCo is that floating-point on FPGAs should not rely on operators that mimick those available in processors. By designing radically new operators, one may obtain more accurate results with less hardware in less time. This thesis is detailed in this document.par Therefore FloPoCo focuses on exotic operators and exotic precisions. However it also provides basic operators (+,-,*,/ and square root) whose performance matches vendor-supplied operators while offering more flexibility.par FloPoCo is not a library of operators, but a generator of operators written in C++. It inputs operator specifications, and outputs synthesizable VHDL. This approach allows much better optimization and customization than what VHDL alone permits. In addition, FloPoCo is to our knowledge the easiest way to design complex operators with flexible pipeline.par FloPoCo supersedes FPLibrary, and is compatible with it.

rawabstract:
The purpose of the FloPoCo project is to explore the many ways in which the flexibility of the FPGA target can be exploited in the arithmetic realm, with a focus on floating-point.\par The philosophy of FloPoCo is that floating-point on FPGAs should not rely on operators that mimick those available in processors. By designing radically new operators, one may obtain more accurate results with less hardware in less time. This thesis is detailed in this document.\par Therefore FloPoCo focuses on exotic operators and exotic precisions. However it also provides basic operators (+,-,*,/ and square root) whose performance matches vendor-supplied operators while offering more flexibility.\par FloPoCo is not a library of operators, but a generator of operators written in C++. It inputs operator specifications, and outputs synthesizable VHDL. This approach allows much better optimization and customization than what VHDL alone permits. In addition, FloPoCo is to our knowledge the easiest way to design complex operators with flexible pipeline.\par FloPoCo supersedes FPLibrary, and is compatible with it.

rawtitle:
{FloPoCo}: generator of arithmetic cores ({Floating-Point Cores}, but not only) for {FPGAs} (but not only)

entry:
@Misc{deDinechin:2010:FGA,
  author =       "Florent de Dinechin and Bogdan Pasca",
  title =        "{FloPoCo}: generator of arithmetic cores
                 ({Floating-Point Cores}, but not only) for {FPGAs} (but
                 not only)",
  howpublished = "Web site and source code.",
  day =          "10",
  month =        aug,
  year =         "2010",
  bibdate =      "Sat Oct 9 14:27:50 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The purpose of the FloPoCo project is to explore the
                 many ways in which the flexibility of the FPGA target
                 can be exploited in the arithmetic realm, with a focus
                 on floating-point.\par

                 The philosophy of FloPoCo is that floating-point on
                 FPGAs should not rely on operators that mimick those
                 available in processors. By designing radically new
                 operators, one may obtain more accurate results with
                 less hardware in less time. This thesis is detailed in
                 this document.\par

                 Therefore FloPoCo focuses on exotic operators and
                 exotic precisions. However it also provides basic
                 operators (+,-,*,/ and square root) whose performance
                 matches vendor-supplied operators while offering more
                 flexibility.\par

                 FloPoCo is not a library of operators, but a generator
                 of operators written in C++. It inputs operator
                 specifications, and outputs synthesizable VHDL. This
                 approach allows much better optimization and
                 customization than what VHDL alone permits. In
                 addition, FloPoCo is to our knowledge the easiest way
                 to design complex operators with flexible
                 pipeline.\par

                 FloPoCo supersedes FPLibrary, and is compatible with
                 it.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: deDinechin:2010:FPE
author: Florent de Dinechin and Bogdan Pasca
editor: Jinian Bian and Qiang Zhou and Kang Zhao
title: Floating-point exponential functions for DSP-enabled FPGAs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 110--117
month: dec
monthnumber: 12
year: 2010
DOI: https://doi.org/10.1109/FPT.2010.5681764
bibdate: Sat Feb 08 09:35:06 2020
bibtimestamp: 2020.02.08 09:35:06 ???
acknowledgement: ack-nhfb
rawauthor: Florent de Dinechin and Bogdan Pasca
raweditor: Jinian Bian and Qiang Zhou and Kang Zhao
rawtitle: Floating-point exponential functions for {DSP}-enabled {FPGAs}
booktitle:
Proceedings 2010 International Conference on Field-Programmable Technology, 8--10 December 2010, Beijing, China

rawbooktitle:
{Proceedings 2010 International Conference on Field-Programmable Technology, 8--10 December 2010, Beijing, China}

entry:
@InProceedings{deDinechin:2010:FPE,
  author =       "Florent de Dinechin and Bogdan Pasca",
  editor =       "Jinian Bian and Qiang Zhou and Kang Zhao",
  booktitle =    "{Proceedings 2010 International Conference on
                 Field-Programmable Technology, 8--10 December 2010,
                 Beijing, China}",
  title =        "Floating-point exponential functions for {DSP}-enabled
                 {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "110--117",
  month =        dec,
  year =         "2010",
  DOI =          "https://doi.org/10.1109/FPT.2010.5681764",
  bibdate =      "Sat Feb 08 09:35:06 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Digeser:2010:ISE
author: P. Digeser and M. Tubolino and M. Klemm and D. Shapiro and M. Bolic
title: Instruction set extension in the NIOS II: a floating point divider for complex numbers
crossref: IEEE:2010:CCE
pages: 110--117
year: 2010
DOI: https://doi.org/10.1109/CCECE.2010.5575173
bibdate: Fri Dec 03 15:43:03 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.12.03 15:43:03 ???
acknowledgement: ack-nhfb
rawauthor: P. Digeser and M. Tubolino and M. Klemm and D. Shapiro and M. Bolic
rawtitle: Instruction set extension in the {NIOS II}: a floating point divider for complex numbers
abstract:
As increasing the clock frequency leads to unmanageable heat and power dissipation the search is on for another way to get more power efficient and faster embedded systems. Given that chip area is also a constraint, we investigate the addition of a custom instruction to the processor instruction set which enables the execution of an efficient complex division. The instruction we designed is a hardware divider for complex numbers which receives four input values and returns two output values. The data bandwidth constraint of 2 inputs and 1 output is loosened by making the instruction multicycle as described in previous work. We uses the custom instruction interface of the NIOS II soft processor and achieve a speedup of up to $ 3 tines $ over the unmodified instruction set.

keywords:
clock frequency; complex numbers; custom instruction; embedded systems; floating point arithmetic; floating point divider; instruction multicycle; instruction set extension; instruction sets; microprocessor chips; NIOS II soft processor; processor instruction set

rawabstract:
As increasing the clock frequency leads to unmanageable heat and power dissipation the search is on for another way to get more power efficient and faster embedded systems. Given that chip area is also a constraint, we investigate the addition of a custom instruction to the processor instruction set which enables the execution of an efficient complex division. The instruction we designed is a hardware divider for complex numbers which receives four input values and returns two output values. The data bandwidth constraint of 2 inputs and 1 output is loosened by making the instruction multicycle as described in previous work. We uses the custom instruction interface of the NIOS II soft processor and achieve a speedup of up to $ 3 \tines $ over the unmodified instruction set.

entry:
@InProceedings{Digeser:2010:ISE,
  author =       "P. Digeser and M. Tubolino and M. Klemm and D. Shapiro
                 and M. Bolic",
  title =        "Instruction set extension in the {NIOS II}: a floating
                 point divider for complex numbers",
  crossref =     "IEEE:2010:CCE",
  year =         "2010",
  DOI =          "https://doi.org/10.1109/CCECE.2010.5575173",
  bibdate =      "Fri Dec 03 15:43:03 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "As increasing the clock frequency leads to
                 unmanageable heat and power dissipation the search is
                 on for another way to get more power efficient and
                 faster embedded systems. Given that chip area is also a
                 constraint, we investigate the addition of a custom
                 instruction to the processor instruction set which
                 enables the execution of an efficient complex division.
                 The instruction we designed is a hardware divider for
                 complex numbers which receives four input values and
                 returns two output values. The data bandwidth
                 constraint of 2 inputs and 1 output is loosened by
                 making the instruction multicycle as described in
                 previous work. We uses the custom instruction interface
                 of the NIOS II soft processor and achieve a speedup of
                 up to $ 3 \tines $ over the unmodified instruction
                 set.",
  acknowledgement = ack-nhfb,
  keywords =     "clock frequency; complex numbers; custom instruction;
                 embedded systems; floating point arithmetic; floating
                 point divider; instruction multicycle; instruction set
                 extension; instruction sets; microprocessor chips; NIOS
                 II soft processor; processor instruction set",
}


bibtype: article
filename: fparith.bib
label: Dvir:2010:HRT
author: Zeev Dvir and Amir Shpilka and Amir Yehudayoff
title: Hardness-Randomness Tradeoffs for Bounded Depth Arithmetic Circuits
journal: j-SIAM-J-COMPUT
volume: 39
number: 4
pages: 1279--1293
year: 2010
CODEN: SMJCAT
ISSN: 0097-5397 (print), 1095-7111 (electronic) OR 00975397 (print), 10957111 (electronic)
ISSNL: 0097-5397 OR 00975397
bibdate: Tue May 18 08:22:14 MDT 2010
bibtimestamp: 2010.05.18 08:22:14 MDT
fjournal: SIAM Journal on Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sicomp
rawauthor: Zeev Dvir and Amir Shpilka and Amir Yehudayoff
rawtitle: Hardness-Randomness Tradeoffs for Bounded Depth Arithmetic Circuits
bibsource:
http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/39/4; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Dvir:2010:HRT,
  author =       "Zeev Dvir and Amir Shpilka and Amir Yehudayoff",
  title =        "Hardness-Randomness Tradeoffs for Bounded Depth
                 Arithmetic Circuits",
  journal =      j-SIAM-J-COMPUT,
  volume =       "39",
  number =       "4",
  pages =        "1279--1293",
  month =        "????",
  year =         "2010",
  CODEN =        "SMJCAT",
  DOI =          "",
  ISSN =         "0097-5397 (print), 1095-7111 (electronic)",
  ISSN-L =       "0097-5397",
  bibdate =      "Tue May 18 08:22:14 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/39/4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Computing",
  journal-URL =  "http://epubs.siam.org/sicomp",
}


bibtype: article
filename: fparith.bib
label: Emmart:2010:HPI
author: Niall Emmart and Charles Weems
title: High Precision Integer Addition, Subtraction and Multiplication with a Graphics Processing Unit
journal: j-PARALLEL-PROCESS-LETT
volume: 20
number: 4
pages: 293--306
month: dec
monthnumber: 12
year: 2010
CODEN: PPLTEE
DOI: https://doi.org/10.1142/S0129626410000259
ISSN: 0129-6264 (print), 1793-642X (electronic) OR 01296264 (print), 1793642X (electronic)
bibdate: Tue Feb 28 11:32:05 MST 2012
bibtimestamp: 2012.02.28 11:32:05 MST
note: See later improvements cite Emmart:2011:HPI.
fjournal: Parallel Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.worldscientific.com/loi/ppl
rawauthor: Niall Emmart and Charles Weems
rawnote: See later improvements \cite{Emmart:2011:HPI}.
rawtitle: High Precision Integer Addition, Subtraction and Multiplication with a Graphics Processing Unit
bibsource:
http://ejournals.wspc.com.sg/ppl/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/parallelprocesslett.bib

keywords:
GNU GMP multiple precision package; graphics processing unit; Karatsuba multiplication algorithm; multiple precision arithmetic; parallel algorithm; Strassen FFT multiplication algorithm

remark:
The abstract reports improvements (GPU compared to GMP) of 3x for multiplication, and 8x for addition and subtraction, with very long operands (32KB or greater).

entry:
@Article{Emmart:2010:HPI,
  author =       "Niall Emmart and Charles Weems",
  title =        "High Precision Integer Addition, Subtraction and
                 Multiplication with a Graphics Processing Unit",
  journal =      j-PARALLEL-PROCESS-LETT,
  volume =       "20",
  number =       "4",
  pages =        "293--306",
  month =        dec,
  year =         "2010",
  CODEN =        "PPLTEE",
  DOI =          "https://doi.org/10.1142/S0129626410000259",
  ISSN =         "0129-6264 (print), 1793-642X (electronic)",
  bibdate =      "Tue Feb 28 11:32:05 MST 2012",
  bibsource =    "http://ejournals.wspc.com.sg/ppl/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/parallelprocesslett.bib",
  note =         "See later improvements \cite{Emmart:2011:HPI}.",
  acknowledgement = ack-nhfb,
  fjournal =     "Parallel Processing Letters",
  journal-URL =  "http://www.worldscientific.com/loi/ppl",
  keywords =     "GNU GMP multiple precision package; graphics
                 processing unit; Karatsuba multiplication algorithm;
                 multiple precision arithmetic; parallel algorithm;
                 Strassen FFT multiplication algorithm",
  remark =       "The abstract reports improvements (GPU compared to
                 GMP) of 3x for multiplication, and 8x for addition and
                 subtraction, with very long operands (32KB or
                 greater).",
}


bibtype: inproceedings
filename: fparith.bib
label: Fahmy:2010:DFP
author: H. A. H. Fahmy and T. ElDeeb and M. Y. Hassan and Y. Farouk and R. R. Eissa
title: Decimal floating point for future processors
crossref: IEEE:2010:ICM
pages: 443--446
year: 2010
DOI: https://doi.org/10.1109/ICM.2010.5696183
bibdate: Thu Feb 17 08:30:56 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.17 08:30:56 ???
acknowledgement: ack-nhfb
rawauthor: H. A. H. Fahmy and T. ElDeeb and M. Y. Hassan and Y. Farouk and R. R. Eissa
rawtitle: Decimal floating point for future processors
abstract:
Many new designs for Decimal Floating Point (DFP) hardware units have been proposed in the last few years. To date, only the IBM POWER6 and POWER7 processors include internal units for decimal floating point processing. We have designed and tested several DFP units including an adder, multiplier, divider, square root, and fused multiply-add compliant with the IEEE 754-2008 standard. This paper presents the results of using our units as part of a vector co-processor and the anticipated gains once the units are moved on chip with the main processor.

rawabstract:
Many new designs for Decimal Floating Point (DFP) hardware units have been proposed in the last few years. To date, only the IBM POWER6 and POWER7 processors include internal units for decimal floating point processing. We have designed and tested several DFP units including an adder, multiplier, divider, square root, and fused multiply-add compliant with the IEEE 754-2008 standard. This paper presents the results of using our units as part of a vector co-processor and the anticipated gains once the units are moved on chip with the main processor.

entry:
@InProceedings{Fahmy:2010:DFP,
  author =       "H. A. H. Fahmy and T. ElDeeb and M. Y. Hassan and Y.
                 Farouk and R. R. Eissa",
  title =        "Decimal floating point for future processors",
  crossref =     "IEEE:2010:ICM",
  pages =        "443--446",
  year =         "2010",
  DOI =          "https://doi.org/10.1109/ICM.2010.5696183",
  bibdate =      "Thu Feb 17 08:30:56 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Many new designs for Decimal Floating Point (DFP)
                 hardware units have been proposed in the last few
                 years. To date, only the IBM POWER6 and POWER7
                 processors include internal units for decimal floating
                 point processing. We have designed and tested several
                 DFP units including an adder, multiplier, divider,
                 square root, and fused multiply-add compliant with the
                 IEEE 754-2008 standard. This paper presents the results
                 of using our units as part of a vector co-processor and
                 the anticipated gains once the units are moved on chip
                 with the main processor.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Fiedler:2010:GGF
author: Glenn Fiedler
title: Gaffer on Games --- Floating Point Determinism
pages: 443--446
day: 24
month: feb
monthnumber: 2
year: 2010
bibdate: Mon Dec 04 07:07:25 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.04 07:07:25 ???
remark: See also cite Dickinson:2001:IRB.
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Glenn Fiedler
rawtitle: Gaffer on Games --- Floating Point Determinism
note:
Comments on the problem of reproducing game behavior on different platforms because of floating-point issues.

rawnote:
Comments on the problem of reproducing game behavior on different platforms because of floating-point issues.

entry:
@Misc{Fiedler:2010:GGF,
  author =       "Glenn Fiedler",
  title =        "Gaffer on Games --- Floating Point Determinism",
  howpublished = "Web site",
  day =          "24",
  month =        feb,
  year =         "2010",
  bibdate =      "Mon Dec 04 07:07:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Comments on the problem of reproducing game behavior
                 on different platforms because of floating-point
                 issues.",
  acknowledgement = ack-nhfb,
  remark =       "See also \cite{Dickinson:2001:IRB}.",
}


bibtype: article
filename: fparith.bib
label: Frey:2010:ABC
author: Gerhard Frey
title: The Arithmetic Behind Cryptography
journal: j-NAMS
volume: 57
number: 3
pages: 366--374
month: mar
monthnumber: 3
year: 2010
CODEN: AMNOAN
ISSN: 0002-9920 (print), 1088-9477 (electronic) OR 00029920 (print), 10889477 (electronic)
ISSNL: 0002-9920 OR 00029920
bibdate: Mon Feb 22 15:35:29 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.02.22 15:35:29 ???
URL: http://www.ams.org/notices/201003/
fjournal: Notices of the American Mathematical Society
acknowledgement: ack-nhfb
ajournal: Notices Amer. Math. Soc.
journalURL: http://www.ams.org/notices/
rawauthor: Gerhard Frey
rawtitle: The Arithmetic Behind Cryptography
entry:
@Article{Frey:2010:ABC,
  author =       "Gerhard Frey",
  title =        "The Arithmetic Behind Cryptography",
  journal =      j-NAMS,
  volume =       "57",
  number =       "3",
  pages =        "366--374",
  month =        mar,
  year =         "2010",
  CODEN =        "AMNOAN",
  ISSN =         "0002-9920 (print), 1088-9477 (electronic)",
  ISSN-L =       "0002-9920",
  bibdate =      "Mon Feb 22 15:35:29 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.ams.org/notices/201003/",
  acknowledgement = ack-nhfb,
  ajournal =     "Notices Amer. Math. Soc.",
  fjournal =     "Notices of the American Mathematical Society",
  journal-URL =  "http://www.ams.org/notices/",
}


bibtype: article
filename: fparith.bib
label: Fu:2010:FDO
author: Haohuan Fu and O. Mencer and W. Luk
title: FPGA Designs with Optimized Logarithmic Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 59
number: 7
pages: 1000--1006
year: 2010
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2010.51
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sun Jul 3 12:14:07 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.07.03 12:14:07 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5416693
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Haohuan Fu and O. Mencer and W. Luk
rawtitle: {FPGA} Designs with Optimized Logarithmic Arithmetic
entry:
@Article{Fu:2010:FDO,
  author =       "Haohuan Fu and O. Mencer and W. Luk",
  title =        "{FPGA} Designs with Optimized Logarithmic Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "59",
  number =       "7",
  pages =        "1000--1006",
  month =        "????",
  year =         "2010",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2010.51",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sun Jul 3 12:14:07 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5416693",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Ghazi:2010:WHU
author: Kaveh R. Ghazi and Vincent Lefevre and Philippe Theveny and Paul Zimmermann
title: Why and How to Use Arbitrary Precision
journal: j-COMPUT-SCI-ENG
volume: 12
number: 3
pages: 5
month: may
monthnumber: 5
year: 2010
CODEN: CSENFA
DOI: https://doi.org/10.1109/MCSE.2010.73
ISSN: 0740-7475 (print), 1558-1918 (electronic) OR 07407475 (print), 15581918 (electronic)
ISSNL: 1521-9615 OR 15219615
bibdate: Thu May 13 11:08:14 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.13 11:08:14 ???
fjournal: Computing in Science and Engineering
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5992
rawauthor: Kaveh R. Ghazi and Vincent Lef{\`e}vre and Philippe Theveny and Paul Zimmermann
rawtitle: Why and How to Use Arbitrary Precision
entry:
@Article{Ghazi:2010:WHU,
  author =       "Kaveh R. Ghazi and Vincent Lef{\`e}vre and Philippe
                 Theveny and Paul Zimmermann",
  title =        "Why and How to Use Arbitrary Precision",
  journal =      j-COMPUT-SCI-ENG,
  volume =       "12",
  number =       "3",
  pages =        "5",
  month =        may # "\slash " # jun,
  year =         "2010",
  CODEN =        "CSENFA",
  DOI =          "https://doi.org/10.1109/MCSE.2010.73",
  ISSN =         "0740-7475 (print), 1558-1918 (electronic)",
  ISSN-L =       "1521-9615",
  bibdate =      "Thu May 13 11:08:14 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing in Science and Engineering",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5992",
}


bibtype: article
filename: fparith.bib
label: Hemmert:2010:FEF
author: K. Scott Hemmert and Keith D. Underwood
title: Fast, Efficient Floating-Point Adders and Multipliers for FPGAs
journal: j-TRETS
volume: 3
number: 3
pages: 11:1--11:??
month: sep
monthnumber: 9
year: 2010
DOI: https://doi.org/10.1145/1839480.1839481
ISSN: 1936-7406 (print), 1936-7414 (electronic) OR 19367406 (print), 19367414 (electronic)
ISSNL: 1936-7406 OR 19367406
bibdate: Fri Oct 8 18:26:34 MDT 2010
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.08 18:26:34 MDT
fjournal: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
keywords: floating point; FPGA; HPC; reconfigurable computing
acknowledgement: ack-nhfb
articleno: 11
journalURL: http://portal.acm.org/toc.cfm?id=J1151
rawauthor: K. Scott Hemmert and Keith D. Underwood
rawtitle: Fast, Efficient Floating-Point Adders and Multipliers for {FPGAs}
abstract:
Floating-point applications are a growing trend in the FPGA community. As such, it has become critical to create floating-point units optimized for standard FPGA technology. Unfortunately, the FPGA design space is very different from the VLSI design space; thus, optimizations for FPGAs can differ significantly from optimizations for VLSI. In particular, the FPGA environment constrains the design space such that only limited parallelism can be effectively exploited to reduce latency. Obtaining the right balances between clock speed, latency, and area in FPGAs can be particularly challenging. This article presents implementation details for an IEEE-754 standard floating-point adder and multiplier for FPGAs. The designs presented here enable a Xilinx Virtex4 FPGA (-11 speed grade) to achieve 270 MHz IEEE compliant double precision floating-point performance with a 9-stage adder pipeline and 14-stage multiplier pipeline. The area requirement is approximately 500 slices for the adder and under 750 slices for the multiplier.

rawabstract:
Floating-point applications are a growing trend in the FPGA community. As such, it has become critical to create floating-point units optimized for standard FPGA technology. Unfortunately, the FPGA design space is very different from the VLSI design space; thus, optimizations for FPGAs can differ significantly from optimizations for VLSI. In particular, the FPGA environment constrains the design space such that only limited parallelism can be effectively exploited to reduce latency. Obtaining the right balances between clock speed, latency, and area in FPGAs can be particularly challenging. This article presents implementation details for an IEEE-754 standard floating-point adder and multiplier for FPGAs. The designs presented here enable a Xilinx Virtex4 FPGA (-11 speed grade) to achieve 270 MHz IEEE compliant double precision floating-point performance with a 9-stage adder pipeline and 14-stage multiplier pipeline. The area requirement is approximately 500 slices for the adder and under 750 slices for the multiplier.

entry:
@Article{Hemmert:2010:FEF,
  author =       "K. Scott Hemmert and Keith D. Underwood",
  title =        "Fast, Efficient Floating-Point Adders and Multipliers
                 for {FPGAs}",
  journal =      j-TRETS,
  volume =       "3",
  number =       "3",
  pages =        "11:1--11:??",
  month =        sep,
  year =         "2010",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/1839480.1839481",
  ISSN =         "1936-7406 (print), 1936-7414 (electronic)",
  ISSN-L =       "1936-7406",
  bibdate =      "Fri Oct 8 18:26:34 MDT 2010",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating-point applications are a growing trend in the
                 FPGA community. As such, it has become critical to
                 create floating-point units optimized for standard FPGA
                 technology. Unfortunately, the FPGA design space is
                 very different from the VLSI design space; thus,
                 optimizations for FPGAs can differ significantly from
                 optimizations for VLSI. In particular, the FPGA
                 environment constrains the design space such that only
                 limited parallelism can be effectively exploited to
                 reduce latency. Obtaining the right balances between
                 clock speed, latency, and area in FPGAs can be
                 particularly challenging. This article presents
                 implementation details for an IEEE-754 standard
                 floating-point adder and multiplier for FPGAs. The
                 designs presented here enable a Xilinx Virtex4 FPGA
                 (-11 speed grade) to achieve 270 MHz IEEE compliant
                 double precision floating-point performance with a
                 9-stage adder pipeline and 14-stage multiplier
                 pipeline. The area requirement is approximately 500
                 slices for the adder and under 750 slices for the
                 multiplier.",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Transactions on Reconfigurable Technology and
                 Systems (TRETS)",
  journal-URL =  "http://portal.acm.org/toc.cfm?id=J1151",
  keywords =     "floating point; FPGA; HPC; reconfigurable computing",
}


bibtype: article
filename: fparith.bib
label: Jaberipur:2010:RDF
author: G. Jaberipur and B. Parhami and S. Gorgin
title: Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value
journal: j-IEEE-TRANS-COMPUT
volume: 59
number: 5
pages: 694--706
year: 2010
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2009.152
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sun Jul 3 11:52:28 MDT 2011
bibtimestamp: 2011.07.03 11:52:28 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5278659
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: G. Jaberipur and B. Parhami and S. Gorgin
rawtitle: Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib

entry:
@Article{Jaberipur:2010:RDF,
  author =       "G. Jaberipur and B. Parhami and S. Gorgin",
  title =        "Redundant-Digit Floating-Point Addition Scheme Based
                 on a Stored Rounding Value",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "59",
  number =       "5",
  pages =        "694--706",
  month =        "????",
  year =         "2010",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2009.152",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sun Jul 3 11:52:28 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5278659",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Jiang:2010:AEP
author: Hao Jiang and Shengguo Li and Lizhi Cheng and Fang Su
title: Accurate evaluation of a polynomial and its derivative in Bernstein form
journal: j-COMPUT-MATH-APPL
volume: 60
number: 3
pages: 744--755
month: aug
monthnumber: 8
year: 2010
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 21:50:42 MST 2017
bibtimestamp: 2017.03.01 21:50:42 MST
URL: http://www.sciencedirect.com/science/article/pii/S0898122110003706
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: Hao Jiang and Shengguo Li and Lizhi Cheng and Fang Su
rawtitle: Accurate evaluation of a polynomial and its derivative in {Bernstein} form
bibsource:
https://www.math.utah.edu/pub/tex/bib/computmathappl2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Jiang:2010:AEP,
  author =       "Hao Jiang and Shengguo Li and Lizhi Cheng and Fang
                 Su",
  title =        "Accurate evaluation of a polynomial and its derivative
                 in {Bernstein} form",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "60",
  number =       "3",
  pages =        "744--755",
  month =        aug,
  year =         "2010",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 21:50:42 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0898122110003706",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: misc
filename: fparith.bib
label: Kahan:2010:PUC
author: W. Kahan
pages: 18
day: 19
month: jul
monthnumber: 7
year: 2010
bibdate: Wed Aug 07 15:43:36 2024
bibtimestamp: 2024.08.07 15:43:36 ???
URL: https://people.eecs.berkeley.edu/~wkahan/19July10.pdf
acknowledgement: ack-nhfb
howpublished: Lecture slides
rawauthor: W. Kahan
title:
Pete's unsung contribution to IEEE Standard 754 for binary floating-point: a talk at a conference to celebrate G. W. ``Pete'' Stewart's 70th Birthday

bibsource:
https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib; https://www.math.utah.edu/pub/bibnet/authors/s/stewart-gilbert-w.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
{Pete}'s unsung contribution to {IEEE Standard 754} for binary floating-point: a talk at a conference to celebrate {G. W. ``Pete'' Stewart}'s 70th Birthday

entry:
@Misc{Kahan:2010:PUC,
  author =       "W. Kahan",
  title =        "{Pete}'s unsung contribution to {IEEE Standard 754}
                 for binary floating-point: a talk at a conference to
                 celebrate {G. W. ``Pete'' Stewart}'s 70th Birthday",
  howpublished = "Lecture slides",
  pages =        "18",
  day =          "19",
  month =        jul,
  year =         "2010",
  bibdate =      "Wed Aug 07 15:43:36 2024",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/bibnet/authors/s/stewart-gilbert-w.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://people.eecs.berkeley.edu/~wkahan/19July10.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kalla:2010:PIN
author: Ron Kalla and Balaram Sinharoy and William J. Starke and Michael Floyd
title: Power7: IBM's Next-Generation Server Processor
journal: j-IEEE-MICRO
volume: 30
number: 2
pages: 7--15
month: mar
monthnumber: 3
year: 2010
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/MM.2010.38
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Fri Apr 23 06:37:18 MDT 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.04.23 06:37:18 MDT
fjournal: IEEE Micro
acknowledgement: ack-nhfb
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: Ron Kalla and Balaram Sinharoy and William J. Starke and Michael Floyd
rawtitle: {Power7}: {IBM}'s Next-Generation Server Processor
keywords:
decimal floating-point arithmetic; fused multiply-add (FMA); IEEE 754-2008 arithmetic; subnormal numbers in hardware; underflow

entry:
@Article{Kalla:2010:PIN,
  author =       "Ron Kalla and Balaram Sinharoy and William J. Starke
                 and Michael Floyd",
  title =        "{Power7}: {IBM}'s Next-Generation Server Processor",
  journal =      j-IEEE-MICRO,
  volume =       "30",
  number =       "2",
  pages =        "7--15",
  month =        mar # "\slash " # apr,
  year =         "2010",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2010.38",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Fri Apr 23 06:37:18 MDT 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "decimal floating-point arithmetic; fused multiply-add
                 (FMA); IEEE 754-2008 arithmetic; subnormal numbers in
                 hardware; underflow",
}


