# bibtab

bibtype: phdthesis
filename: fparith.bib
label: Bewick:1994:FMA
author: Gary Bewick
title: Fast Multiplication: Algorithms and Implementations
type: Ph.D. thesis
school: Computer Systems Laboratory, Stanford University
address: Stanford, CA, USA
pages: 170
month: feb
monthnumber: 2
year: 1994
bibdate: Mon Dec 24 09:59:22 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.12.24 09:59:22 ???
note: Also issued as report CSL-TR-94-617
acknowledgement: ack-nhfb
rawauthor: Gary Bewick
rawnote: Also issued as report CSL-TR-94-617
rawtitle: Fast Multiplication: Algorithms and Implementations
entry:
@PhdThesis{Bewick:1994:FMA,
  author =       "Gary Bewick",
  title =        "Fast Multiplication: Algorithms and Implementations",
  type =         "{Ph.D.} thesis",
  school =       "Computer Systems Laboratory, Stanford University",
  address =      "Stanford, CA, USA",
  pages =        "170",
  month =        feb,
  year =         "1994",
  bibdate =      "Mon Dec 24 09:59:22 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Also issued as report CSL-TR-94-617",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: BrinchHansen:1994:MLD
author: Per Brinch Hansen
title: Multiple-length Division Revisited: a Tour of the Minefield
journal: j-SPE
volume: 24
number: 6
pages: 579--601
month: jun
monthnumber: 6
year: 1994
CODEN: SPEXBL
DOI: https://doi.org/10.1002/spe.4380240605
ISSN: 0038-0644 (print), 1097-024X (electronic) OR 00380644 (print), 1097024X (electronic)
ISSNL: 0038-0644 OR 00380644
bibdate: Fri Nov 28 17:07:54 2003
bibtimestamp: 2003.11.28 17:07:54 ???
URL: http://brinch-hansen.net/papers/1994b.pdf
fjournal: Software --- Practice and Experience
keywords: algorithms; multiple-length integer division
acknowledgement: ack-nj
ajournal: Softw. Pract. Exp.
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X
onlinedate: 30 Oct 2006
rawauthor: Per {Brinch Hansen}
rawtitle: Multiple-length Division Revisited: a Tour of the Minefield
bibsource:
ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/bibnet/authors/h/hansen-per-brinch.bib; https://www.math.utah.edu/pub/tex/bib/cryptography1990.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/litprog.bib; https://www.math.utah.edu/pub/tex/bib/spe.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

note:
This paper derives an algorithm for division of long integers, and implements it as a literate program, although without identifier cross-references. See also related work on division cite BrinchHansen:1995:LDA,Regener:1984:MID .

abstract:
Long division of natural numbers plays a crucial role in Cobol arithmetic, cryptography, and primality testing. Only a handful of textbooks discuss the theory and practice of long division, and none of them do it satisfactorily. This tutorial attempts to fill this surprising gap in the literature on computer algorithms. We illustrate the subtleties of long division by examples, define the problem concisely, summarize the theory, and develop a complete Pascal algorithm using a consistent terminology.

rawabstract:
Long division of natural numbers plays a crucial role in Cobol arithmetic, cryptography, and primality testing. Only a handful of textbooks discuss the theory and practice of long division, and none of them do it satisfactorily. This tutorial attempts to fill this surprising gap in the literature on computer algorithms. We illustrate the subtleties of long division by examples, define the problem concisely, summarize the theory, and develop a complete Pascal algorithm using a consistent terminology.

rawnote:
This paper derives an algorithm for division of long integers, and implements it as a literate program, although without identifier cross-references. See also related work on division \cite{BrinchHansen:1995:LDA,Regener:1984:MID} .

entry:
@Article{BrinchHansen:1994:MLD,
  author =       "Per {Brinch Hansen}",
  title =        "Multiple-length Division Revisited: a Tour of the
                 Minefield",
  journal =      j-SPE,
  volume =       "24",
  number =       "6",
  pages =        "579--601",
  month =        jun,
  year =         "1994",
  CODEN =        "SPEXBL",
  DOI =          "https://doi.org/10.1002/spe.4380240605",
  ISSN =         "0038-0644 (print), 1097-024X (electronic)",
  ISSN-L =       "0038-0644",
  bibdate =      "Fri Nov 28 17:07:54 2003",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/bibnet/authors/h/hansen-per-brinch.bib;
                 https://www.math.utah.edu/pub/tex/bib/cryptography1990.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/litprog.bib;
                 https://www.math.utah.edu/pub/tex/bib/spe.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  note =         "This paper derives an algorithm for division of long
                 integers, and implements it as a literate program,
                 although without identifier cross-references. See also
                 related work on division
                 \cite{BrinchHansen:1995:LDA,Regener:1984:MID} .",
  URL =          "http://brinch-hansen.net/papers/1994b.pdf",
  abstract =     "Long division of natural numbers plays a crucial role
                 in Cobol arithmetic, cryptography, and primality
                 testing. Only a handful of textbooks discuss the theory
                 and practice of long division, and none of them do it
                 satisfactorily. This tutorial attempts to fill this
                 surprising gap in the literature on computer
                 algorithms. We illustrate the subtleties of long
                 division by examples, define the problem concisely,
                 summarize the theory, and develop a complete Pascal
                 algorithm using a consistent terminology.",
  acknowledgement = ack-nj # " and " # ack-mfc # " and " # ack-nhfb,
  ajournal =     "Softw. Pract. Exp.",
  fjournal =     "Software --- Practice and Experience",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X",
  keywords =     "algorithms; multiple-length integer division",
  onlinedate =   "30 Oct 2006",
}


bibtype: inproceedings
filename: fparith.bib
label: Brosgol:1994:ISD
author: Benjamin M. Brosgol and Robert I. Eachus and David E. Emery
title: Information Systems Development in Ada
crossref: ACM:1994:AAW
pages: 2--16
year: 1994
bibdate: Fri Nov 28 16:05:55 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 16:05:55 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-mfc
rawauthor: Benjamin M. Brosgol and Robert I. Eachus and David E. Emery
rawtitle: Information Systems Development in {Ada}
abstract:
In this paper we survey how to use Ada (both Ada 83 and Ada 9X) for IS applications, with a focus on two principal issues: Specification of the information architecture of an IS application, and Programming techniques relevant to financial and related applications.par We cover both the language features and the supplemental packages for IS development. Special attention will be paid to the Ada Decimal-Associated Reusabilia (`ADAR') components for Ada 83 and transitioning to Ada 9X.

rawabstract:
In this paper we survey how to use Ada (both Ada 83 and Ada 9X) for IS applications, with a focus on two principal issues: Specification of the information architecture of an IS application, and Programming techniques relevant to financial and related applications.\par We cover both the language features and the supplemental packages for IS development. Special attention will be paid to the Ada Decimal-Associated Reusabilia (`ADAR') components for Ada 83 and transitioning to Ada 9X.

entry:
@InProceedings{Brosgol:1994:ISD,
  author =       "Benjamin M. Brosgol and Robert I. Eachus and David E.
                 Emery",
  title =        "Information Systems Development in {Ada}",
  crossref =     "ACM:1994:AAW",
  pages =        "2--16",
  year =         "1994",
  bibdate =      "Fri Nov 28 16:05:55 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper we survey how to use Ada (both Ada 83
                 and Ada 9X) for IS applications, with a focus on two
                 principal issues: Specification of the information
                 architecture of an IS application, and Programming
                 techniques relevant to financial and related
                 applications.\par

                 We cover both the language features and the
                 supplemental packages for IS development. Special
                 attention will be paid to the Ada Decimal-Associated
                 Reusabilia (`ADAR') components for Ada 83 and
                 transitioning to Ada 9X.",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: mastersthesis
filename: fparith.bib
label: Bull:1994:SFF
author: Nathan Lee Bull
title: A study of frequency-sampling filters realized on floating-point digital signal processors
type: Thesis (M.S.)
school: University of Tennessee, Knoxville
address: Knoxville, TN, USA
pages: vii + 56
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Digital filters (Mathematics)
acknowledgement: ack-nhfb
rawauthor: Nathan Lee Bull
rawtitle: A study of frequency-sampling filters realized on floating-point digital signal processors
entry:
@MastersThesis{Bull:1994:SFF,
  author =       "Nathan Lee Bull",
  title =        "A study of frequency-sampling filters realized on
                 floating-point digital signal processors",
  type =         "Thesis ({M.S.})",
  school =       "University of Tennessee, Knoxville",
  address =      "Knoxville, TN, USA",
  pages =        "vii + 56",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Digital filters (Mathematics)",
}


bibtype: article
filename: fparith.bib
label: Carr:1994:IRM
author: S. Carr and K. Kennedy
title: Improving the Ratio of Memory Operations in Floating-Point Operations in Loops
journal: j-TOPLAS
volume: 16
number: 6
pages: 1768--1810
month: nov
monthnumber: 11
year: 1994
CODEN: ATPSDT
ISSN: 0164-0925 (print), 1558-4593 (electronic) OR 01640925 (print), 15584593 (electronic)
ISSNL: 0164-0925 OR 01640925
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: ACM Transactions on Programming Languages and Systems
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, Michigan Technol. University, Houghton, MI, USA
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J783
rawauthor: S. Carr and K. Kennedy
rawtitle: Improving the Ratio of Memory Operations in Floating-Point Operations in Loops
abstract:
Over the past decade, microprocessor design strategies have focused on increasing the computational power on a single chip. Because computations often require more data from cache per floating-point operation than a machine can deliver and because operations are pipelined, idle computational cycles are common when scientific applications are executed. To overcome these bottlenecks, programmers have learned to use a coding style that ensures a better balance between memory references and floating-point operations. In our view, this is a step in the wrong direction because it makes programs more machine-specific. A programmer should not be required to write a new program version for each new machine; instead, the task of specializing a program to a target machine should be left to the compiler. But is our view practical? Can a sophisticated optimizing compiler obviate the need for the myriad of programming tricks that have found their way into practice to improve the performance of the memory hierarchy? In this paper we attempt to answer that question. To do so, we develop and evaluate techniques that automatically restructure program loops to achieve high performance on specific target architectures. These methods attempt to balance computation and memory accesses and seek to eliminate or reduce pipeline interlock. To do this, they estimate statically the balance between memory operations and floating-point operations for each loop in a particular program and use these estimates to determine whether to apply various loop transformations. Experiments with our automatic techniques show that integer-factor speedups are possible on kernels. Additionally, the estimate of the balance between memory operations and computation, and the application of the estimate are very accurate-experiments reveal little difference between the balance achieved by our automatic system and that possible by hand optimization.

keywords:
Bottlenecks; Floating-point operations; Integer-factor speedups; Memory operations; Memory references; Microprocessor design strategies; Pipeline interlock; Program loops; Sophisticated optimizing compiler

thesaurus:
Floating point arithmetic; Optimising compilers; Pipeline processing; Program control structures; Storage management

rawabstract:
Over the past decade, microprocessor design strategies have focused on increasing the computational power on a single chip. Because computations often require more data from cache per floating-point operation than a machine can deliver and because operations are pipelined, idle computational cycles are common when scientific applications are executed. To overcome these bottlenecks, programmers have learned to use a coding style that ensures a better balance between memory references and floating-point operations. In our view, this is a step in the wrong direction because it makes programs more machine-specific. A programmer should not be required to write a new program version for each new machine; instead, the task of specializing a program to a target machine should be left to the compiler. But is our view practical? Can a sophisticated optimizing compiler obviate the need for the myriad of programming tricks that have found their way into practice to improve the performance of the memory hierarchy? In this paper we attempt to answer that question. To do so, we develop and evaluate techniques that automatically restructure program loops to achieve high performance on specific target architectures. These methods attempt to balance computation and memory accesses and seek to eliminate or reduce pipeline interlock. To do this, they estimate statically the balance between memory operations and floating-point operations for each loop in a particular program and use these estimates to determine whether to apply various loop transformations. Experiments with our automatic techniques show that integer-factor speedups are possible on kernels. Additionally, the estimate of the balance between memory operations and computation, and the application of the estimate are very accurate-experiments reveal little difference between the balance achieved by our automatic system and that possible by hand optimization.

entry:
@Article{Carr:1994:IRM,
  author =       "S. Carr and K. Kennedy",
  title =        "Improving the Ratio of Memory Operations in
                 Floating-Point Operations in Loops",
  journal =      j-TOPLAS,
  volume =       "16",
  number =       "6",
  pages =        "1768--1810",
  month =        nov,
  year =         "1994",
  CODEN =        "ATPSDT",
  ISSN =         "0164-0925 (print), 1558-4593 (electronic)",
  ISSN-L =       "0164-0925",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Over the past decade, microprocessor design strategies
                 have focused on increasing the computational power on a
                 single chip. Because computations often require more
                 data from cache per floating-point operation than a
                 machine can deliver and because operations are
                 pipelined, idle computational cycles are common when
                 scientific applications are executed. To overcome these
                 bottlenecks, programmers have learned to use a coding
                 style that ensures a better balance between memory
                 references and floating-point operations. In our view,
                 this is a step in the wrong direction because it makes
                 programs more machine-specific. A programmer should not
                 be required to write a new program version for each new
                 machine; instead, the task of specializing a program to
                 a target machine should be left to the compiler. But is
                 our view practical? Can a sophisticated optimizing
                 compiler obviate the need for the myriad of programming
                 tricks that have found their way into practice to
                 improve the performance of the memory hierarchy? In
                 this paper we attempt to answer that question. To do
                 so, we develop and evaluate techniques that
                 automatically restructure program loops to achieve high
                 performance on specific target architectures. These
                 methods attempt to balance computation and memory
                 accesses and seek to eliminate or reduce pipeline
                 interlock. To do this, they estimate statically the
                 balance between memory operations and floating-point
                 operations for each loop in a particular program and
                 use these estimates to determine whether to apply
                 various loop transformations. Experiments with our
                 automatic techniques show that integer-factor speedups
                 are possible on kernels. Additionally, the estimate of
                 the balance between memory operations and computation,
                 and the application of the estimate are very
                 accurate-experiments reveal little difference between
                 the balance achieved by our automatic system and that
                 possible by hand optimization.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, Michigan Technol.
                 University, Houghton, MI, USA",
  classification = "C5230 (Digital arithmetic methods); C6120 (File
                 organisation); C6150C (Compilers, interpreters and
                 other processors)",
  fjournal =     "ACM Transactions on Programming Languages and
                 Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J783",
  keywords =     "Bottlenecks; Floating-point operations; Integer-factor
                 speedups; Memory operations; Memory references;
                 Microprocessor design strategies; Pipeline interlock;
                 Program loops; Sophisticated optimizing compiler",
  thesaurus =    "Floating point arithmetic; Optimising compilers;
                 Pipeline processing; Program control structures;
                 Storage management",
}


bibtype: mastersthesis
filename: fparith.bib
label: Chandramouli:1994:DSP
author: V. Chandramouli
title: Design of a self-timed, pipelined, floating point multiplier in gallium arsenide
type: Thesis (M.S.)
school: Department of Computer Science, University of Utah
address: Salt Lake City, UT, USA
pages: xiii + 121
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Computer architecture.; Gallium arsenide semiconductors.
acknowledgement: ack-nhfb
rawauthor: V. Chandramouli
rawtitle: Design of a self-timed, pipelined, floating point multiplier in gallium arsenide
entry:
@MastersThesis{Chandramouli:1994:DSP,
  author =       "V. Chandramouli",
  title =        "Design of a self-timed, pipelined, floating point
                 multiplier in gallium arsenide",
  type =         "Thesis ({M.S.})",
  school =       "Department of Computer Science, University of Utah",
  address =      "Salt Lake City, UT, USA",
  pages =        "xiii + 121",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Computer architecture.; Gallium arsenide
                 semiconductors.",
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:1994:EDU
author: Sau-Gee Chen and Chieh-Chih Li
title: Efficient designs of unified $2$'s complement division and square root algorithm and architecture
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 943--947
year: 1994
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: Sau-Gee Chen and Chieh-Chih Li
rawtitle: Efficient designs of unified $2$'s complement division and square root algorithm and architecture
booktitle:
Proceedings of TENCON '94. IEEE Region 10's Ninth Annual International Conference. Theme: `Frontiers of Computer Technology'

rawbooktitle:
Proceedings of {TENCON '94}. {IEEE} Region 10's Ninth Annual International Conference. Theme: `Frontiers of Computer Technology'

entry:
@InProceedings{Chen:1994:EDU,
  author =       "Sau-Gee Chen and Chieh-Chih Li",
  booktitle =    "Proceedings of {TENCON '94}. {IEEE} Region 10's Ninth
                 Annual International Conference. Theme: `Frontiers of
                 Computer Technology'",
  title =        "Efficient designs of unified $2$'s complement division
                 and square root algorithm and architecture",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "943--947",
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Efficient unified 2's complement division and square
                 root algorithm, and their architectures are proposed in
                 this work. The designs are high speed, small area and
                 high compatibility. The architectures provide bit level
                 pipelined operation, as well \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chesneaux:1994:ERS
author: J.-M. Chesneaux
title: The equality relations in scientific computing
journal: j-NUMER-ALGORITHMS
volume: 7
number: 2-4
pages: 129--143
month: jul
monthnumber: 7
year: 1994
CODEN: NUALEG
ISSN: 1017-1398 (print), 1572-9265 (electronic) OR 10171398 (print), 15729265 (electronic)
ISSNL: 1017-1398 OR 10171398
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: Numerical Algorithms
acknowledgement: ack-nhfb
affiliation: Laboratoire MASI, Universite Pierre et Marie Curie, Paris, France
journalURL: http://link.springer.com/journal/11075
thesaurus: Digital arithmetic; Mathematics computing; Roundoff errors
rawauthor: J.-M. Chesneaux
rawtitle: The equality relations in scientific computing
abstract:
The equality relation (more generally, the ordering relations) in floating point arithmetic is the exact translation of the mathematical equality relation. Because of the propagation of round-off errors, the floating point arithmetic is not the exact representation of the theoretical arithmetic which is continuous on the real numbers. This leads to some incoherence when the equality concept is used in floating point arithmetic. A well known example is the detection of a zero element in the pivoting column and equation when applying Gaussian elimination, which is almost impossible in floating point arithmetic. The author begins by showing the inadequacy of the equality relation used in floating point arithmetic (the author calls it floating point equality), and then introduces two new concepts stochastic numbers and the equality relation between such numbers which is called the stochastic equality. It is shown how these concepts allow recovery of the coherence between the arithmetic operators and the ordering relations that was missing in floating point computations.

keywords:
Arithmetic operators; Equality relations; Floating point arithmetic; Floating point equality; Gaussian elimination; Ordering relations; Pivoting column; Round-off errors; Scientific computing; Stochastic equality; Stochastic numbers; Zero element

rawabstract:
The equality relation (more generally, the ordering relations) in floating point arithmetic is the exact translation of the mathematical equality relation. Because of the propagation of round-off errors, the floating point arithmetic is not the exact representation of the theoretical arithmetic which is continuous on the real numbers. This leads to some incoherence when the equality concept is used in floating point arithmetic. A well known example is the detection of a zero element in the pivoting column and equation when applying Gaussian elimination, which is almost impossible in floating point arithmetic. The author begins by showing the inadequacy of the equality relation used in floating point arithmetic (the author calls it floating point equality), and then introduces two new concepts stochastic numbers and the equality relation between such numbers which is called the stochastic equality. It is shown how these concepts allow recovery of the coherence between the arithmetic operators and the ordering relations that was missing in floating point computations.

entry:
@Article{Chesneaux:1994:ERS,
  author =       "J.-M. Chesneaux",
  title =        "The equality relations in scientific computing",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "7",
  number =       "2-4",
  pages =        "129--143",
  month =        jul,
  year =         "1994",
  CODEN =        "NUALEG",
  ISSN =         "1017-1398 (print), 1572-9265 (electronic)",
  ISSN-L =       "1017-1398",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The equality relation (more generally, the ordering
                 relations) in floating point arithmetic is the exact
                 translation of the mathematical equality relation.
                 Because of the propagation of round-off errors, the
                 floating point arithmetic is not the exact
                 representation of the theoretical arithmetic which is
                 continuous on the real numbers. This leads to some
                 incoherence when the equality concept is used in
                 floating point arithmetic. A well known example is the
                 detection of a zero element in the pivoting column and
                 equation when applying Gaussian elimination, which is
                 almost impossible in floating point arithmetic. The
                 author begins by showing the inadequacy of the equality
                 relation used in floating point arithmetic (the author
                 calls it floating point equality), and then introduces
                 two new concepts stochastic numbers and the equality
                 relation between such numbers which is called the
                 stochastic equality. It is shown how these concepts
                 allow recovery of the coherence between the arithmetic
                 operators and the ordering relations that was missing
                 in floating point computations.",
  acknowledgement = ack-nhfb,
  affiliation =  "Laboratoire MASI, Universit{\'e} Pierre et Marie
                 Curie, Paris, France",
  classification = "C5230 (Digital arithmetic methods); C7310
                 (Mathematics)",
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
  keywords =     "Arithmetic operators; Equality relations; Floating
                 point arithmetic; Floating point equality; Gaussian
                 elimination; Ordering relations; Pivoting column;
                 Round-off errors; Scientific computing; Stochastic
                 equality; Stochastic numbers; Zero element",
  pubcountry =   "Switzerland",
  thesaurus =    "Digital arithmetic; Mathematics computing; Roundoff
                 errors",
}


bibtype: inproceedings
filename: fparith.bib
label: Chren:1994:ALIa
author: W. A. Chren, Jr.
booktitle: Proceedings of the 37th Midwest Symposium on Circuits and Systems, 1994
title: Area and latency improvements for direct digital synthesis using the residue number system
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 269--273
year: 1994
DOI: https://doi.org/10.1109/MWSCAS.1994.519237
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: W. A. {Chren, Jr.}
rawbooktitle: Proceedings of the 37th Midwest Symposium on Circuits and Systems, 1994
rawtitle: Area and latency improvements for direct digital synthesis using the residue number system
entry:
@InProceedings{Chren:1994:ALIa,
  author =       "W. A. {Chren, Jr.}",
  booktitle =    "Proceedings of the 37th Midwest Symposium on Circuits
                 and Systems, 1994",
  title =        "Area and latency improvements for direct digital
                 synthesis using the residue number system",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "269--273",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MWSCAS.1994.519237",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Two residue number system-based direct digital
                 synthesizers are presented. The High-Agility Direct
                 Synthesizer exhibits a frequency switching latency
                 which is reduced by as much as 50\% below that of
                 traditional, binary number system-based designs.
                 \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Chren:1994:ALIb
author: W. A. Chren, Jr.
title: Area and latency improvements for direct digital synthesis using the residue number system
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 269--273
year: 1994
DOI: https://doi.org/10.1109/MWSCAS.1994.519237
ISBN: 0-7803-2428-5 OR 0780324285
ISBN13: 978-0-7803-2428-2 OR 9780780324282
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: W. A. {Chren, Jr.}
rawtitle: Area and latency improvements for direct digital synthesis using the residue number system
booktitle:
Proceedings of the 37th Midwest Symposium on Circuits and Systems, 1994. 3--5 August 1994, Lafayette, LA, USA

rawbooktitle:
Proceedings of the 37th Midwest Symposium on Circuits and Systems, 1994. 3--5 August 1994, Lafayette, {LA}, {USA}

entry:
@InProceedings{Chren:1994:ALIb,
  author =       "W. A. {Chren, Jr.}",
  booktitle =    "Proceedings of the 37th Midwest Symposium on Circuits
                 and Systems, 1994. 3--5 August 1994, Lafayette, {LA},
                 {USA}",
  title =        "Area and latency improvements for direct digital
                 synthesis using the residue number system",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "269--273",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MWSCAS.1994.519237",
  ISBN =         "0-7803-2428-5",
  ISBN-13 =      "978-0-7803-2428-2",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Two residue number system-based direct digital
                 synthesizers are presented. The High-Agility Direct
                 Synthesizer exhibits a frequency switching latency
                 which is reduced by as much as 50\% below that of
                 traditional, binary number system-based designs. The
                 Reduced Area Direct Synthesizer has a chip area which
                 is reduced by more than 40\%. The area reduction is due
                 primarily to the decomposition of the sine ROM into
                 several small look-up tables, while the latency
                 reduction is due to the shortening of the carry paths
                 in the phase accumulator",
}


bibtype: article
filename: fparith.bib
label: Cortadella:1994:HRD
author: J. Cortadella and T. Lang
title: High-Radix Division and Square-Root with Speculation
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 919--931
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295854
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:57 MDT 2011
bibtimestamp: 2011.07.07 07:13:57 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295854
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-sfo
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. Cortadella and T. Lang
rawtitle: High-Radix Division and Square-Root with Speculation
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib; OCLC Proceedings database

entry:
@Article{Cortadella:1994:HRD,
  author =       "J. Cortadella and T. Lang",
  title =        "High-Radix Division and Square-Root with Speculation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "919--931",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295854",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:57 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295854",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
  summary =      "The speed of high-radix digit-recurrence dividers and
                 square-root units is mainly determined by the
                 complexity of the result-digit selection. We present a
                 scheme in which a simpler function speculates the
                 result digit, and, when this speculation is \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Dallaway:1994:DAC
author: Richard Z. Dallaway
title: Dynamics of Arithmetic: a Connectionist View of Arithmetic Skills
type: Technical report
number: CSRP 306
institution: Univerity of Sussex
address: Brighton, UK
pages: 159
month: feb
monthnumber: 2
year: 1994
ISSN: 1350-3162 OR 13503162
bibdate: Fri Nov 28 16:36:28 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 16:36:28 ???
acknowledgement: ack-mfc
rawauthor: Richard Z. Dallaway
rawtitle: Dynamics of Arithmetic: a Connectionist View of Arithmetic Skills
entry:
@TechReport{Dallaway:1994:DAC,
  author =       "Richard Z. Dallaway",
  title =        "Dynamics of Arithmetic: a Connectionist View of
                 Arithmetic Skills",
  type =         "Technical report",
  number =       "CSRP 306",
  institution =  "Univerity of Sussex",
  address =      "Brighton, UK",
  pages =        "159",
  month =        feb,
  year =         "1994",
  ISSN =         "1350-3162",
  bibdate =      "Fri Nov 28 16:36:28 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: DasSarma:1994:MAR
author: D. DasSarma and D. W. Matula
title: Measuring the Accuracy of ROM Reciprocal Tables
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 932--940
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295855
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:16:49 MDT
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-sfo
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. DasSarma and D. W. Matula
rawtitle: Measuring the Accuracy of {ROM} Reciprocal Tables
entry:
@Article{DasSarma:1994:MAR,
  author =       "D. DasSarma and D. W. Matula",
  title =        "Measuring the Accuracy of {ROM} Reciprocal Tables",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "932--940",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295855",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Daumas:1994:FAR
author: M. Daumas and C. Mazenc and X. Merrheim and J. M. Muller
title: Fast and accurate range reduction for computation of the elementary functions
crossref: Ames:1994:IPI
pages: ??--??
year: 1994
bibdate: Sat Jun 25 08:57:47 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.25 08:57:47 ???
keywords: range reduction
acknowledgement: ack-nhfb
rawauthor: M. Daumas and C. Mazenc and X. Merrheim and J. M. Muller
rawtitle: Fast and accurate range reduction for computation of the elementary functions
entry:
@InProceedings{Daumas:1994:FAR,
  author =       "M. Daumas and C. Mazenc and X. Merrheim and J. M.
                 Muller",
  title =        "Fast and accurate range reduction for computation of
                 the elementary functions",
  crossref =     "Ames:1994:IPI",
  pages =        "??--??",
  year =         "1994",
  bibdate =      "Sat Jun 25 08:57:47 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "range reduction",
}


bibtype: article
filename: fparith.bib
label: Daumas:1994:RFP
author: Marc Daumas and David W. Matula
title: Rounding of floating point intervals
journal: j-INTERVAL-COMP
volume: 4
pages: 28--45
year: 1994
ISSN: 0135-4868 OR 01354868
MRclass: 65G10 (65G05)
MRnumber: 1 332 074
bibdate: Fri Dec 8 08:24:03 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:03 ???
fjournal: Interval Computations = Interval'nye vychisleniia
acknowledgement: ack-nhfb
rawauthor: Marc Daumas and David W. Matula
rawtitle: Rounding of floating point intervals
entry:
@Article{Daumas:1994:RFP,
  author =       "Marc Daumas and David W. Matula",
  title =        "Rounding of floating point intervals",
  journal =      j-INTERVAL-COMP,
  volume =       "4",
  pages =        "28--45",
  year =         "1994",
  ISSN =         "0135-4868",
  MRclass =      "65G10 (65G05)",
  MRnumber =     "1 332 074",
  bibdate =      "Fri Dec 8 08:24:03 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Interval Computations = Interval'nye vychisleniia",
  xxnote =       "SCAN-93 (Vienna, 1993)",
}


bibtype: article
filename: fparith.bib
label: De:1994:FPA
author: M. De and B. P. Sinha
title: Fast parallel algorithm for ternary multiplication using multivalued $ I^2 L $ technology
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 5
pages: 603--607
month: may
monthnumber: 5
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.280807
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:55 MDT 2011
bibtimestamp: 2011.07.07 07:13:55 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=280807
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. De and B. P. Sinha
rawtitle: Fast parallel algorithm for ternary multiplication using multivalued {$ I^2 L $} technology
entry:
@Article{De:1994:FPA,
  author =       "M. De and B. P. Sinha",
  title =        "Fast parallel algorithm for ternary multiplication
                 using multivalued {$ I^2 L $} technology",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "5",
  pages =        "603--607",
  month =        may,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.280807",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:55 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=280807",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: delaSerna:1994:TBF
author: A. E. de la Serna and M. A. Soderstrand
booktitle: Conference Record of the Twenty-Eighth Asilomar Conference on Signals, Systems and Computers, 1994
title: Trade-off between FPGA resource utilization and roundoff error in optimized CSD FIR digital filters
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 187--191
year: 1994
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: A. E. de la Serna and M. A. Soderstrand
rawbooktitle: Conference Record of the Twenty-Eighth Asilomar Conference on Signals, Systems and Computers, 1994
rawtitle:
Trade-off between {FPGA} resource utilization and roundoff error in optimized {CSD} {FIR} digital filters

entry:
@InProceedings{delaSerna:1994:TBF,
  author =       "A. E. de la Serna and M. A. Soderstrand",
  booktitle =    "Conference Record of the Twenty-Eighth Asilomar
                 Conference on Signals, Systems and Computers, 1994",
  title =        "Trade-off between {FPGA} resource utilization and
                 roundoff error in optimized {CSD} {FIR} digital
                 filters",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "187--191",
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "In this paper, we investigate the trade off between
                 filter order and bits of coefficient precision in
                 fixed-coefficient FIR digital filters utilizing
                 canonical signed digit (CSD) coefficient
                 representation. We demonstrate that the use of
                 optimized \ldots{}",
}


bibtype: article
filename: fparith.bib
label: delRosario:1994:HIM
author: J. M. del Rosario and A. N. Choudhary
title: High-performance I/O for massively parallel computers: problems and prospects
journal: j-COMPUTER
volume: 27
number: 3
pages: 59--68
month: mar
monthnumber: 3
year: 1994
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Fri Sep 13 16:03:42 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.09.13 16:03:42 MDT
fjournal: Computer
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Syracuse University, NY, USA
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
rawauthor: J. M. del Rosario and A. N. Choudhary
rawtitle: High-performance {I/O} for massively parallel computers: problems and prospects
keywords:
Access patterns; Compilers; File systems; Floating-point operations per second; Hardware technology; High-performance I/O; High-performance storage systems; High-speed networking; I/O infrastructure; Language interfaces; Massive parallel processing; Massively parallel computers; Networking technology; Operating systems; Parallel I/O problem; Powerful supercomputers; Resource-management approaches; Runtime system; Teraflops barrier; Visualization systems

thesaurus:
Computer networks; Input-output programs; Network operating systems; Parallel machines; Parallel programming

entry:
@Article{delRosario:1994:HIM,
  author =       "J. M. del Rosario and A. N. Choudhary",
  title =        "High-performance {I/O} for massively parallel
                 computers: problems and prospects",
  journal =      j-COMPUTER,
  volume =       "27",
  number =       "3",
  pages =        "59--68",
  month =        mar,
  year =         "1994",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Fri Sep 13 16:03:42 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. and Comput. Eng., Syracuse
                 University, NY, USA",
  classification = "B6210L (Computer communications); C5440
                 (Multiprocessor systems and techniques); C5620
                 (Computer networks and techniques); C6110P (Parallel
                 programming); C6150N (Distributed systems)",
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "Access patterns; Compilers; File systems;
                 Floating-point operations per second; Hardware
                 technology; High-performance I/O; High-performance
                 storage systems; High-speed networking; I/O
                 infrastructure; Language interfaces; Massive parallel
                 processing; Massively parallel computers; Networking
                 technology; Operating systems; Parallel I/O problem;
                 Powerful supercomputers; Resource-management
                 approaches; Runtime system; Teraflops barrier;
                 Visualization systems",
  thesaurus =    "Computer networks; Input-output programs; Network
                 operating systems; Parallel machines; Parallel
                 programming",
}


bibtype: techreport
filename: fparith.bib
label: Demmel:1994:CPBa
author: James Demmel and Inderjit Dhillon and Huan Ren
title: On the correctness of parallel bisection in floating point
type: Report
number: UCB/CSD 94/805
institution: Computer Science Division (EECS), University of California
address: Berkeley, CA, USA
pages: 38
month: mar
monthnumber: 3
year: 1994
bibdate: Thu Aug 23 06:41:11 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.08.23 06:41:11 ???
note: Also known as LAPACK Working Note number 70.
URL: http://www.neglib.org/lapack/lawns/lawn70.ps
acknowledgement: ack-nhfb
rawauthor: James Demmel and Inderjit Dhillon and Huan Ren
rawnote: Also known as LAPACK Working Note number 70.
rawtitle: On the correctness of parallel bisection in floating point
entry:
@TechReport{Demmel:1994:CPBa,
  author =       "James Demmel and Inderjit Dhillon and Huan Ren",
  title =        "On the correctness of parallel bisection in floating
                 point",
  type =         "Report",
  number =       "UCB/CSD 94/805",
  institution =  "Computer Science Division (EECS), University of
                 California",
  address =      "Berkeley, CA, USA",
  pages =        "38",
  month =        mar,
  year =         "1994",
  bibdate =      "Thu Aug 23 06:41:11 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Also known as LAPACK Working Note number 70.",
  URL =          "http://www.neglib.org/lapack/lawns/lawn70.ps",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Demmel:1994:CPBb
author: James Demmel and Inderjit Dhillon and Huan Ren
title: On the Correctness of Parallel Bisection in Floating Point
type: LAPACK Working Note
number: 70
institution: inst-UT-CS
address: inst-UT-CS:adr
pages: 38
month: mar
monthnumber: 3
year: 1994
bibdate: Fri Apr 22 17:06:37 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.22 17:06:37 ???
note: UT-CS-94-228, March 1994.
URL: http://www.netlib.org/lapack/lawns/lawn70.ps; http://www.netlib.org/lapack/lawnspdf/lawn70.pdf
acknowledgement: ack-nhfb
rawauthor: James Demmel and Inderjit Dhillon and Huan Ren
rawnote: UT-CS-94-228, March 1994.
rawtitle: On the Correctness of Parallel Bisection in Floating Point
entry:
@TechReport{Demmel:1994:CPBb,
  author =       "James Demmel and Inderjit Dhillon and Huan Ren",
  title =        "On the Correctness of Parallel Bisection in Floating
                 Point",
  type =         "LAPACK Working Note",
  number =       "70",
  institution =  inst-UT-CS,
  address =      inst-UT-CS:adr,
  month =        mar,
  year =         "1994",
  bibdate =      "Fri Apr 22 17:06:37 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "UT-CS-94-228, March 1994.",
  URL =          "http://www.netlib.org/lapack/lawns/lawn70.ps;
                 http://www.netlib.org/lapack/lawnspdf/lawn70.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Demmel:1994:FNA
author: James W. Demmel and Xiaoye Li
title: Faster Numerical Algorithms via Exception Handling
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 983--992
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295860
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:16:49 MDT
note: This is an expanded version of cite Demmel:1993:FNA.
URL: http://www.cs.berkeley.edu/~xiaoye/ieee.ps.gz
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: James W. Demmel and Xiaoye Li
rawnote: This is an expanded version of \cite{Demmel:1993:FNA}.
rawtitle: Faster Numerical Algorithms via Exception Handling
entry:
@Article{Demmel:1994:FNA,
  author =       "James W. Demmel and Xiaoye Li",
  title =        "Faster Numerical Algorithms via Exception Handling",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "983--992",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295860",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  note =         "This is an expanded version of
                 \cite{Demmel:1993:FNA}.",
  URL =          "http://www.cs.berkeley.edu/~xiaoye/ieee.ps.gz",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Dimauro:1994:DFNa
author: G. Dimauro and S. Impedovo and G. Pirlo
booktitle: Proceedings of the 20th EUROMICRO Conference, EUROMICRO 94. System Architecture and Integration
title: The `diagonal function' in non-redundant residue number system
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 590--596
year: 1994
DOI: https://doi.org/10.1109/EURMIC.1994.390354
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: G. Dimauro and S. Impedovo and G. Pirlo
rawbooktitle: Proceedings of the 20th {EUROMICRO} Conference, {EUROMICRO 94}. System Architecture and Integration
rawtitle: The `diagonal function' in non-redundant residue number system
entry:
@InProceedings{Dimauro:1994:DFNa,
  author =       "G. Dimauro and S. Impedovo and G. Pirlo",
  booktitle =    "Proceedings of the 20th {EUROMICRO} Conference,
                 {EUROMICRO 94}. System Architecture and Integration",
  title =        "The `diagonal function' in non-redundant residue
                 number system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "590--596",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/EURMIC.1994.390354",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Although the `diagonal function' of a Residue Number
                 System has been recently introduced as a powerful tool
                 to perform non modular operations, its implementation
                 is generally realized using an additional modulus
                 external to the set of system moduli. \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Dimauro:1994:DFNb
author: G. Dimauro and S. Impedovo and G. Pirlo
booktitle: EUROMICRO 94. System Architecture and Integration. Proceedings of the 20th EUROMICRO Conference
title: The `diagonal function' in non-redundant residue number system
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 590--596
year: 1994
DOI: https://doi.org/10.1109/EURMIC.1994.390354
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: G. Dimauro and S. Impedovo and G. Pirlo
rawbooktitle: {EUROMICRO 94}. System Architecture and Integration. Proceedings of the 20th {EUROMICRO} Conference
rawtitle: The `diagonal function' in non-redundant residue number system
entry:
@InProceedings{Dimauro:1994:DFNb,
  author =       "G. Dimauro and S. Impedovo and G. Pirlo",
  booktitle =    "{EUROMICRO 94}. System Architecture and Integration.
                 Proceedings of the 20th {EUROMICRO} Conference",
  title =        "The `diagonal function' in non-redundant residue
                 number system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "590--596",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/EURMIC.1994.390354",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Although the `diagonal function' of a Residue Number
                 System has been recently introduced as a powerful tool
                 to perform non modular operations, its implementation
                 is generally realized using an additional modulus
                 external to the set of system moduli. \ldots{}",
}


bibtype: misc
filename: fparith.bib
label: Edelman:1994:W
author: Alan Edelman
title: When is $ x star (1 / x) neq 1 $ ?
pages: 590--596
day: 7
month: dec
monthnumber: 12
year: 1994
bibdate: Wed Aug 07 15:04:56 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.07 15:04:56 ???
URL: https://math.mit.edu/~edelman/homepage/papers/ieee.pdf
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: Alan Edelman
rawtitle: When is $ x \star (1 / x) \neq 1 $ ?
entry:
@Misc{Edelman:1994:W,
  author =       "Alan Edelman",
  title =        "When is $ x \star (1 / x) \neq 1 $ ?",
  howpublished = "Web document",
  day =          "7",
  month =        dec,
  year =         "1994",
  bibdate =      "Wed Aug 07 15:04:56 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://math.mit.edu/~edelman/homepage/papers/ieee.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: Ercegovac:1994:DSR
author: Milos D. (Dragutin) Ercegovac and Tomas Lang
title: Division and square root: digit-recurrence algorithms and implementations
publisher: pub-KLUWER
address: pub-KLUWER:adr
pages: x + 230
year: 1994
ISBN: 0-7923-9438-0 OR 0792394380
ISBN13: 978-0-7923-9438-9 OR 9780792394389
LCCN: QA76.9.C62 E73 1994
bibdate: Fri Mar 27 09:46:24 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.03.27 09:46:24 ???
acknowledgement: ack-nhfb
rawauthor: Milo{\v{s}} D. (Dragutin) Ercegovac and Tomas Lang
rawtitle: Division and square root: digit-recurrence algorithms and implementations
entry:
@Book{Ercegovac:1994:DSR,
  author =       "Milo{\v{s}} D. (Dragutin) Ercegovac and Tomas Lang",
  title =        "Division and square root: digit-recurrence algorithms
                 and implementations",
  publisher =    pub-KLUWER,
  address =      pub-KLUWER:adr,
  pages =        "x + 230",
  year =         "1994",
  ISBN =         "0-7923-9438-0",
  ISBN-13 =      "978-0-7923-9438-9",
  LCCN =         "QA76.9.C62 E73 1994",
  bibdate =      "Fri Mar 27 09:46:24 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Ercegovac:1994:VHR
author: M. D. Ercegovac and T. Lang and P. Montuschi
title: Very-High Radix Division with Prescaling and Selection by Rounding
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 909--918
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295853
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:57 MDT 2011
bibtimestamp: 2011.07.07 07:13:57 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295853
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-sfo
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. D. Ercegovac and T. Lang and P. Montuschi
rawtitle: Very-High Radix Division with Prescaling and Selection by Rounding
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib; OCLC Proceedings database

entry:
@Article{Ercegovac:1994:VHR,
  author =       "M. D. Ercegovac and T. Lang and P. Montuschi",
  title =        "Very-High Radix Division with Prescaling and Selection
                 by Rounding",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "909--918",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295853",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:57 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295853",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
  summary =      "A division algorithm in which the quotient-digit
                 selection is performed by rounding the shifted residual
                 in carry-save form is presented. To allow the use of
                 this simple function, the divisor (and dividend) is
                 prescaled to a range close to one. The \ldots{}",
  xxtitle =      "Very high radix division with selection by rounding
                 and prescaling",
}


bibtype: article
filename: fparith.bib
label: Fagin:1994:FPG
author: B. Fagin and C. Renard
title: Field Programmable Gate Arrays and Floating Point Arithmetic
journal: j-IEEE-TRANS-VLSI-SYST
volume: 2
number: 3
pages: 365--367
month: sep
monthnumber: 9
year: 1994
CODEN: IEVSE9
DOI: https://doi.org/10.1109/92.311646
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, US Air Force Acad., Colorado Springs, CO, USA
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: B. Fagin and C. Renard
rawtitle: Field Programmable Gate Arrays and Floating Point Arithmetic
abstract:
We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA's permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. PPGA's also permit accurate assessments of the area and time costs associated with various features of the IEEE floating-point standard, including rounding and gradual underflow. These costs are analyzed, along with the effects of architectural correlation, a phenomenon that occurs when the cost of combining architectural features exceeds the sum of separate implementation. We conclude with an assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic.

keywords:
Addition; Architectural correlation; Area costs; Field programmable gate arrays; Floating point arithmetic; Floating-point adder; Floating-point multiplier; FPGA; IEEE Standard 754 compliance; Multiplication; Time costs

thesaurus:
Adders; Application specific integrated circuits; Digital arithmetic; Logic arrays; Multiplying circuits

rawabstract:
We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA's permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. PPGA's also permit accurate assessments of the area and time costs associated with various features of the IEEE floating-point standard, including rounding and gradual underflow. These costs are analyzed, along with the effects of architectural correlation, a phenomenon that occurs when the cost of combining architectural features exceeds the sum of separate implementation. We conclude with an assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic.

entry:
@Article{Fagin:1994:FPG,
  author =       "B. Fagin and C. Renard",
  title =        "Field Programmable Gate Arrays and Floating Point
                 Arithmetic",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "2",
  number =       "3",
  pages =        "365--367",
  month =        sep,
  year =         "1994",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/92.311646",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present empirical results describing the
                 implementation of an IEEE Standard 754 compliant
                 floating-point adder/multiplier using field
                 programmable gate arrays. The use of FPGA's permits
                 fast and accurate quantitative evaluation of a variety
                 of circuit design tradeoffs for addition and
                 multiplication. PPGA's also permit accurate assessments
                 of the area and time costs associated with various
                 features of the IEEE floating-point standard, including
                 rounding and gradual underflow. These costs are
                 analyzed, along with the effects of architectural
                 correlation, a phenomenon that occurs when the cost of
                 combining architectural features exceeds the sum of
                 separate implementation. We conclude with an assessment
                 of the strengths and weaknesses of using FPGA's for
                 floating-point arithmetic.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, US Air Force Acad.,
                 Colorado Springs, CO, USA",
  classification = "B1265B (Logic circuits); B2570 (Semiconductor
                 integrated circuits); C5120 (Logic and switching
                 circuits); C5230 (Digital arithmetic methods)",
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
  keywords =     "Addition; Architectural correlation; Area costs; Field
                 programmable gate arrays; Floating point arithmetic;
                 Floating-point adder; Floating-point multiplier; FPGA;
                 IEEE Standard 754 compliance; Multiplication; Time
                 costs",
  summary =      "We present empirical results describing the
                 implementation of an IEEE Standard 754 compliant
                 floating-point adder/multiplier using field
                 programmable gate arrays. The use of FPGA's permits
                 fast and accurate quantitative evaluation of a variety
                 of \ldots{}",
  thesaurus =    "Adders; Application specific integrated circuits;
                 Digital arithmetic; Logic arrays; Multiplying
                 circuits",
}


bibtype: book
filename: fparith.bib
label: Farquhar:1994:MPH
author: Erin Farquhar and Philip Bruce
title: The MIPS Programmer's Handbook
publisher: pub-MORGAN-KAUFMANN
address: pub-MORGAN-KAUFMANN:adr
pages: viii + 408
year: 1994
ISBN: 1-55860-297-6 OR 1558602976
ISBN13: 978-1-55860-297-7 OR 9781558602977
LCCN: QA76.6 .F375 1994
bibdate: Fri May 13 18:21:14 1994
bibtimestamp: 1994.05.13 18:21:14 ???
acknowledgement: ack-nhfb
rawauthor: Erin Farquhar and Philip Bruce
rawtitle: The {MIPS} Programmer's Handbook
abstract:
A hands-on view of the highly successful MIPS family of microprocessors, written for programmers developing systems applications for the MIPS platform. The MIPS Programmer's Handbook describes the MIPS architecture from the perspective of assembly- and C-language programmers, with special emphasis on issues related to embedded applications. Engineers writing system-level programs for MIPS-based embedded systems will find the topic selection especially useful including the sections on software conventions, initializing the processor in a bare machine environment, and writing exception handlers. For convenient use, the instruction set reference is presented with only one page per instruction. The authors focus on the instructions available to assembly-language programmers, rather than on the hardware-level instruction set documented in data books released by vendors of the MIPS processor. Provides enough detail for anyone doing serious system-level programming. Also included are ten complete program examples, with line-by-line explanations.

TOC:
1: Introduction 2: Software Conventions 3: Initialization 4: Exceptions 5: Instruction Set Reference A: Overview of the MIPS1 Architecture B: Instruction Summary C: Prologue and Epilogue Templates D: Include Files E: Libraries F: Vendors of MIPS Products

rawabstract:
A hands-on view of the highly successful MIPS family of microprocessors, written for programmers developing systems applications for the MIPS platform. The MIPS Programmer's Handbook describes the MIPS architecture from the perspective of assembly- and C-language programmers, with special emphasis on issues related to embedded applications. Engineers writing system-level programs for MIPS-based embedded systems will find the topic selection especially useful including the sections on software conventions, initializing the processor in a bare machine environment, and writing exception handlers. For convenient use, the instruction set reference is presented with only one page per instruction. The authors focus on the instructions available to assembly-language programmers, rather than on the hardware-level instruction set documented in data books released by vendors of the MIPS processor. Provides enough detail for anyone doing serious system-level programming. Also included are ten complete program examples, with line-by-line explanations.

rawTOC:
1: Introduction \\ 2: Software Conventions \\ 3: Initialization \\ 4: Exceptions \\ 5: Instruction Set Reference \\ A: Overview of the MIPS1 Architecture \\ B: Instruction Summary \\ C: Prologue and Epilogue Templates \\ D: Include Files \\ E: Libraries \\ F: Vendors of MIPS Products

entry:
@Book{Farquhar:1994:MPH,
  author =       "Erin Farquhar and Philip Bruce",
  title =        "The {MIPS} Programmer's Handbook",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  pages =        "viii + 408",
  year =         "1994",
  ISBN =         "1-55860-297-6",
  ISBN-13 =      "978-1-55860-297-7",
  LCCN =         "QA76.6 .F375 1994",
  bibdate =      "Fri May 13 18:21:14 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 https://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$36.95",
  abstract =     "A hands-on view of the highly successful MIPS family
                 of microprocessors, written for programmers developing
                 systems applications for the MIPS platform. The MIPS
                 Programmer's Handbook describes the MIPS architecture
                 from the perspective of assembly- and C-language
                 programmers, with special emphasis on issues related to
                 embedded applications. Engineers writing system-level
                 programs for MIPS-based embedded systems will find the
                 topic selection especially useful including the
                 sections on software conventions, initializing the
                 processor in a bare machine environment, and writing
                 exception handlers. For convenient use, the instruction
                 set reference is presented with only one page per
                 instruction. The authors focus on the instructions
                 available to assembly-language programmers, rather than
                 on the hardware-level instruction set documented in
                 data books released by vendors of the MIPS processor.
                 Provides enough detail for anyone doing serious
                 system-level programming. Also included are ten
                 complete program examples, with line-by-line
                 explanations.",
  acknowledgement = ack-nhfb,
  libnote =      "Not yet in my library.",
  tableofcontents = "1: Introduction \\
                 2: Software Conventions \\
                 3: Initialization \\
                 4: Exceptions \\
                 5: Instruction Set Reference \\
                 A: Overview of the MIPS1 Architecture \\
                 B: Instruction Summary \\
                 C: Prologue and Epilogue Templates \\
                 D: Include Files \\
                 E: Libraries \\
                 F: Vendors of MIPS Products",
}


bibtype: inproceedings
filename: fparith.bib
label: FiallosAguilar:1994:HPA
author: M. Fiallos-Aguilar
title: High precision arithmetic units for fine-grain massively parallel computing
crossref: IEEE:1994:PFI
pages: 403--407
year: 1994
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
acknowledgement: ack-nhfb
affiliation: Lab. LIP-IMAG, Ecole Normale Superieure de Lyon, France
thesaurus: Digital arithmetic; Parallel architectures; Pipeline arithmetic
rawauthor: M. Fiallos-Aguilar
rawtitle: High precision arithmetic units for fine-grain massively parallel computing
abstract:
In this paper we deal with new high precision arithmetic units (AUs). These AUs are specialized in the computation of one arithmetic operation (division, addition, etc.), but when hundreds of them are interconnected by a reconfigurable network, a parallel architecture that uses massive digit-level pipelining between floating-point arithmetic units (allowing fast computation of scientific jobs) becomes interesting. In this paper we present several new AUs for the fast computation of arithmetic expressions that will be used on a high precision massively parallel computer. (6 Refs.)

keywords:
Arithmetic units; Fine-grain; Floating-point arithmetic units; High precision; Massively parallel computing; Parallel architecture

rawabstract:
In this paper we deal with new high precision arithmetic units (AUs). These AUs are specialized in the computation of one arithmetic operation (division, addition, etc.), but when hundreds of them are interconnected by a reconfigurable network, a parallel architecture that uses massive digit-level pipelining between floating-point arithmetic units (allowing fast computation of scientific jobs) becomes interesting. In this paper we present several new AUs for the fast computation of arithmetic expressions that will be used on a high precision massively parallel computer. (6 Refs.)

entry:
@InProceedings{FiallosAguilar:1994:HPA,
  author =       "M. Fiallos-Aguilar",
  title =        "High precision arithmetic units for fine-grain
                 massively parallel computing",
  crossref =     "IEEE:1994:PFI",
  pages =        "403--407",
  year =         "1994",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper we deal with new high precision
                 arithmetic units (AUs). These AUs are specialized in
                 the computation of one arithmetic operation (division,
                 addition, etc.), but when hundreds of them are
                 interconnected by a reconfigurable network, a parallel
                 architecture that uses massive digit-level pipelining
                 between floating-point arithmetic units (allowing fast
                 computation of scientific jobs) becomes interesting. In
                 this paper we present several new AUs for the fast
                 computation of arithmetic expressions that will be used
                 on a high precision massively parallel computer. (6
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Lab. LIP-IMAG, Ecole Normale Superieure de Lyon,
                 France",
  classification = "C5220P (Parallel architecture); C5230 (Digital
                 arithmetic methods)",
  keywords =     "Arithmetic units; Fine-grain; Floating-point
                 arithmetic units; High precision; Massively parallel
                 computing; Parallel architecture",
  thesaurus =    "Digital arithmetic; Parallel architectures; Pipeline
                 arithmetic",
}


bibtype: article
filename: fparith.bib
label: Gander:1994:AFP
author: H. Gander and M. Vincze and J. P. Prenninger
title: Application of a Floating Point Digital Signal Processor to the Control of a Laser Tracking System
journal: j-IEEE-TRANS-CONTROL-SYST-TECHNOL
volume: 2
number: 4
pages: 290--298
month: dec
monthnumber: 12
year: 1994
CODEN: IETTE2
ISSN: 1063-6536 (print), 1558-0865 (electronic) OR 10636536 (print), 15580865 (electronic)
ISSNL: 1063-6536 OR 10636536
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Control Systems Technology
acknowledgement: ack-nhfb
rawauthor: H. Gander and M. Vincze and J. P. Prenninger
rawtitle: Application of a Floating Point Digital Signal Processor to the Control of a Laser Tracking System
entry:
@Article{Gander:1994:AFP,
  author =       "H. Gander and M. Vincze and J. P. Prenninger",
  title =        "Application of a Floating Point Digital Signal
                 Processor to the Control of a Laser Tracking System",
  journal =      j-IEEE-TRANS-CONTROL-SYST-TECHNOL,
  volume =       "2",
  number =       "4",
  pages =        "290--298",
  month =        dec,
  year =         "1994",
  CODEN =        "IETTE2",
  ISSN =         "1063-6536 (print), 1558-0865 (electronic)",
  ISSN-L =       "1063-6536",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Control Systems Technology",
  summary =      "Laser tracking systems represent the most promising
                 technique for dynamic position measurement of
                 industrial robots. The Institute of Flexible Automation
                 at the Vienna University of Technology a new tracking
                 algorithm has been developed. It is shown \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Gerber:1994:DPH
author: S. Gerber and M. Goessel
title: Detection of permanent hardware faults of a floating point adder by pseudoduplication
crossref: Echtle:1994:PFI
pages: 327--335
year: 1994
DOI: https://doi.org/10.1007/3-540-58426-9_139
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
acknowledgement: ack-nhfb
affiliation: Max-Planck-Society Fault-Tolerant Comput. Group, Potsdam University, Germany
thesaurus: Adders; Digital simulation; Fault location; Floating point arithmetic; Logic CAD; Logic testing
rawauthor: S. Gerber and M. Goessel
rawtitle: Detection of permanent hardware faults of a floating point adder by pseudoduplication
abstract:
In this paper the detection of hardware faults by pseudoduplication for a special floating point adder is investigated. For a special floating point adder all single stuck-at-0/1 faults are injected. In a first simulation experiment for random input patterns all the faults are determined which can be detected by pseudoduplication. In a second experiment for sequences of random input vectors with different length the probability to detect an arbitrary single fault is determined.

keywords:
Arbitrary single fault; Floating point adder; Permanent hardware faults; Probability; Pseudoduplication; Random input patterns; Stuck at faults

rawabstract:
In this paper the detection of hardware faults by pseudoduplication for a special floating point adder is investigated. For a special floating point adder all single stuck-at-0/1 faults are injected. In a first simulation experiment for random input patterns all the faults are determined which can be detected by pseudoduplication. In a second experiment for sequences of random input vectors with different length the probability to detect an arbitrary single fault is determined.

entry:
@InProceedings{Gerber:1994:DPH,
  author =       "S. Gerber and M. Goessel",
  title =        "Detection of permanent hardware faults of a floating
                 point adder by pseudoduplication",
  crossref =     "Echtle:1994:PFI",
  pages =        "327--335",
  year =         "1994",
  DOI =          "https://doi.org/10.1007/3-540-58426-9_139",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper the detection of hardware faults by
                 pseudoduplication for a special floating point adder is
                 investigated. For a special floating point adder all
                 single stuck-at-0/1 faults are injected. In a first
                 simulation experiment for random input patterns all the
                 faults are determined which can be detected by
                 pseudoduplication. In a second experiment for sequences
                 of random input vectors with different length the
                 probability to detect an arbitrary single fault is
                 determined.",
  acknowledgement = ack-nhfb,
  affiliation =  "Max-Planck-Society Fault-Tolerant Comput. Group,
                 Potsdam University, Germany",
  classification = "B1130B (Computer-aided circuit analysis and design);
                 B1265B (Logic circuits); C5120 (Logic and switching
                 circuits); C5210B (Computer-aided logic design); C7410D
                 (Electronic engineering computing)",
  keywords =     "Arbitrary single fault; Floating point adder;
                 Permanent hardware faults; Probability;
                 Pseudoduplication; Random input patterns; Stuck at
                 faults",
  thesaurus =    "Adders; Digital simulation; Fault location; Floating
                 point arithmetic; Logic CAD; Logic testing",
}


bibtype: article
filename: fparith.bib
label: Granlund:1994:DII
author: Torbjorn Granlund and Peter L. Montgomery
title: Division by invariant integers using multiplication
journal: j-SIGPLAN
volume: 29
number: 6
pages: 61--72
month: jun
monthnumber: 6
year: 1994
CODEN: SINODQ
DOI: https://doi.org/10.1145/178243.178249
ISBN: 0-89791-598-4 OR 0897915984
ISBN13: 978-0-89791-598-4 OR 9780897915984
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:16:51 MST 2003
bibtimestamp: 2003.12.14 09:16:51 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliation: Cygnus Support, Mountain View, CA, USA
annote: Published as part of the Proceedings of PLDI'94.
corpsource: Cygnus Support, Mountain View, CA, USA
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
treatment: T Theoretical or Mathematical
rawauthor: Torbj{\"o}rn Granlund and Peter L. Montgomery
rawtitle: Division by invariant integers using multiplication
bibsource:
http://portal.acm.org/; http://www.acm.org/pubs/contents/proceedings/pldi/178243/index.html; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
ftp://ftp.cwi.nl/pub/pmontgom/divcnst.psa4.gz; ftp://ftp.cwi.nl/pub/pmontgom/divcnst.psl.gz; http://www.acm.org:80/pubs/citations/proceedings/pldi/178243/p61-granlund/

abstract:
Integer division remains expensive on today's processors as the cost of integer multiplication declines. We present code sequences for division by arbitrary nonzero integer constants and run-time invariants using integer multiplication. The algorithms assume a two's complement architecture. Most also require that the upper half of an integer product be quickly accessible. We treat unsigned division, signed division where the quotient rounds towards zero, signed division where the quotient rounds towards $ - infty $, and division where the result is known a priori to be exact. We give some implementation results using the C compiler GCC.

keywords:
algorithms; Arbitrary nonzero integer constants; arbitrary nonzero integer constants; C compiler; Code sequences; code sequences; digital arithmetic; Floating point arithmetic; floating point arithmetic; GCC; Integer division; integer division; Integer multiplication; integer multiplication; Invariant integers; invariant integers; mathematics computing; Multiplication; multiplication; performance; program; program compilers; programming; reduced instruction set computing; RISC processors; Run-time invariants; run-time invariants; Signed division; signed division; Two's complement architecture; two's complement architecture; Unsigned division; unsigned division

subject:
bf G.1.0 Mathematics of Computing, NUMERICAL ANALYSIS, General, Computer arithmetic. bf F.2.1 Theory of Computation, ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY, Numerical Algorithms and Problems. bf D.3.4 Software, PROGRAMMING LANGUAGES, Processors, Compilers.

thesaurus:
Digital arithmetic; Mathematics computing; Program compilers; Programming; Reduced instruction set computing

rawabstract:
Integer division remains expensive on today's processors as the cost of integer multiplication declines. We present code sequences for division by arbitrary nonzero integer constants and run-time invariants using integer multiplication. The algorithms assume a two's complement architecture. Most also require that the upper half of an integer product be quickly accessible. We treat unsigned division, signed division where the quotient rounds towards zero, signed division where the quotient rounds towards $ - \infty $, and division where the result is known a priori to be exact. We give some implementation results using the C compiler GCC.

entry:
@Article{Granlund:1994:DII,
  author =       "Torbj{\"o}rn Granlund and Peter L. Montgomery",
  title =        "Division by invariant integers using multiplication",
  journal =      j-SIGPLAN,
  volume =       "29",
  number =       "6",
  pages =        "61--72",
  month =        jun,
  year =         "1994",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/178243.178249",
  ISBN =         "0-89791-598-4",
  ISBN-13 =      "978-0-89791-598-4",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:51 MST 2003",
  bibsource =    "http://portal.acm.org/;
                 http://www.acm.org/pubs/contents/proceedings/pldi/178243/index.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://ftp.cwi.nl/pub/pmontgom/divcnst.psa4.gz;
                 ftp://ftp.cwi.nl/pub/pmontgom/divcnst.psl.gz;
                 http://www.acm.org:80/pubs/citations/proceedings/pldi/178243/p61-granlund/",
  abstract =     "Integer division remains expensive on today's
                 processors as the cost of integer multiplication
                 declines. We present code sequences for division by
                 arbitrary nonzero integer constants and run-time
                 invariants using integer multiplication. The algorithms
                 assume a two's complement architecture. Most also
                 require that the upper half of an integer product be
                 quickly accessible. We treat unsigned division, signed
                 division where the quotient rounds towards zero, signed
                 division where the quotient rounds towards $ - \infty
                 $, and division where the result is known a priori to
                 be exact. We give some implementation results using the
                 C compiler GCC.",
  acknowledgement = ack-nhfb,
  affiliation =  "Cygnus Support, Mountain View, CA, USA",
  annote =       "Published as part of the Proceedings of PLDI'94.",
  classification = "C5230 (Digital arithmetic methods); C6110 (Systems
                 analysis and programming); C6150C (Compilers,
                 interpreters and other processors)",
  confdate =     "20-24 June 1994",
  conflocation = "Orlando, FL, USA",
  confsponsor =  "ACM",
  conftitle =    "ACM SIGPLAN '94 Conference on Programming Language
                 Design and Implementation (PLDI)",
  corpsource =   "Cygnus Support, Mountain View, CA, USA",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "algorithms; Arbitrary nonzero integer constants;
                 arbitrary nonzero integer constants; C compiler; Code
                 sequences; code sequences; digital arithmetic; Floating
                 point arithmetic; floating point arithmetic; GCC;
                 Integer division; integer division; Integer
                 multiplication; integer multiplication; Invariant
                 integers; invariant integers; mathematics computing;
                 Multiplication; multiplication; performance; program;
                 program compilers; programming; reduced instruction set
                 computing; RISC processors; Run-time invariants;
                 run-time invariants; Signed division; signed division;
                 Two's complement architecture; two's complement
                 architecture; Unsigned division; unsigned division",
  sponsororg =   "ACM",
  subject =      "{\bf G.1.0} Mathematics of Computing, NUMERICAL
                 ANALYSIS, General, Computer arithmetic. {\bf F.2.1}
                 Theory of Computation, ANALYSIS OF ALGORITHMS AND
                 PROBLEM COMPLEXITY, Numerical Algorithms and Problems.
                 {\bf D.3.4} Software, PROGRAMMING LANGUAGES,
                 Processors, Compilers.",
  thesaurus =    "Digital arithmetic; Mathematics computing; Program
                 compilers; Programming; Reduced instruction set
                 computing",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: article
filename: fparith.bib
label: Grosse:1994:IRS
author: Eric Grosse and John D. Hobby
title: Improved rounding for spline coefficients and knots
journal: j-MATH-COMPUT
volume: 63
number: 207
pages: 175--194
month: jul
monthnumber: 7
year: 1994
CODEN: MCMPAF
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
MRclass: 65D07
MRnumber: 94j:65019
bibdate: Tue Mar 25 15:38:13 MST 1997
bibtimestamp: 1997.03.25 15:38:13 MST
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
affiliation: Comput. Sci. Res., AT&T Bell Labs., Murray Hill, NJ, USA
ajournal: Math. Comput.
corpsource: Comput. Sci. Res., AT&T Bell Labs., Murray Hill, NJ, USA
journalURL: http://www.ams.org/mcom/
treatment: T Theoretical or Mathematical
rawauthor: Eric Grosse and John D. Hobby
rawtitle: Improved rounding for spline coefficients and knots
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp1990.bib

keywords:
affine model; algorithm; error; error analysis; infinite-precision value; knot; knots; Lovasz basis reduction; optimal full-precision free-; parameterized spline; quadratic error model; rounding; roundoff errors; spline coefficients; splines (mathematics)

classcodes:
B0290F (Interpolation and function approximation); B0290B (Error analysis in numerical methods); C4130 (Interpolation and function approximation); C4110 (Error analysis in numerical methods)

entry:
@Article{Grosse:1994:IRS,
  author =       "Eric Grosse and John D. Hobby",
  title =        "Improved rounding for spline coefficients and knots",
  journal =      j-MATH-COMPUT,
  volume =       "63",
  number =       "207",
  pages =        "175--194",
  month =        jul,
  year =         "1994",
  CODEN =        "MCMPAF",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  MRclass =      "65D07",
  MRnumber =     "94j:65019",
  bibdate =      "Tue Mar 25 15:38:13 MST 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp1990.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Comput. Sci. Res., AT\&T Bell Labs., Murray Hill, NJ,
                 USA",
  ajournal =     "Math. Comput.",
  classcodes =   "B0290F (Interpolation and function approximation);
                 B0290B (Error analysis in numerical methods); C4130
                 (Interpolation and function approximation); C4110
                 (Error analysis in numerical methods)",
  corpsource =   "Comput. Sci. Res., AT\&T Bell Labs., Murray Hill, NJ,
                 USA",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
  keywords =     "affine model; algorithm; error; error analysis;
                 infinite-precision value; knot; knots; Lovasz basis
                 reduction; optimal full-precision free-; parameterized
                 spline; quadratic error model; rounding; roundoff
                 errors; spline coefficients; splines (mathematics)",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: article
filename: fparith.bib
label: Hahn:1994:UDF
author: H. Hahn and D. Timmermann and B. J. Hosticka and B. Rix
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 11
pages: 1339--1344
month: nov
monthnumber: 11
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.324568
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:58 MDT 2011
bibtimestamp: 2011.07.07 07:13:58 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=324568
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Hahn and D. Timmermann and B. J. Hosticka and B. Rix
title:
A unified and division-free CORDIC argument reduction method with unlimited convergence domain including inverse hyperbolic functions

rawtitle:
A unified and division-free {CORDIC} argument reduction method with unlimited convergence domain including inverse hyperbolic functions

entry:
@Article{Hahn:1994:UDF,
  author =       "H. Hahn and D. Timmermann and B. J. Hosticka and B.
                 Rix",
  title =        "A unified and division-free {CORDIC} argument
                 reduction method with unlimited convergence domain
                 including inverse hyperbolic functions",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "11",
  pages =        "1339--1344",
  month =        nov,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.324568",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:58 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=324568",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Hartwig:1994:FPA
author: F. Hartwig and A. Lacroix
booktitle: IEEE International Symposium on Circuits and Systems: ISCAS '94, 2 June 1994
title: Floating point addition errors and their effect on the roundoff noise in digital signal processing
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 121--124
year: 1994
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: F. Hartwig and A. Lacroix
rawbooktitle: {IEEE} International Symposium on Circuits and Systems: {ISCAS '94}, 2 June 1994
rawtitle: Floating point addition errors and their effect on the roundoff noise in digital signal processing
entry:
@InProceedings{Hartwig:1994:FPA,
  author =       "F. Hartwig and A. Lacroix",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems: {ISCAS '94}, 2 June 1994",
  title =        "Floating point addition errors and their effect on the
                 roundoff noise in digital signal processing",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "121--124",
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "An improved adder model is derived which takes into
                 account correlations between signal and error. For
                 different adder strategies is shown the influence of
                 the improved adder model on the estimated of the
                 resulting \ldots{}",
}


bibtype: mastersthesis
filename: fparith.bib
label: Hauser:1994:PEH
author: John R. Hauser
title: Programmed exception handling: research project
type: Master of Science, Plan II
school: Department of Computer Science, University of California, Berkeley
address: Berkeley, CA, USA
pages: 82
year: 1994
LCCN: T7.49.1994 H286
bibdate: Mon Feb 18 12:39:53 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.02.18 12:39:53 ???
acknowledgement: ack-nhfb
rawauthor: John R. Hauser
rawtitle: Programmed exception handling: research project
entry:
@MastersThesis{Hauser:1994:PEH,
  author =       "John R. Hauser",
  title =        "Programmed exception handling: research project",
  type =         "{Master of Science, Plan II}",
  school =       "Department of Computer Science, University of
                 California, Berkeley",
  address =      "Berkeley, CA, USA",
  pages =        "82",
  year =         "1994",
  LCCN =         "T7.49.1994 H286",
  bibdate =      "Mon Feb 18 12:39:53 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Hegland:1994:SSP
author: Markus Hegland
journal: j-NUM-MATH
volume: 68
number: 4
pages: 507--547
year: 1994
CODEN: NUMMA7
ISSN: 0029-599X (print), 0945-3245 (electronic) OR 0029599X (print), 09453245 (electronic)
ISSNL: 0029-599X OR 0029599X
MRclass: 65T20 (65Y05)
MRnumber: 96e:65082
bibdate: Mon May 26 11:49:34 MDT 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.05.26 11:49:34 MDT
fjournal: Numerische Mathematik
acknowledgement: ack-nhfb
corpsource: Centre for Math. Anal. and its Applications, Australian Nat. University, Canberra, ACT, Australia
journalURL: http://link.springer.com/journal/211
treatment: A Application; P Practical; T Theoretical or Mathematical
rawauthor: Markus Hegland
title:
A self-sorting in-place fast Fourier transform algorithm suitable for vector and parallel processing

keywords:
data analysis; distributed memory computers; fast Fourier transforms; floating point pipelines; Fujitsu VP2200; index digit permutations; mathematics computing; matrix recursions; parallel processing; self-sorting in-place fast Fourier transform algorithm; splitting formulas; uniformly long vector lengths; vector processing; vector processor systems

rawtitle:
A self-sorting in-place fast {Fourier} transform algorithm suitable for vector and parallel processing

entry:
@Article{Hegland:1994:SSP,
  author =       "Markus Hegland",
  title =        "A self-sorting in-place fast {Fourier} transform
                 algorithm suitable for vector and parallel processing",
  journal =      j-NUM-MATH,
  volume =       "68",
  number =       "4",
  pages =        "507--547",
  year =         "1994",
  CODEN =        "NUMMA7",
  ISSN =         "0029-599X (print), 0945-3245 (electronic)",
  ISSN-L =       "0029-599X",
  MRclass =      "65T20 (65Y05)",
  MRnumber =     "96e:65082",
  bibdate =      "Mon May 26 11:49:34 MDT 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "B0290Z (Other numerical methods); C4190 (Other
                 numerical methods); C5220P (Parallel architecture);
                 C5440 (Multiprocessing systems); C7310 (Mathematics
                 computing)",
  corpsource =   "Centre for Math. Anal. and its Applications,
                 Australian Nat. University, Canberra, ACT, Australia",
  fjournal =     "Numerische Mathematik",
  journal-URL =  "http://link.springer.com/journal/211",
  keywords =     "data analysis; distributed memory computers; fast
                 Fourier transforms; floating point pipelines; Fujitsu
                 VP2200; index digit permutations; mathematics
                 computing; matrix recursions; parallel processing;
                 self-sorting in-place fast Fourier transform algorithm;
                 splitting formulas; uniformly long vector lengths;
                 vector processing; vector processor systems",
  treatment =    "A Application; P Practical; T Theoretical or
                 Mathematical",
}


bibtype: article
filename: fparith.bib
label: Hemkumar:1994:RLC
author: N. D. Hemkumar and J. R. Cavallaro
title: Redundant and On-Line CORDIC for Unitary Transformations
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 941--954
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295856
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:16:49 MDT
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: N. D. Hemkumar and J. R. Cavallaro
rawtitle: Redundant and On-Line {CORDIC} for Unitary Transformations
entry:
@Article{Hemkumar:1994:RLC,
  author =       "N. D. Hemkumar and J. R. Cavallaro",
  title =        "Redundant and On-Line {CORDIC} for Unitary
                 Transformations",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "941--954",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295856",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: article
filename: fparith.bib
label: Hester:1994:PPP
author: P. D. Hester and W. J. Filip
title: Preface: Power2 and PowerPC Architecture and Implementation
journal: j-IBM-JRD
volume: 38
number: 5
pages: 490--491
month: sep
monthnumber: 9
year: 1994
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Mon Feb 12 08:14:00 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.02.12 08:14:00 ???
URL: http://www.almaden.ibm.com/journal/rd38-5.html#one
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawauthor: P. D. Hester and W. J. Filip
rawtitle: Preface: {Power2} and {PowerPC} Architecture and Implementation
abstract:
During the four years since the RISC System / 6000* (RS / 6000) announcement in February of 1990, IBM* has strengthened its product line with microprocessor enhancements, increased memory capacity, improved graphics, greatly expanded I/O adapters, and new AIX* and compiler releases. In 1991, IBM began planning for future RS / 6000 systems that would span the range from small, battery-operated products to very large supercomputers and mainframes. As the first step toward achieving this ``palmtop to teraFLOPS'' goal with a single architecture, IBM investigated further optimizations for the original POWER Architecture*. This effort led to the creation of the PowerPC* alliance (IBM Corporation, Motorola*, Inc., and Apple* Computer Corporation) and the definition of the PowerPC Architecture*. Today, the single-chip PowerPC 601* processor is the basis of IBM's entry systems. A more aggressively superscalar version of the original POWER processor, the multichip POWER2* processor, is exploited in our current IBM high-end RISC systems. As technology continues to advance, PowerPC implementations will provide the basis for high-performance 64-bit super servers. This special issue of the IBM Journal of Research and Development focuses on the POWER2 and PowerPC portions of IBM's wide-ranging announcement in the Fall of 1993. The new POWER2 processor nearly doubles the performance of the earlier high-end models. The PowerPC 601 processor was introduced in the RISC System / 6000 Model 250, the first system in the industry to use the PowerPC Architecture created by the strategic IBM/Motorola/Apple alliance. These workstations achieved industry-leading performance and price/performance on virtually every industry-standard benchmark, including SPECint92*, SPECfp92*, Linpack, TPP, TPC-A*, and TPC-C*. Compared to the 1990 offerings, SPEC performance nearly quadrupled, transaction performance improved by a factor of almost five, maximum memory capacity quadrupled, and the maximum disk capacity grew by an order of magnitude. The POWER2 design exploits both multichip technology and a larger die size to execute up to six instructions (eight operations) per clock cycle. Many of the higher-performance POWER2-based systems provide peak execution rates in excess of a half billion operations per second. The paper by White and Dhawan provides an overview of the POWER2 design. Shippy and Griffith describe the dual fixed-point unit design, the data cache unit, and the storage control unit. Hicks, Fry, and Harvey describe the dual floating-point unit design. Barreh et al. describe hardware strategies to minimize compare-branch penalties in the instruction cache unit. Welbon et al. describe a POWER2 hardware performance- monitoring facility which provides execution characteristics that can identify opportunities for application performance improvement. This facility can also be used to gather information crucial to future design decisions. Two performance papers conclude the POWER2 portion of this issue. Franklin et al. analyze some of the key POWER2 hardware contributions to performance on the commercial workloads. Agarwal, Gustavson, and Zubair relate their experiences with optimizing the high-performance Engineering/Scientific Subroutine Library (ESSL) for the POWER2 implementation. While POWER2 and PowerPC implementations provide the opportunity for high-performance systems, optimizing software is also key in delivering end-user performance. Blainey describes aspects of the TOBEY compiler, with special emphasis on instruction scheduling for the RS / 6000 products. Heisch describes TDPR, a prototype version of FDPR, a program restructuring tool which improves application performance by placing frequently executed code blocks so as to minimize instruction cache misses and branch penalties. IBM and the PowerPC alliance are currently developing a family of five PowerPC designs. IBM and Motorola designers at the Somerset Design Center in Austin will optimize single-chip implementations of the PowerPC Architecture for high-volume products. The high-end requirements of the large server and workstation products will be addressed with multichip PowerPC implementations from IBM.par IBM entry-level workstation products introduced the PowerPC 601 microprocessor, the first member of the PowerPC family. The goal for the PowerPC 601 designers was to quickly bring PowerPC to the market. Vaden et al. describe the microarchitecture and performance aspects of the PowerPC 601 processor. Brodnax et al. discuss the PowerPC 601 circuitry and chip implementation details. Future products are planned that will incorporate the PowerPC 603*, PowerPC 604*, and the 64-bit PowerPC 620* implementations as they become available. In addition, the price and price/performance of the PowerPC family enable lower-cost ``RISC PCs'' to be built using PowerPC microprocessors. These ``RISC PCs'' will be developed by the IBM POWER Personal Systems Division.par The PowerPC and POWER2 systems signify a major milestone in IBM's commitment to the ``palmtops to teraFLOPS'' strategy. The PowerPC 601 chip extends the entry products further into the high-volume market by providing exceptional performance in a low-cost single-chip microprocessor. The high-end POWER2 implementation extracts the maximum performance achievable in today's technology, thrusting the IBM RISC processors into the supercomputing and large-server environments. IBM POWER Parallel Systems extends the RS / 6000 processing capability by providing IBM POWER Parallel SP2* systems with up to 512 POWER/POWER2 nodes. In addition to scalability, four-way High Availability Cluster Multi-Processor (HACMP) systems provide the reliability/availability that one would expect from mainframe-class systems by supporting a ``no single point of failure'' capability, even when one processor is off line. This impressive base of processing technology complements a commitment to high-performance compilers and strong graphics offerings.par This robust product line addresses the cost-driven requirements of the entry workstation market, the transaction and server requirements of the commercial market, and the computation-intensive requirements of the technical market. These hardware offerings result from a team effort by many dedicated and talented individuals from around the world. Their expertise and skill in a wide range of disciplines were key to achieving this significant step toward the goal of a comprehensive architecture. We want to thank all those involved in continuing the success of the RISC System / 6000 line.

rawabstract:
During the four years since the RISC System\slash 6000* (RS\slash 6000) announcement in February of 1990, IBM* has strengthened its product line with microprocessor enhancements, increased memory capacity, improved graphics, greatly expanded I/O adapters, and new AIX* and compiler releases. In 1991, IBM began planning for future RS\slash 6000 systems that would span the range from small, battery-operated products to very large supercomputers and mainframes. As the first step toward achieving this ``palmtop to teraFLOPS'' goal with a single architecture, IBM investigated further optimizations for the original POWER Architecture*. This effort led to the creation of the PowerPC* alliance (IBM Corporation, Motorola*, Inc., and Apple* Computer Corporation) and the definition of the PowerPC Architecture*. Today, the single-chip PowerPC 601* processor is the basis of IBM's entry systems. A more aggressively superscalar version of the original POWER processor, the multichip POWER2* processor, is exploited in our current IBM high-end RISC systems. As technology continues to advance, PowerPC implementations will provide the basis for high-performance 64-bit super servers. This special issue of the IBM Journal of Research and Development focuses on the POWER2 and PowerPC portions of IBM's wide-ranging announcement in the Fall of 1993. The new POWER2 processor nearly doubles the performance of the earlier high-end models. The PowerPC 601 processor was introduced in the RISC System\slash 6000 Model 250, the first system in the industry to use the PowerPC Architecture created by the strategic IBM/Motorola/Apple alliance. These workstations achieved industry-leading performance and price/performance on virtually every industry-standard benchmark, including SPECint92*, SPECfp92*, Linpack, TPP, TPC-A*, and TPC-C*. Compared to the 1990 offerings, SPEC performance nearly quadrupled, transaction performance improved by a factor of almost five, maximum memory capacity quadrupled, and the maximum disk capacity grew by an order of magnitude. The POWER2 design exploits both multichip technology and a larger die size to execute up to six instructions (eight operations) per clock cycle. Many of the higher-performance POWER2-based systems provide peak execution rates in excess of a half billion operations per second. The paper by White and Dhawan provides an overview of the POWER2 design. Shippy and Griffith describe the dual fixed-point unit design, the data cache unit, and the storage control unit. Hicks, Fry, and Harvey describe the dual floating-point unit design. Barreh et al. describe hardware strategies to minimize compare-branch penalties in the instruction cache unit. Welbon et al. describe a POWER2 hardware performance- monitoring facility which provides execution characteristics that can identify opportunities for application performance improvement. This facility can also be used to gather information crucial to future design decisions. Two performance papers conclude the POWER2 portion of this issue. Franklin et al. analyze some of the key POWER2 hardware contributions to performance on the commercial workloads. Agarwal, Gustavson, and Zubair relate their experiences with optimizing the high-performance Engineering/Scientific Subroutine Library (ESSL) for the POWER2 implementation. While POWER2 and PowerPC implementations provide the opportunity for high-performance systems, optimizing software is also key in delivering end-user performance. Blainey describes aspects of the TOBEY compiler, with special emphasis on instruction scheduling for the RS\slash 6000 products. Heisch describes TDPR, a prototype version of FDPR, a program restructuring tool which improves application performance by placing frequently executed code blocks so as to minimize instruction cache misses and branch penalties. IBM and the PowerPC alliance are currently developing a family of five PowerPC designs. IBM and Motorola designers at the Somerset Design Center in Austin will optimize single-chip implementations of the PowerPC Architecture for high-volume products. The high-end requirements of the large server and workstation products will be addressed with multichip PowerPC implementations from IBM.\par IBM entry-level workstation products introduced the PowerPC 601 microprocessor, the first member of the PowerPC family. The goal for the PowerPC 601 designers was to quickly bring PowerPC to the market. Vaden et al. describe the microarchitecture and performance aspects of the PowerPC 601 processor. Brodnax et al. discuss the PowerPC 601 circuitry and chip implementation details. Future products are planned that will incorporate the PowerPC 603*, PowerPC 604*, and the 64-bit PowerPC 620* implementations as they become available. In addition, the price and price/performance of the PowerPC family enable lower-cost ``RISC PCs'' to be built using PowerPC microprocessors. These ``RISC PCs'' will be developed by the IBM POWER Personal Systems Division.\par The PowerPC and POWER2 systems signify a major milestone in IBM's commitment to the ``palmtops to teraFLOPS'' strategy. The PowerPC 601 chip extends the entry products further into the high-volume market by providing exceptional performance in a low-cost single-chip microprocessor. The high-end POWER2 implementation extracts the maximum performance achievable in today's technology, thrusting the IBM RISC processors into the supercomputing and large-server environments. IBM POWER Parallel Systems extends the RS\slash 6000 processing capability by providing IBM POWER Parallel SP2* systems with up to 512 POWER/POWER2 nodes. In addition to scalability, four-way High Availability Cluster Multi-Processor (HACMP) systems provide the reliability/availability that one would expect from mainframe-class systems by supporting a ``no single point of failure'' capability, even when one processor is off line. This impressive base of processing technology complements a commitment to high-performance compilers and strong graphics offerings.\par This robust product line addresses the cost-driven requirements of the entry workstation market, the transaction and server requirements of the commercial market, and the computation-intensive requirements of the technical market. These hardware offerings result from a team effort by many dedicated and talented individuals from around the world. Their expertise and skill in a wide range of disciplines were key to achieving this significant step toward the goal of a comprehensive architecture. We want to thank all those involved in continuing the success of the RISC System\slash 6000 line.

entry:
@Article{Hester:1994:PPP,
  author =       "P. D. Hester and W. J. Filip",
  title =        "Preface: {Power2} and {PowerPC} Architecture and
                 Implementation",
  journal =      j-IBM-JRD,
  volume =       "38",
  number =       "5",
  pages =        "490--491",
  month =        sep,
  year =         "1994",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Mon Feb 12 08:14:00 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.almaden.ibm.com/journal/rd38-5.html#one",
  abstract =     "During the four years since the RISC System\slash
                 6000* (RS\slash 6000) announcement in February of 1990,
                 IBM* has strengthened its product line with
                 microprocessor enhancements, increased memory capacity,
                 improved graphics, greatly expanded I/O adapters, and
                 new AIX* and compiler releases. In 1991, IBM began
                 planning for future RS\slash 6000 systems that would
                 span the range from small, battery-operated products to
                 very large supercomputers and mainframes. As the first
                 step toward achieving this ``palmtop to teraFLOPS''
                 goal with a single architecture, IBM investigated
                 further optimizations for the original POWER
                 Architecture*. This effort led to the creation of the
                 PowerPC* alliance (IBM Corporation, Motorola*, Inc.,
                 and Apple* Computer Corporation) and the definition of
                 the PowerPC Architecture*. Today, the single-chip
                 PowerPC 601* processor is the basis of IBM's entry
                 systems. A more aggressively superscalar version of the
                 original POWER processor, the multichip POWER2*
                 processor, is exploited in our current IBM high-end
                 RISC systems. As technology continues to advance,
                 PowerPC implementations will provide the basis for
                 high-performance 64-bit super servers. This special
                 issue of the IBM Journal of Research and Development
                 focuses on the POWER2 and PowerPC portions of IBM's
                 wide-ranging announcement in the Fall of 1993. The new
                 POWER2 processor nearly doubles the performance of the
                 earlier high-end models. The PowerPC 601 processor was
                 introduced in the RISC System\slash 6000 Model 250, the
                 first system in the industry to use the PowerPC
                 Architecture created by the strategic
                 IBM/Motorola/Apple alliance. These workstations
                 achieved industry-leading performance and
                 price/performance on virtually every industry-standard
                 benchmark, including SPECint92*, SPECfp92*, Linpack,
                 TPP, TPC-A*, and TPC-C*. Compared to the 1990
                 offerings, SPEC performance nearly quadrupled,
                 transaction performance improved by a factor of almost
                 five, maximum memory capacity quadrupled, and the
                 maximum disk capacity grew by an order of magnitude.
                 The POWER2 design exploits both multichip technology
                 and a larger die size to execute up to six instructions
                 (eight operations) per clock cycle. Many of the
                 higher-performance POWER2-based systems provide peak
                 execution rates in excess of a half billion operations
                 per second. The paper by White and Dhawan provides an
                 overview of the POWER2 design. Shippy and Griffith
                 describe the dual fixed-point unit design, the data
                 cache unit, and the storage control unit. Hicks, Fry,
                 and Harvey describe the dual floating-point unit
                 design. Barreh et al. describe hardware strategies to
                 minimize compare-branch penalties in the instruction
                 cache unit. Welbon et al. describe a POWER2 hardware
                 performance- monitoring facility which provides
                 execution characteristics that can identify
                 opportunities for application performance improvement.
                 This facility can also be used to gather information
                 crucial to future design decisions. Two performance
                 papers conclude the POWER2 portion of this issue.
                 Franklin et al. analyze some of the key POWER2 hardware
                 contributions to performance on the commercial
                 workloads. Agarwal, Gustavson, and Zubair relate their
                 experiences with optimizing the high-performance
                 Engineering/Scientific Subroutine Library (ESSL) for
                 the POWER2 implementation. While POWER2 and PowerPC
                 implementations provide the opportunity for
                 high-performance systems, optimizing software is also
                 key in delivering end-user performance. Blainey
                 describes aspects of the TOBEY compiler, with special
                 emphasis on instruction scheduling for the RS\slash
                 6000 products. Heisch describes TDPR, a prototype
                 version of FDPR, a program restructuring tool which
                 improves application performance by placing frequently
                 executed code blocks so as to minimize instruction
                 cache misses and branch penalties. IBM and the PowerPC
                 alliance are currently developing a family of five
                 PowerPC designs. IBM and Motorola designers at the
                 Somerset Design Center in Austin will optimize
                 single-chip implementations of the PowerPC Architecture
                 for high-volume products. The high-end requirements of
                 the large server and workstation products will be
                 addressed with multichip PowerPC implementations from
                 IBM.\par

                 IBM entry-level workstation products introduced the
                 PowerPC 601 microprocessor, the first member of the
                 PowerPC family. The goal for the PowerPC 601 designers
                 was to quickly bring PowerPC to the market. Vaden et
                 al. describe the microarchitecture and performance
                 aspects of the PowerPC 601 processor. Brodnax et al.
                 discuss the PowerPC 601 circuitry and chip
                 implementation details. Future products are planned
                 that will incorporate the PowerPC 603*, PowerPC 604*,
                 and the 64-bit PowerPC 620* implementations as they
                 become available. In addition, the price and
                 price/performance of the PowerPC family enable
                 lower-cost ``RISC PCs'' to be built using PowerPC
                 microprocessors. These ``RISC PCs'' will be developed
                 by the IBM POWER Personal Systems Division.\par

                 The PowerPC and POWER2 systems signify a major
                 milestone in IBM's commitment to the ``palmtops to
                 teraFLOPS'' strategy. The PowerPC 601 chip extends the
                 entry products further into the high-volume market by
                 providing exceptional performance in a low-cost
                 single-chip microprocessor. The high-end POWER2
                 implementation extracts the maximum performance
                 achievable in today's technology, thrusting the IBM
                 RISC processors into the supercomputing and
                 large-server environments. IBM POWER Parallel Systems
                 extends the RS\slash 6000 processing capability by
                 providing IBM POWER Parallel SP2* systems with up to
                 512 POWER/POWER2 nodes. In addition to scalability,
                 four-way High Availability Cluster Multi-Processor
                 (HACMP) systems provide the reliability/availability
                 that one would expect from mainframe-class systems by
                 supporting a ``no single point of failure'' capability,
                 even when one processor is off line. This impressive
                 base of processing technology complements a commitment
                 to high-performance compilers and strong graphics
                 offerings.\par

                 This robust product line addresses the cost-driven
                 requirements of the entry workstation market, the
                 transaction and server requirements of the commercial
                 market, and the computation-intensive requirements of
                 the technical market. These hardware offerings result
                 from a team effort by many dedicated and talented
                 individuals from around the world. Their expertise and
                 skill in a wide range of disciplines were key to
                 achieving this significant step toward the goal of a
                 comprehensive architecture. We want to thank all those
                 involved in continuing the success of the RISC
                 System\slash 6000 line.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
}


bibtype: article
filename: fparith.bib
label: Hicks:1994:PFU
author: T. N. Hicks and R. E. Fry and P. E. Harvey
title: POWER2 floating-point unit: Architecture and implementation
journal: j-IBM-JRD
volume: 38
number: 5
pages: 525--536
month: sep
monthnumber: 9
year: 1994
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
affiliation: IBM Corp., Austin, TX, USA
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawauthor: T. N. Hicks and R. E. Fry and P. E. Harvey
rawtitle: {POWER2} floating-point unit: Architecture and implementation
abstract:
The POWER2 floating-point unit (FPU) extends the concept of the innovative multiply-add fused (MAF) ALU of the RISC System/6000 processor to provide a floating-point unit that sets new standards, not only for computation capability but for data throughput and processor flexibility. The POWERS FPU achieves a performance (MFLOPS) rate never accomplished before by a personal workstation machine by: (1) integrating dual generic MAF ALUs, (2) doubling the instruction bandwidth and quadrupling the data bandwidth over that of the POWER FPU, (3) adding support for additional functions, and (4) using dynamic instruction scheduling techniques to maximize instruction-level parallelism not only among its own internal units but with the rest of the CPU.

keywords:
Data bandwidth; Dynamic instruction scheduling; Floating-point unit; Instruction bandwidth; Instruction-level parallelism; Multiply add fused arithmetic logic unit; POWER2; RISC System/6000 processor

thesaurus:
Floating point arithmetic; Microprocessor chips; Parallel architectures; Parallel processing; Reduced instruction set computing

rawabstract:
The POWER2 floating-point unit (FPU) extends the concept of the innovative multiply-add fused (MAF) ALU of the RISC System/6000 processor to provide a floating-point unit that sets new standards, not only for computation capability but for data throughput and processor flexibility. The POWERS FPU achieves a performance (MFLOPS) rate never accomplished before by a personal workstation machine by: (1) integrating dual generic MAF ALUs, (2) doubling the instruction bandwidth and quadrupling the data bandwidth over that of the POWER FPU, (3) adding support for additional functions, and (4) using dynamic instruction scheduling techniques to maximize instruction-level parallelism not only among its own internal units but with the rest of the CPU.

entry:
@Article{Hicks:1994:PFU,
  author =       "T. N. Hicks and R. E. Fry and P. E. Harvey",
  title =        "{POWER2} floating-point unit: Architecture and
                 implementation",
  journal =      j-IBM-JRD,
  volume =       "38",
  number =       "5",
  pages =        "525--536",
  month =        sep,
  year =         "1994",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The POWER2 floating-point unit (FPU) extends the
                 concept of the innovative multiply-add fused (MAF) ALU
                 of the RISC System/6000 processor to provide a
                 floating-point unit that sets new standards, not only
                 for computation capability but for data throughput and
                 processor flexibility. The POWERS FPU achieves a
                 performance (MFLOPS) rate never accomplished before by
                 a personal workstation machine by: (1) integrating dual
                 generic MAF ALUs, (2) doubling the instruction
                 bandwidth and quadrupling the data bandwidth over that
                 of the POWER FPU, (3) adding support for additional
                 functions, and (4) using dynamic instruction scheduling
                 techniques to maximize instruction-level parallelism
                 not only among its own internal units but with the rest
                 of the CPU.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Austin, TX, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220P (Parallel architecture);
                 C5230 (Digital arithmetic methods)",
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "Data bandwidth; Dynamic instruction scheduling;
                 Floating-point unit; Instruction bandwidth;
                 Instruction-level parallelism; Multiply add fused
                 arithmetic logic unit; POWER2; RISC System/6000
                 processor",
  thesaurus =    "Floating point arithmetic; Microprocessor chips;
                 Parallel architectures; Parallel processing; Reduced
                 instruction set computing",
}


bibtype: inproceedings
filename: fparith.bib
label: Hilker:1994:NMM
author: S. Hilker and N. Phan and D. Rainey
title: A 3.4 ns 0.8 mu m BiCMOS 53*53 b multiplier tree
crossref: Wuorinen:1994:IIS
pages: 292--293
year: 1994
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
acknowledgement: ack-nhfb
affiliation: IBM Corp., Rochester, MN, USA
rawauthor: S. Hilker and N. Phan and D. Rainey
rawtitle: A 3.4 ns 0.8 mu m {BiCMOS} 53*53 b multiplier tree
abstract:
A 53*53 b multiplier tree with 3.4 ns latency, 10 mm/sup 2/ active area, and 5 W power dissipation at 200 MHz and 3.6 V supply is implemented in 0.8 mu m n-well BiCMOS with 115 AA gate oxide, 0.45 mu m effective channel length, and 4 levels of metal. This 3.4ns low-latency multiplier is for a floating-point unit (FPU) on a BiCMOS RISC processor capable of performing IEEE double precision multiply-add operations in three pipelined stages at 200MHz (15ns latency, 5ns throughput, 400MFLOPs peak rate) using multiply-add fused dataflow.

keywords:
0.8 Micron; 200 MHz; 3.4 Ns; 3.6 V; 400 MFLOPS; 5 W; Effective channel length; Floating-point unit; IEEE double precision multiply-add operations; Latency; Multiplier tree; Multiply-add fused dataflow; N-well BiCMOS; Pipelined stages; Power dissipation; RISC processor

thesaurus:
BiCMOS integrated circuits; Digital arithmetic; Multiplying circuits; Parallel processing; Pipeline processing; Reduced instruction set computing

rawabstract:
A 53*53 b multiplier tree with 3.4 ns latency, 10 mm/sup 2/ active area, and 5 W power dissipation at 200 MHz and 3.6 V supply is implemented in 0.8 mu m n-well BiCMOS with 115 AA gate oxide, 0.45 mu m effective channel length, and 4 levels of metal. This 3.4ns low-latency multiplier is for a floating-point unit (FPU) on a BiCMOS RISC processor capable of performing IEEE double precision multiply-add operations in three pipelined stages at 200MHz (15ns latency, 5ns throughput, 400MFLOPs peak rate) using multiply-add fused dataflow.

entry:
@InProceedings{Hilker:1994:NMM,
  author =       "S. Hilker and N. Phan and D. Rainey",
  title =        "A 3.4 ns 0.8 mu m {BiCMOS} 53*53 b multiplier tree",
  crossref =     "Wuorinen:1994:IIS",
  pages =        "292--293",
  year =         "1994",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 53*53 b multiplier tree with 3.4 ns latency, 10
                 mm/sup 2/ active area, and 5 W power dissipation at 200
                 MHz and 3.6 V supply is implemented in 0.8 mu m n-well
                 BiCMOS with 115 AA gate oxide, 0.45 mu m effective
                 channel length, and 4 levels of metal. This 3.4ns
                 low-latency multiplier is for a floating-point unit
                 (FPU) on a BiCMOS RISC processor capable of performing
                 IEEE double precision multiply-add operations in three
                 pipelined stages at 200MHz (15ns latency, 5ns
                 throughput, 400MFLOPs peak rate) using multiply-add
                 fused dataflow.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Rochester, MN, USA",
  classification = "B1265B (Logic circuits); B2570K (Mixed technology
                 integrated circuits); C5120 (Logic and switching
                 circuits); C5220P (Parallel architecture); C5230
                 (Digital arithmetic methods)",
  keywords =     "0.8 Micron; 200 MHz; 3.4 Ns; 3.6 V; 400 MFLOPS; 5 W;
                 Effective channel length; Floating-point unit; IEEE
                 double precision multiply-add operations; Latency;
                 Multiplier tree; Multiply-add fused dataflow; N-well
                 BiCMOS; Pipelined stages; Power dissipation; RISC
                 processor",
  numericalindex = "Time 3.4E-09 s; Size 8.0E-07 m; Power 5.0E+00 W;
                 Frequency 2.0E+08 Hz; Voltage 3.6E+00 V; Computer speed
                 4.0E+08 FLOPS",
  thesaurus =    "BiCMOS integrated circuits; Digital arithmetic;
                 Multiplying circuits; Parallel processing; Pipeline
                 processing; Reduced instruction set computing",
}


bibtype: book
filename: fparith.bib
label: Hill:1994:GPL
author: Patricia Hill
title: The Godel Programming Language
publisher: pub-MIT
address: pub-MIT:adr
pages: xx + 348
year: 1994
ISBN: 0-262-08229-2 OR 0262082292
ISBN13: 978-0-262-08229-7 OR 9780262082297
LCCN: QA76.73.G17H55 1994
bibdate: Thu Sep 15 07:47:50 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.15 07:47:50 ???
acknowledgement: ack-nhfb
rawauthor: Patricia Hill
rawtitle: The {G{\"o}del} Programming Language
note:
Section 13.3 (pp. 206--218) defines floating-point numbers and standard functions conforming to Version 4.0 (August 1992) of the Language Independent Arithmetic Standard (LIAS) ISO / IEC CD 10967-1:1992 (JTC1/SC22/WG11 N318, ANSI X3T3 92-064). It also conforms to the ANSI / IEEE Standard for Binary Floating-Point Arithmetic 754-1985.

rawnote:
Section 13.3 (pp. 206--218) defines floating-point numbers and standard functions conforming to Version 4.0 (August 1992) of the Language Independent Arithmetic Standard (LIAS) ISO\slash IEC CD 10967-1:1992 (JTC1/SC22/WG11 N318, ANSI X3T3 92-064). It also conforms to the ANSI\slash IEEE Standard for Binary Floating-Point Arithmetic 754-1985.

entry:
@Book{Hill:1994:GPL,
  author =       "Patricia Hill",
  title =        "The {G{\"o}del} Programming Language",
  publisher =    pub-MIT,
  address =      pub-MIT:adr,
  pages =        "xx + 348",
  year =         "1994",
  ISBN =         "0-262-08229-2",
  ISBN-13 =      "978-0-262-08229-7",
  LCCN =         "QA76.73.G17H55 1994",
  bibdate =      "Thu Sep 15 07:47:50 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Section 13.3 (pp. 206--218) defines floating-point
                 numbers and standard functions conforming to Version
                 4.0 (August 1992) of the Language Independent
                 Arithmetic Standard (LIAS) ISO\slash IEC CD
                 10967-1:1992 (JTC1/SC22/WG11 N318, ANSI X3T3 92-064).
                 It also conforms to the ANSI\slash IEEE Standard for
                 Binary Floating-Point Arithmetic 754-1985.",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Hopkins:1994:CEM
author: Tim Hopkins and John Slater
title: A Comment on the Eispack Machine Epsilon Routine
type: Technical Report
number: 18-94
institution: University of Kent, Computing Laboratory, University of Kent
address: Canterbury, UK
pages: xx + 348
year: 1994
bibdate: Tue Apr 12 12:00:52 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.12 12:00:52 ???
URL: http://www.cs.kent.ac.uk/pubs/1994/74/content.ps.gz
acknowledgement: ack-nhfb
rawauthor: Tim Hopkins and John Slater
rawtitle: A Comment on the {Eispack} Machine Epsilon Routine
entry:
@TechReport{Hopkins:1994:CEM,
  author =       "Tim Hopkins and John Slater",
  title =        "A Comment on the {Eispack} Machine Epsilon Routine",
  type =         "Technical Report",
  number =       "18-94",
  institution =  "University of Kent, Computing Laboratory, University
                 of Kent",
  address =      "Canterbury, UK",
  year =         "1994",
  bibdate =      "Tue Apr 12 12:00:52 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.kent.ac.uk/pubs/1994/74/content.ps.gz",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Horvath:1994:PPM
author: Tamas Horvath and Spyros S. Magliveras and Tran van Trung
title: A Parallel Permutation Multiplier for a PGM Crypto-Chip
journal: j-LECT-NOTES-COMP-SCI
volume: 839
pages: 108--113
year: 1994
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Feb 5 11:49:18 MST 2002
bibtimestamp: 2002.02.05 11:49:18 MST
fjournal: Lecture Notes in Computer Science
keywords: CRYPTO; cryptology; IACR; IEEE
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Tam{\'a}s Horv{\'a}th and Spyros S. Magliveras and Tran van Trung
rawtitle: A Parallel Permutation Multiplier for a {PGM} Crypto-Chip
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t0839.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/0839/08390108.htm; http://link.springer-ny.com/link/service/series/0558/papers/0839/08390108.pdf

entry:
@Article{Horvath:1994:PPM,
  author =       "Tam{\'a}s Horv{\'a}th and Spyros S. Magliveras and
                 Tran van Trung",
  title =        "A Parallel Permutation Multiplier for a {PGM}
                 Crypto-Chip",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "839",
  pages =        "108--113",
  year =         "1994",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Feb 5 11:49:18 MST 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t0839.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/0839/08390108.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/0839/08390108.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  keywords =     "CRYPTO; cryptology; IACR; IEEE",
}


bibtype: article
filename: fparith.bib
label: Hsu:1994:CPF
author: Chau-Yun Hsu and Jui Chi Yao
title: Comparative performance of fast cosine transform with fixed-point roundoff error analysis
journal: j-IEEE-TRANS-SIG-PROC
volume: 42
number: 5
pages: 1256--1259
month: may
monthnumber: 5
year: 1994
CODEN: ITPRED
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Sat Jul 16 11:25:06 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:06 MDT
fjournal: IEEE Transactions on Signal Processing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: Chau-Yun Hsu and Jui Chi Yao
rawtitle: Comparative performance of fast cosine transform with fixed-point roundoff error analysis
entry:
@Article{Hsu:1994:CPF,
  author =       "Chau-Yun Hsu and Jui Chi Yao",
  title =        "Comparative performance of fast cosine transform with
                 fixed-point roundoff error analysis",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "42",
  number =       "5",
  pages =        "1256--1259",
  month =        may,
  year =         "1994",
  CODEN =        "ITPRED",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Sat Jul 16 11:25:06 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  summary =      "Suitable scaling schemes are chosen for the Lee's and
                 the Hou's (1984) fast DCT algorithms, and the relative
                 fixed-point roundoff error analyses are carried out,
                 respectively. The average output signal-to-noise ratio
                 are then calculated, and it is \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Hsu:1994:NFP
author: Chau-Yun Hsu
title: Novel fixed-point roundoff analysis of the decimation-in-time FHT
journal: j-IEEE-TRANS-SIG-PROC
volume: 42
number: 1
pages: 206--208
month: jan
monthnumber: 1
year: 1994
CODEN: ITPRED
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Sat Jul 16 11:25:06 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:06 MDT
fjournal: IEEE Transactions on Signal Processing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: Chau-Yun Hsu
rawtitle: Novel fixed-point roundoff analysis of the decimation-in-time {FHT}
entry:
@Article{Hsu:1994:NFP,
  author =       "Chau-Yun Hsu",
  title =        "Novel fixed-point roundoff analysis of the
                 decimation-in-time {FHT}",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "42",
  number =       "1",
  pages =        "206--208",
  month =        jan,
  year =         "1994",
  CODEN =        "ITPRED",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Sat Jul 16 11:25:06 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  summary =      "A least upper bound for the increasing factor of the
                 magnitude of the decimation-in-time fast Hartley
                 transform (FHT) in fixed-point arithmetic is developed
                 and a new scaling model for the roundoff analysis in
                 the fixed-point arithmetic computation \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Hull:1994:ICE
author: T. E. Hull and Thomas F. Fairgrieve and Ping Tak Peter Tang
title: Implementing Complex Elementary Functions Using Exception Handling
journal: j-TOMS
volume: 20
number: 2
pages: 215--244
month: jun
monthnumber: 6
year: 1994
CODEN: ACMSCU
DOI: https://doi.org/10.1145/178365.178404
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Tue Mar 21 15:10:29 1995
bibtimestamp: 1995.03.21 15:10:29 ???
URL: http://www.acm.org/pubs/citations/journals/toms/1994-20-2/p215-hull/
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: algorithms; complex elementary functions; design; implementation
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/toms
rawauthor: T. E. Hull and Thomas F. Fairgrieve and Ping Tak Peter Tang
rawtitle: Implementing Complex Elementary Functions Using Exception Handling
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

note:
See correction cite Anonymous:1994:C, and improved analysis, tightened bounds, and exhibition of worst cases for complex square roots cite Jeannerod:2017:REC.

abstract:
Algorithms are developed for reliable and accurate evaluations of the complex elementary functions required in Fortran 77 and Fortran 90, namely cabs, csqrt, cexp, clog, csin, and ccos. The algorithms are presented in a pseudocode that has a convenient exception-handling facility. A tight error bound is derived for each algorithm. Corresponding Fortran programs for an IEEE environment have also been developed to illustrate the practicality of the algorithms, and these programs have been tested very carefully to help confirm the correctness of the algorithms and their error bounds. The results are of these tests are included in the paper, but the Fortran programs are not; the programs are available from Fairgrieve, (tff@cs.toronto.edu).

subject:
G.1.0 [Numerical Analysis]: General--error analysis; numerical algorithms; G.1.2 [Numerical Analysis]: Approximation--elementary function approximation; G.4 [Mathematics of Computing]: Mathematical Software--algorithm analysis; reliability and robustness; verification

rawabstract:
Algorithms are developed for reliable and accurate evaluations of the complex elementary functions required in Fortran 77 and Fortran 90, namely cabs, csqrt, cexp, clog, csin, and ccos. The algorithms are presented in a pseudocode that has a convenient exception-handling facility. A tight error bound is derived for each algorithm. Corresponding Fortran programs for an IEEE environment have also been developed to illustrate the practicality of the algorithms, and these programs have been tested very carefully to help confirm the correctness of the algorithms and their error bounds. The results are of these tests are included in the paper, but the Fortran programs are not; the programs are available from Fairgrieve, (tff@cs.toronto.edu).

rawnote:
See correction \cite{Anonymous:1994:C}, and improved analysis, tightened bounds, and exhibition of worst cases for complex square roots \cite{Jeannerod:2017:REC}.

entry:
@Article{Hull:1994:ICE,
  author =       "T. E. Hull and Thomas F. Fairgrieve and Ping Tak Peter
                 Tang",
  title =        "Implementing Complex Elementary Functions Using
                 Exception Handling",
  journal =      j-TOMS,
  volume =       "20",
  number =       "2",
  pages =        "215--244",
  month =        jun,
  year =         "1994",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/178365.178404",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Tue Mar 21 15:10:29 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  note =         "See correction \cite{Anonymous:1994:C}, and improved
                 analysis, tightened bounds, and exhibition of worst
                 cases for complex square roots
                 \cite{Jeannerod:2017:REC}.",
  URL =          "http://www.acm.org/pubs/citations/journals/toms/1994-20-2/p215-hull/",
  abstract =     "Algorithms are developed for reliable and accurate
                 evaluations of the complex elementary functions
                 required in Fortran 77 and Fortran 90, namely cabs,
                 csqrt, cexp, clog, csin, and ccos. The algorithms are
                 presented in a pseudocode that has a convenient
                 exception-handling facility. A tight error bound is
                 derived for each algorithm. Corresponding Fortran
                 programs for an IEEE environment have also been
                 developed to illustrate the practicality of the
                 algorithms, and these programs have been tested very
                 carefully to help confirm the correctness of the
                 algorithms and their error bounds. The results are of
                 these tests are included in the paper, but the Fortran
                 programs are not; the programs are available from
                 Fairgrieve, (tff@cs.toronto.edu).",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "algorithms; complex elementary functions; design;
                 implementation",
  subject =      "G.1.0 [Numerical Analysis]: General--error analysis;
                 numerical algorithms; G.1.2 [Numerical Analysis]:
                 Approximation--elementary function approximation; G.4
                 [Mathematics of Computing]: Mathematical
                 Software--algorithm analysis; reliability and
                 robustness; verification",
}


bibtype: article
filename: fparith.bib
label: Hung:1994:ASD
author: C. Y. Hung and B. Parhami
title: An approximate sign detection method for residue numbers and its application to RNS division
journal: j-COMPUT-MATH-APPL
volume: 27
number: 4
pages: 23--35
month: feb
monthnumber: 2
year: 1994
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 19:11:19 MST 2017
bibtimestamp: 2017.03.01 19:11:19 MST
URL: http://www.sciencedirect.com/science/article/pii/0898122194900523
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: C. Y. Hung and B. Parhami
rawtitle: An approximate sign detection method for residue numbers and its application to {RNS} division
entry:
@Article{Hung:1994:ASD,
  author =       "C. Y. Hung and B. Parhami",
  title =        "An approximate sign detection method for residue
                 numbers and its application to {RNS} division",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "27",
  number =       "4",
  pages =        "23--35",
  month =        feb,
  year =         "1994",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 19:11:19 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl1990.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/0898122194900523",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: article
filename: fparith.bib
label: Hung:1994:FRD
author: Ching Yu Hung and Behrooz Parhami
title: Fast RNS division algorithms for fixed divisors with application to RSA encryption
journal: j-INFO-PROC-LETT
volume: 51
number: 4
pages: 163--169
day: 24
month: aug
monthnumber: 8
year: 1994
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
MRclass: 94A60
MRnumber: 1 294 308
bibdate: Fri Oct 25 18:39:09 2002
bibtimestamp: 2002.10.25 18:39:09 ???
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
affiliation: Univ of California
affiliationaddress: Santa Barbara, CA, USA
corpsource: Department of Electr. and Comput. Eng., California University, Santa Barbara, CA, USA
journalURL: http://www.sciencedirect.com/science/journal/00200190
journalabr: Inf Process Lett
treatment: A Application; T Theoretical or Mathematical
rawauthor: Ching Yu Hung and Behrooz Parhami
rawtitle: Fast {RNS} division algorithms for fixed divisors with application to {RSA} encryption
bibsource:
Compendex database; http://www.elsevier.com:80/inca/publications/store/5/0/5/6/1/2/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/infoproc.bib; MathSciNet database

keywords:
Algorithms; Chinese remainder theorem; Chinese remainder theorem decoding and table lookup; Computational complexity; computational complexity; Computational complexity; Computational methods; Computer software; Cryptography; cryptography; Cryptography; Decoding; Digital arithmetic; digital arithmetic; Digital arithmetic; Division; divisor reciprocal; Exponentiation; fast RNS division algorithms; fixed divisors; Fixed divisors; Function evaluation; mathematics computing; Modular multiplication; multiplication; Numbering systems; on-line speed; ordinary integer division; Parallel processing systems; preprocessing; Residue number system; Residue processors; RSA encryption; Sign detection; Table lookup; Time complexity; time complexity; Time complexity

entry:
@Article{Hung:1994:FRD,
  author =       "Ching Yu Hung and Behrooz Parhami",
  title =        "Fast {RNS} division algorithms for fixed divisors with
                 application to {RSA} encryption",
  journal =      j-INFO-PROC-LETT,
  volume =       "51",
  number =       "4",
  pages =        "163--169",
  day =          "24",
  month =        aug,
  year =         "1994",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  MRclass =      "94A60",
  MRnumber =     "1 294 308",
  bibdate =      "Fri Oct 25 18:39:09 2002",
  bibsource =    "Compendex database;
                 http://www.elsevier.com:80/inca/publications/store/5/0/5/6/1/2/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/infoproc.bib;
                 MathSciNet database",
  acknowledgement = ack-nhfb,
  affiliation =  "Univ of California",
  affiliationaddress = "Santa Barbara, CA, USA",
  classification = "722.4; 723.1; 723.2; 921.6; C4240 (Programming and
                 algorithm theory)C6130S (Data security); C7310
                 (Mathematics)",
  corpsource =   "Department of Electr. and Comput. Eng., California
                 University, Santa Barbara, CA, USA",
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
  journalabr =   "Inf Process Lett",
  keywords =     "Algorithms; Chinese remainder theorem; Chinese
                 remainder theorem decoding and table lookup;
                 Computational complexity; computational complexity;
                 Computational complexity; Computational methods;
                 Computer software; Cryptography; cryptography;
                 Cryptography; Decoding; Digital arithmetic; digital
                 arithmetic; Digital arithmetic; Division; divisor
                 reciprocal; Exponentiation; fast RNS division
                 algorithms; fixed divisors; Fixed divisors; Function
                 evaluation; mathematics computing; Modular
                 multiplication; multiplication; Numbering systems;
                 on-line speed; ordinary integer division; Parallel
                 processing systems; preprocessing; Residue number
                 system; Residue processors; RSA encryption; Sign
                 detection; Table lookup; Time complexity; time
                 complexity; Time complexity",
  treatment =    "A Application; T Theoretical or Mathematical",
}


bibtype: book
filename: fparith.bib
label: IBM:1994:IRS
editor: Steve White and John Reysa
title: IBM RISC System / 6000 Technology: Volume II
publisher: pub-IBM
address: pub-IBM:adr
pages: 163--169
year: 1994
bibdate: Fri Mar 18 10:25:19 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.03.18 10:25:19 ???
acknowledgement: ack-nhfb
raweditor: Steve White and John Reysa
rawtitle: {IBM RISC} System\slash 6000 Technology: Volume {II}
note:
A partial draft is available via anonymous ftp to path |ibminet.awdpa.ibm.com| in the PostScript file path |/pub/rs6kpapers/techbook.ps|.

rawnote:
A partial draft is available via anonymous ftp to \path|ibminet.awdpa.ibm.com| in the PostScript file \path|/pub/rs6kpapers/techbook.ps|.

entry:
@Book{IBM:1994:IRS,
  editor =       "Steve White and John Reysa",
  title =        "{IBM RISC} System\slash 6000 Technology: Volume {II}",
  publisher =    pub-IBM,
  address =      pub-IBM:adr,
  year =         "1994",
  bibdate =      "Fri Mar 18 10:25:19 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "A partial draft is available via anonymous ftp to
                 \path|ibminet.awdpa.ibm.com| in the PostScript file
                 \path|/pub/rs6kpapers/techbook.ps|.",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: IBM:1994:OA
author: IBM Corporation
title: The PowerPC Architecture: a Specification for a New Family of RISC Processors
publisher: pub-MORGAN-KAUFMANN
address: pub-MORGAN-KAUFMANN:adr
edition: Second
pages: xxxi + 518
year: 1994
ISBN: 1-55860-316-6 OR 1558603166
ISBN13: 978-1-55860-316-5 OR 9781558603165
LCCN: QA76.8.P67 P68 1994
bibdate: Wed Jul 6 14:15:23 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.07.06 14:15:23 ???
acknowledgement: ack-nhfb
rawauthor: {IBM Corporation}
rawtitle: The {PowerPC} Architecture: a Specification for a New Family of {RISC} Processors
entry:
@Book{IBM:1994:OA,
  author =       "{IBM Corporation}",
  title =        "The {PowerPC} Architecture: a Specification for a New
                 Family of {RISC} Processors",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  edition =      "Second",
  pages =        "xxxi + 518",
  year =         "1994",
  ISBN =         "1-55860-316-6",
  ISBN-13 =      "978-1-55860-316-5",
  LCCN =         "QA76.8.P67 P68 1994",
  bibdate =      "Wed Jul 6 14:15:23 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "US\$49.95",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Ienne:1994:BSM
author: P. Ienne and M. A. Viredaz
title: Bit-serial multipliers and squarers
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 12
pages: 1445--1450
month: dec
monthnumber: 12
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.338107
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:59 MDT 2011
bibtimestamp: 2011.07.07 07:13:59 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=338107
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: P. Ienne and M. A. Viredaz
rawtitle: Bit-serial multipliers and squarers
entry:
@Article{Ienne:1994:BSM,
  author =       "P. Ienne and M. A. Viredaz",
  title =        "Bit-serial multipliers and squarers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "12",
  pages =        "1445--1450",
  month =        dec,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.338107",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:59 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=338107",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Ignatowski:1994:CNA
author: R. Ignatowski and E. E. Swartzlander
journal: Conference record
pages: 152--??
year: 1994
ISSN: 1058-6393 OR 10586393
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: R. Ignatowski and E. E. Swartzlander
title:
Creating New Algorithms and Modifying Old Algorithms to Use the Variable Precision Floating Point Simulator

rawtitle:
Creating New Algorithms and Modifying Old Algorithms to Use the Variable Precision Floating Point Simulator

entry:
@Article{Ignatowski:1994:CNA,
  author =       "R. Ignatowski and E. E. Swartzlander",
  title =        "Creating New Algorithms and Modifying Old Algorithms
                 to Use the Variable Precision Floating Point
                 Simulator",
  journal =      "Conference record",
  pages =        "152--??",
  year =         "1994",
  ISSN =         "1058-6393",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: Isaacson:1994:ANM
author: Eugene Isaacson and Herbert Bishop Keller
title: Analysis of numerical methods
publisher: pub-DOVER
address: pub-DOVER:adr
pages: xv + 541
year: 1994
ISBN: 0-486-68029-0 (paperback) OR 0486680290 (paperback)
ISBN13: 978-0-486-68029-3 (paperback) OR 9780486680293 (paperback)
LCCN: QA297 .I8 1994
bibdate: Fri Aug 20 09:37:14 MDT 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; z3950.loc.gov:7090/Voyager
bibtimestamp: 2010.08.20 09:37:14 MDT
URL: http://www.loc.gov/catdir/description/dover031/94007740.html
remark: Originally published in cite Isaacson:1966:ANM. Contains new preface.
subject: Numerical analysis
acknowledgement: ack-nhfb
rawauthor: Eugene Isaacson and Herbert Bishop Keller
rawtitle: Analysis of numerical methods
entry:
@Book{Isaacson:1994:ANM,
  author =       "Eugene Isaacson and Herbert Bishop Keller",
  title =        "Analysis of numerical methods",
  publisher =    pub-DOVER,
  address =      pub-DOVER:adr,
  pages =        "xv + 541",
  year =         "1994",
  ISBN =         "0-486-68029-0 (paperback)",
  ISBN-13 =      "978-0-486-68029-3 (paperback)",
  LCCN =         "QA297 .I8 1994",
  bibdate =      "Fri Aug 20 09:37:14 MDT 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 z3950.loc.gov:7090/Voyager",
  URL =          "http://www.loc.gov/catdir/description/dover031/94007740.html",
  acknowledgement = ack-nhfb,
  remark =       "Originally published in \cite{Isaacson:1966:ANM}.
                 Contains new preface.",
  subject =      "Numerical analysis",
}


bibtype: book
filename: fparith.bib
label: ISO:1994:IIIa
author: ISO
publisher: pub-ISO
address: pub-ISO:adr
pages: viii + 92
day: 15
month: dec
monthnumber: 12
year: 1994
bibdate: Sun Mar 15 11:09:44 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.03.15 11:09:44 ???
acknowledgement: ack-nhfb
rawauthor: {ISO}
title:
ISO / IEC 10967-1 (1994-12): Information technology --- Language independent arithmetic --- Part 1: Integer and floating point arithmetic

URL:
http://standards.iso.org/ittf/PubliclyAvailableStandards/c018939_ISO_IEC_10967-1_1994(E).zip; http://www.iec.ch/cgi-bin/procgi.pl/www/iecwww.p?wwwlang=E&wwwprog=cat-det.p&wartnum=019729; http://www.iso.ch/cate/d18939.html

rawtitle:
{ISO\slash IEC 10967-1 (1994-12)}: {Information} technology --- {Language} independent arithmetic --- {Part 1}: {Integer} and floating point arithmetic

entry:
@Book{ISO:1994:IIIa,
  author =       "{ISO}",
  title =        "{ISO\slash IEC 10967-1 (1994-12)}: {Information}
                 technology --- {Language} independent arithmetic ---
                 {Part 1}: {Integer} and floating point arithmetic",
  publisher =    pub-ISO,
  address =      pub-ISO:adr,
  pages =        "viii + 92",
  day =          "15",
  month =        dec,
  year =         "1994",
  bibdate =      "Sun Mar 15 11:09:44 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "CHF 176, US\$136.00",
  URL =          "http://standards.iso.org/ittf/PubliclyAvailableStandards/c018939_ISO_IEC_10967-1_1994(E).zip;
                 http://www.iec.ch/cgi-bin/procgi.pl/www/iecwww.p?wwwlang=E&wwwprog=cat-det.p&wartnum=019729;
                 http://www.iso.ch/cate/d18939.html",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Jackson:1994:PCE
author: K. R. Jackson and N. S. Nedialkov
title: Precision Control and Exception Handling in Scientific Computing
type: Technical Report
institution: Department of Computer Science, University of Toronto
address: Toronto, ON, Canada
pages: 8
year: 1994
bibdate: Tue May 22 15:45:43 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.05.22 15:45:43 ???
acknowledgement: ack-nhfb
rawauthor: K. R. Jackson and N. S. Nedialkov
rawtitle: Precision Control and Exception Handling in Scientific Computing
URL:
http://www.cs.toronto.edu/NA/reports.html#prec.except; http://www.cs.toronto.edu/pub/reports/na/prec.except.ps.Z

abstract:
This paper describes convenient language facilities for precision control and exception handling. Nedialkov has developed a variable-precision and exception handling library, SciLib, implemented as a numerical class library in C++. A new scalar data type, em real, is introduced, consisting of variable-precision floating-point numbers. Arithmetic, relational, and input and output operators of the language are overloaded for reals, so that mathematical expressions can be written without explicit function calls. Precision of computations can be changed during program execution. The exception handling mechanism treats only numerical exceptions and does not distinguish between different types of exceptions.par The proposed precision control and exception handling facilities are illustrated by sample SciLib programs.

rawabstract:
This paper describes convenient language facilities for precision control and exception handling. Nedialkov has developed a variable-precision and exception handling library, SciLib, implemented as a numerical class library in C++. A new scalar data type, {\em real}, is introduced, consisting of variable-precision floating-point numbers. Arithmetic, relational, and input and output operators of the language are overloaded for reals, so that mathematical expressions can be written without explicit function calls. Precision of computations can be changed during program execution. The exception handling mechanism treats only numerical exceptions and does not distinguish between different types of exceptions.\par The proposed precision control and exception handling facilities are illustrated by sample SciLib programs.

entry:
@TechReport{Jackson:1994:PCE,
  author =       "K. R. Jackson and N. S. Nedialkov",
  title =        "Precision Control and Exception Handling in Scientific
                 Computing",
  type =         "Technical Report",
  institution =  "Department of Computer Science, University of
                 Toronto",
  address =      "Toronto, ON, Canada",
  pages =        "8",
  year =         "1994",
  bibdate =      "Tue May 22 15:45:43 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.toronto.edu/NA/reports.html#prec.except;
                 http://www.cs.toronto.edu/pub/reports/na/prec.except.ps.Z",
  abstract =     "This paper describes convenient language facilities
                 for precision control and exception handling. Nedialkov
                 has developed a variable-precision and exception
                 handling library, SciLib, implemented as a numerical
                 class library in C++. A new scalar data type, {\em
                 real}, is introduced, consisting of variable-precision
                 floating-point numbers. Arithmetic, relational, and
                 input and output operators of the language are
                 overloaded for reals, so that mathematical expressions
                 can be written without explicit function calls.
                 Precision of computations can be changed during program
                 execution. The exception handling mechanism treats only
                 numerical exceptions and does not distinguish between
                 different types of exceptions.\par

                 The proposed precision control and exception handling
                 facilities are illustrated by sample SciLib programs.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Jain:1994:SRR
author: V. K. Jain and Lei Lin
title: Square-root, reciprocal, sine / cosine, arctangent cell for signal and image processing
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: II/521--II/524
year: 1994
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: V. K. Jain and Lei Lin
rawtitle: Square-root, reciprocal, sine\slash cosine, arctangent cell for signal and image processing
booktitle:
IEEE International Conference on Acoustics, Speech, and Signal Processing: ICASSP-94, 19--22 April 1994

rawbooktitle:
{IEEE} International Conference on Acoustics, Speech, and Signal Processing: {ICASSP-94, 19--22} April 1994

entry:
@InProceedings{Jain:1994:SRR,
  author =       "V. K. Jain and Lei Lin",
  booktitle =    "{IEEE} International Conference on Acoustics, Speech,
                 and Signal Processing: {ICASSP-94, 19--22} April 1994",
  title =        "Square-root, reciprocal, sine\slash cosine, arctangent
                 cell for signal and image processing",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "II/521--II/524",
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "This paper discusses an efficient interpolation method
                 for nonlinear function generation. Based on this, a 24
                 bit VLSI cell, capable of computing the (1) square
                 root, (2) reciprocal, (3) sine/cosine, and (4)
                 arctangent functions, is presented for \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Jaromczyk:1994:CCH
author: Jerzy W. Jaromczyk and G. W. Wasilkowski
title: Computing convex hull in a floating point arithmetic
journal: j-COMP-GEOM
volume: 4
number: 5
pages: 283--292
year: 1994
ISSN: 0925-7721 (print), 1879-081X (electronic) OR 09257721 (print), 1879081X (electronic)
ISSNL: 0925-7721 OR 09257721
MRclass: 68U05
MRnumber: 95j:68159
bibdate: Fri Dec 8 08:24:07 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:07 ???
fjournal: Computational Geometry. Theory and Applications
acknowledgement: ack-nhfb
rawauthor: Jerzy W. Jaromczyk and G. W. Wasilkowski
rawtitle: Computing convex hull in a floating point arithmetic
entry:
@Article{Jaromczyk:1994:CCH,
  author =       "Jerzy W. Jaromczyk and G. W. Wasilkowski",
  title =        "Computing convex hull in a floating point arithmetic",
  journal =      j-COMP-GEOM,
  volume =       "4",
  number =       "5",
  pages =        "283--292",
  year =         "1994",
  ISSN =         "0925-7721 (print), 1879-081X (electronic)",
  ISSN-L =       "0925-7721",
  MRclass =      "68U05",
  MRnumber =     "95j:68159",
  bibdate =      "Fri Dec 8 08:24:07 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Computational Geometry. Theory and Applications",
}


bibtype: article
filename: fparith.bib
label: Johnstone:1994:DAN
author: Paul Johnstone and Frederick E. Petry
title: Design and analysis of non-binary radix floating point representations
journal: j-COMPUT-ELECTR-ENG
volume: 20
number: 1
pages: 39--50
month: jan
monthnumber: 1
year: 1994
CODEN: CPEEBQ
ISSN: 0045-7906 (print), 1879-0755 (electronic) OR 00457906 (print), 18790755 (electronic)
ISSNL: 0045-7906 OR 00457906
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Computers and Electrical Engineering
acknowledgement: ack-nhfb
affiliation: Dow Jones Telerate, New Orleans, LA, USA
thesaurus: Digital arithmetic; Roundoff errors
rawauthor: Paul Johnstone and Frederick E. Petry
rawtitle: Design and analysis of non-binary radix floating point representations
abstract:
The authors examine the feasibility of higher radix floating point representations and in particular decimal based representations. Traditional analyses of such representations have assumed the format of a floating point datum to be roughly identical to that of traditional binary floating point encodings such as the IEEE P754 task group standard representations. We relax this restriction and propose a method of encoding higher radix floating point data with range, precision and storage requirements comparable to those exhibited by traditional binary representations. Results from W. M. McKeeman's (1967) maximum and average relative representational error (MRRE and ARRE) analyses, R. P. Brent's (1973) RMS error evaluation, D. W. Matula's (1970) ratio of significance space and gap functions, and W. S. Brown and P. L. Richman's (1969) exponent range estimates are extended to accommodate the proposed representation. A decimal alternative to traditional binary representations is proposed and the behavior of such a system is contrasted with that of a comparable binary system.

keywords:
ARRE; Average relative representational error; Decimal alternative; Decimal based representations; decimal floating-point arithmetic; Exponent range estimates; Floating point datum; Gap functions; Higher radix floating point representations; MRRE; Non-binary radix floating point representations; RMS error evaluation; Significance space ratio; Storage requirements

rawabstract:
The authors examine the feasibility of higher radix floating point representations and in particular decimal based representations. Traditional analyses of such representations have assumed the format of a floating point datum to be roughly identical to that of traditional binary floating point encodings such as the IEEE P754 task group standard representations. We relax this restriction and propose a method of encoding higher radix floating point data with range, precision and storage requirements comparable to those exhibited by traditional binary representations. Results from W. M. McKeeman's (1967) maximum and average relative representational error (MRRE and ARRE) analyses, R. P. Brent's (1973) RMS error evaluation, D. W. Matula's (1970) ratio of significance space and gap functions, and W. S. Brown and P. L. Richman's (1969) exponent range estimates are extended to accommodate the proposed representation. A decimal alternative to traditional binary representations is proposed and the behavior of such a system is contrasted with that of a comparable binary system.

entry:
@Article{Johnstone:1994:DAN,
  author =       "Paul Johnstone and Frederick E. Petry",
  title =        "Design and analysis of non-binary radix floating point
                 representations",
  journal =      j-COMPUT-ELECTR-ENG,
  volume =       "20",
  number =       "1",
  pages =        "39--50",
  month =        jan,
  year =         "1994",
  CODEN =        "CPEEBQ",
  ISSN =         "0045-7906 (print), 1879-0755 (electronic)",
  ISSN-L =       "0045-7906",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The authors examine the feasibility of higher radix
                 floating point representations and in particular
                 decimal based representations. Traditional analyses of
                 such representations have assumed the format of a
                 floating point datum to be roughly identical to that of
                 traditional binary floating point encodings such as the
                 IEEE P754 task group standard representations. We relax
                 this restriction and propose a method of encoding
                 higher radix floating point data with range, precision
                 and storage requirements comparable to those exhibited
                 by traditional binary representations. Results from W.
                 M. McKeeman's (1967) maximum and average relative
                 representational error (MRRE and ARRE) analyses, R. P.
                 Brent's (1973) RMS error evaluation, D. W. Matula's
                 (1970) ratio of significance space and gap functions,
                 and W. S. Brown and P. L. Richman's (1969) exponent
                 range estimates are extended to accommodate the
                 proposed representation. A decimal alternative to
                 traditional binary representations is proposed and the
                 behavior of such a system is contrasted with that of a
                 comparable binary system.",
  acknowledgement = ack-nhfb,
  affiliation =  "Dow Jones Telerate, New Orleans, LA, USA",
  classification = "B1265 (Digital electronics); C5230 (Digital
                 arithmetic methods)",
  fjournal =     "Computers and Electrical Engineering",
  keywords =     "ARRE; Average relative representational error; Decimal
                 alternative; Decimal based representations; decimal
                 floating-point arithmetic; Exponent range estimates;
                 Floating point datum; Gap functions; Higher radix
                 floating point representations; MRRE; Non-binary radix
                 floating point representations; RMS error evaluation;
                 Significance space ratio; Storage requirements",
  thesaurus =    "Digital arithmetic; Roundoff errors",
}


bibtype: article
filename: fparith.bib
label: Kabuo:1994:ARS
title: Accurate Rounding Scheme for the Newton--Raphson Method Using Redundant Binary Representation
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 1
pages: 43--51
month: jan
monthnumber: 1
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.250608
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:53 MDT 2011
bibtimestamp: 2011.07.07 07:13:53 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=250608
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nj
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: Accurate Rounding Scheme for the {Newton--Raphson} Method Using Redundant Binary Representation
author:
H. Kabuo and T. Taniguchi and A. Miyoshi and H. Yamashita and M. Urano and H. Edamatsu and S. Kuninobu

bibsource:
ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib

rawauthor:
H. Kabuo and T. Taniguchi and A. Miyoshi and H. Yamashita and M. Urano and H. Edamatsu and S. Kuninobu

entry:
@Article{Kabuo:1994:ARS,
  author =       "H. Kabuo and T. Taniguchi and A. Miyoshi and H.
                 Yamashita and M. Urano and H. Edamatsu and S.
                 Kuninobu",
  title =        "Accurate Rounding Scheme for the {Newton--Raphson}
                 Method Using Redundant Binary Representation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "1",
  pages =        "43--51",
  month =        jan,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.250608",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:53 MDT 2011",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=250608",
  acknowledgement = ack-nj # "\slash " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "Proposes a new algorithm of estimation and
                 compensation of the error effect for rounding in the
                 case of implementation of division and square root
                 using the Newton--Raphson method. The authors analyze
                 the error of the hardware system to confirm the
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Kalliojarvi:1994:RCW
author: K. Kalliojarvi and J. Astola
title: Required coefficient word length in floating-point and logarithmic digital filters
journal: j-IEEE-SIGNAL-PROCESS-LETT
volume: 1
number: 3
pages: 52--54
month: mar
monthnumber: 3
year: 1994
CODEN: ISPLEM
ISSN: 1070-9908 (print), 1558-2361 (electronic) OR 10709908 (print), 15582361 (electronic)
ISSNL: 1070-9908 OR 10709908
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Signal Processing Letters
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=97
rawauthor: K. Kalliojarvi and J. Astola
rawtitle: Required coefficient word length in floating-point and logarithmic digital filters
entry:
@Article{Kalliojarvi:1994:RCW,
  author =       "K. Kalliojarvi and J. Astola",
  title =        "Required coefficient word length in floating-point and
                 logarithmic digital filters",
  journal =      j-IEEE-SIGNAL-PROCESS-LETT,
  volume =       "1",
  number =       "3",
  pages =        "52--54",
  month =        mar,
  year =         "1994",
  CODEN =        "ISPLEM",
  ISSN =         "1070-9908 (print), 1558-2361 (electronic)",
  ISSN-L =       "1070-9908",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Signal Processing Letters",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=97",
  summary =      "The effects of coefficient quantization to the
                 response of a digital filter are studied. Easy-to-use
                 expressions for the required coefficient word length,
                 with which the filter response deviations are within
                 specified bounds, are derived for filters \ldots{}",
}


bibtype: mastersthesis
filename: fparith.bib
label: Kambi:1994:EAD
author: Shivaprakash Jayadev Kambi
title: Error analysis of digital filters realized with floating-point arithmetic
type: Thesis (M.S.)
school: Mississippi State University. Department of Electrical and Computer Engineering
address: Mississippi State, MS 39762, USA
pages: viii + 82
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Shivaprakash Jayadev Kambi
rawtitle: Error analysis of digital filters realized with floating-point arithmetic
keywords:
Digital filters (Mathematics); Electric filters, Digital.; Floating-point arithmetic.; Mississippi State University --- Thesis --- (1994)

entry:
@MastersThesis{Kambi:1994:EAD,
  author =       "Shivaprakash Jayadev Kambi",
  title =        "Error analysis of digital filters realized with
                 floating-point arithmetic",
  type =         "Thesis ({M.S.})",
  school =       "Mississippi State University. Department of Electrical
                 and Computer Engineering",
  address =      "Mississippi State, MS 39762, USA",
  pages =        "viii + 82",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Digital filters (Mathematics); Electric filters,
                 Digital.; Floating-point arithmetic.; Mississippi State
                 University --- Thesis --- (1994)",
}


bibtype: inproceedings
filename: fparith.bib
label: Kanellakis:1994:FPR
author: A. Kanellakis and P. Agathoklis
booktitle: IEEE International Symposium on Circuits and Systems: ISCAS '94, 2 June 1994
title: Floating-point roundoff noise analysis of $2$-D state-space digital filters
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 601--604
year: 1994
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: A. Kanellakis and P. Agathoklis
rawbooktitle: {IEEE} International Symposium on Circuits and Systems: {ISCAS '94}, 2 June 1994
rawtitle: Floating-point roundoff noise analysis of {$2$-D} state-space digital filters
entry:
@InProceedings{Kanellakis:1994:FPR,
  author =       "A. Kanellakis and P. Agathoklis",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems: {ISCAS '94}, 2 June 1994",
  title =        "Floating-point roundoff noise analysis of {$2$-D}
                 state-space digital filters",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "601--604",
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "In this paper the analysis of roundoff noise in
                 floating point state-space realizations of $2$-D
                 digital filters is considered. The variance of the
                 roundoff noise at the output of a $2$-D digital filter
                 is derived. It is shown that this variance is
                 \ldots{}",
}


bibtype: misc
filename: fparith.bib
label: Karp:1994:FPA
author: Alan H. Karp and Peter Markstein and Dennis Brzezinski
pages: 601--604
day: 23
month: aug
monthnumber: 8
year: 1994
bibdate: Thu Oct 17 10:20:52 2019
bibtimestamp: 2019.10.17 10:20:52 ???
URL: http://patft.uspto.gov/netahtml/PTO/search-bool.html; https://patents.google.com/patent/US5341321A
acknowledgement: ack-nhfb
howpublished: US Patent 5,341,321
rawauthor: Alan H. Karp and Peter Markstein and Dennis Brzezinski
title:
Floating point arithmetic unit using modified Newton--Raphson technique for division and square root

note:
Patent filed 5 May 1993, granted to Hewlett-Packard Company on 23 August 1994. Patent expired 5-May-2013. See criticism in cite Zimmermann:2005:XXX.

abstract:
A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton--Raphson method. The modified form of the Newton--Raphson method is used in place of the final iteration of the conventional Newton--Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.

rawabstract:
A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton--Raphson method. The modified form of the Newton--Raphson method is used in place of the final iteration of the conventional Newton--Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.

rawnote:
Patent filed 5 May 1993, granted to Hewlett-Packard Company on 23 August 1994. Patent expired 5-May-2013. See criticism in \cite{Zimmermann:2005:XXX}.

rawtitle:
Floating point arithmetic unit using modified {Newton--Raphson} technique for division and square root

entry:
@Misc{Karp:1994:FPA,
  author =       "Alan H. Karp and Peter Markstein and Dennis
                 Brzezinski",
  title =        "Floating point arithmetic unit using modified
                 {Newton--Raphson} technique for division and square
                 root",
  howpublished = "US Patent 5,341,321",
  day =          "23",
  month =        aug,
  year =         "1994",
  bibdate =      "Thu Oct 17 10:20:52 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Patent filed 5 May 1993, granted to Hewlett-Packard
                 Company on 23 August 1994. Patent expired 5-May-2013.
                 See criticism in \cite{Zimmermann:2005:XXX}.",
  URL =          "http://patft.uspto.gov/netahtml/PTO/search-bool.html;
                 https://patents.google.com/patent/US5341321A",
  abstract =     "A floating point processing system which uses a
                 multiplier unit and an adder unit to perform floating
                 point division and square root operations using both a
                 conventional and a modified form of the Newton--Raphson
                 method. The modified form of the Newton--Raphson method
                 is used in place of the final iteration of the
                 conventional Newton--Raphson so as to compute high
                 precision approximated results with a substantial
                 improvement in speed. The invention computes
                 approximated results faster and simplifies hardware
                 requirements because no multiplications of numbers of
                 the precision of the result are required.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Katti:1994:CDC
author: R. Katti
title: Comments on ``Decomposition of Complex Multipliers Using Polynomial Encoding''
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 3
pages: 381--383
month: mar
monthnumber: 3
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.272441
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:54 MDT 2011
bibtimestamp: 2011.07.07 07:13:54 MDT
note: See cite Skavantzos:1992:DCM.
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=272441
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: R. Katti
rawnote: See \cite{Skavantzos:1992:DCM}.
rawtitle: Comments on {``Decomposition of Complex Multipliers Using Polynomial Encoding''}
entry:
@Article{Katti:1994:CDC,
  author =       "R. Katti",
  title =        "Comments on {``Decomposition of Complex Multipliers
                 Using Polynomial Encoding''}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "3",
  pages =        "381--383",
  month =        mar,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.272441",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:54 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  note =         "See \cite{Skavantzos:1992:DCM}.",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=272441",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Kawahito:1994:HSA
author: S. Kawahito and M. Ishida and T. Nakamura and M. Kameyama and T. Higuchi
title: High-speed area-efficient multiplier design using multiple-valued current-mode circuits
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 1
pages: 34--42
month: jan
monthnumber: 1
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.250607
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:53 MDT 2011
bibtimestamp: 2011.07.07 07:13:53 MDT
note: See comments cite Parhami:1996:CHS.
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=250607
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Kawahito and M. Ishida and T. Nakamura and M. Kameyama and T. Higuchi
rawnote: See comments \cite{Parhami:1996:CHS}.
rawtitle: High-speed area-efficient multiplier design using multiple-valued current-mode circuits
entry:
@Article{Kawahito:1994:HSA,
  author =       "S. Kawahito and M. Ishida and T. Nakamura and M.
                 Kameyama and T. Higuchi",
  title =        "High-speed area-efficient multiplier design using
                 multiple-valued current-mode circuits",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "1",
  pages =        "34--42",
  month =        jan,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.250607",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:53 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  note =         "See comments \cite{Parhami:1996:CHS}.",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=250607",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Kim:1994:FPF
author: Seehyun Kim and Wonyong Sung
title: A Floating-Point to Fixed-Point Assembly Program Translator for the TMS 320C25
journal: j-IEEE-TRANS-CIRCUITS-SYST-2
volume: 41
number: 11
pages: 730--739
month: nov
monthnumber: 11
year: 1994
CODEN: ICSPE5
DOI: https://doi.org/10.1109/82.331543
ISSN: 1057-7130 (print), 1558-125X (electronic) OR 10577130 (print), 1558125X (electronic)
ISSNL: 1057-7130 OR 10577130
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Circuits and Systems. 2, Analog and Digital Signal Processing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82
rawauthor: Seehyun Kim and Wonyong Sung
rawtitle: A Floating-Point to Fixed-Point Assembly Program Translator for the {TMS} {320C25}
entry:
@Article{Kim:1994:FPF,
  author =       "Seehyun Kim and Wonyong Sung",
  title =        "A Floating-Point to Fixed-Point Assembly Program
                 Translator for the {TMS} {320C25}",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-2,
  volume =       "41",
  number =       "11",
  pages =        "730--739",
  month =        nov,
  year =         "1994",
  CODEN =        "ICSPE5",
  DOI =          "https://doi.org/10.1109/82.331543",
  ISSN =         "1057-7130 (print), 1558-125X (electronic)",
  ISSN-L =       "1057-7130",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems. 2, Analog
                 and Digital Signal Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82",
  summary =      "A floating-point digital signal processor-like
                 programming environment is developed for the Texas
                 Instruments TMS 320C25, a fixed-point digital signal
                 professor. Programmers first develop an assembly
                 program using a hypothetical floating-point instrument
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Kobbelt:1994:FDP
author: L. Kobbelt
title: A Fast Dot-Product Algorithm with Minimal Rounding Errors
journal: j-COMPUTING
volume: 52
number: 4
pages: 355--369
year: 1994
CODEN: CMPTA2
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
MRclass: 68Q20 (68Q25)
MRnumber: 1 287 970
bibdate: Tue Oct 12 16:33:42 MDT 1999
bibtimestamp: 1999.10.12 16:33:42 MDT
fjournal: Computing: Archiv fur informatik und numerik
acknowledgement: ack-nhfb
affiliation: Inst. fur Betriebs-und Dialogsyst., Karlsruhe University, Germany
journalURL: http://link.springer.com/journal/607
journalabr: Comput Vienna New York
rawauthor: L. Kobbelt
rawtitle: A Fast Dot-Product Algorithm with Minimal Rounding Errors
bibsource:
Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib; MathSciNet database; OCLC Contents1st database

abstract:
Presents a new algorithm which computes dot-products of arbitrary length with minimal rounding errors, independent of the number of addends. The algorithm has an O(n) time and O(1) memory complexity, and does not need extensions of the arithmetic kernel, i.e., the usual floating-point operations. A slight modification yields an algorithm which computes the dot-product in machine precision. Due to its simplicity, the algorithm can easily be implemented in hardware.

keywords:
Addends; Algorithms; Arbitrary length; Arithmetic kernel; Computational complexity; Computer arithmetic; Computer hardware; Digital arithmetic; Dot product computation; Errors; Exact computer arithmetic; Fast dot-product algorithm; Floating-point operations; Hardware implementation; Machine precision; Matrix algebra; Matrix multiplications; Memory complexity; Minimal rounding errors; Numerical algorithms; Numerical methods; Stability; Summation; Time complexity

thesaurus:
Computational complexity; Digital arithmetic; Matrix algebra; Numerical analysis; Roundoff errors; Vectors

rawabstract:
Presents a new algorithm which computes dot-products of arbitrary length with minimal rounding errors, independent of the number of addends. The algorithm has an O(n) time and O(1) memory complexity, and does not need extensions of the arithmetic kernel, i.e., the usual floating-point operations. A slight modification yields an algorithm which computes the dot-product in machine precision. Due to its simplicity, the algorithm can easily be implemented in hardware.

entry:
@Article{Kobbelt:1994:FDP,
  author =       "L. Kobbelt",
  title =        "A Fast Dot-Product Algorithm with Minimal Rounding
                 Errors",
  journal =      j-COMPUTING,
  volume =       "52",
  number =       "4",
  pages =        "355--369",
  year =         "1994",
  CODEN =        "CMPTA2",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  MRclass =      "68Q20 (68Q25)",
  MRnumber =     "1 287 970",
  bibdate =      "Tue Oct 12 16:33:42 MDT 1999",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 MathSciNet database; OCLC Contents1st database",
  abstract =     "Presents a new algorithm which computes dot-products
                 of arbitrary length with minimal rounding errors,
                 independent of the number of addends. The algorithm has
                 an O(n) time and O(1) memory complexity, and does not
                 need extensions of the arithmetic kernel, i.e., the
                 usual floating-point operations. A slight modification
                 yields an algorithm which computes the dot-product in
                 machine precision. Due to its simplicity, the algorithm
                 can easily be implemented in hardware.",
  acknowledgement = ack-nhfb,
  affiliation =  "Inst. f{\"u}r Betriebs-und Dialogsyst., Karlsruhe
                 University, Germany",
  classification = "721.1; 722.4; 921.1; 921.6; C4140 (Linear algebra);
                 C4240 (Programming and algorithm theory); C5230
                 (Digital arithmetic methods)",
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
  journalabr =   "Comput Vienna New York",
  keywords =     "Addends; Algorithms; Arbitrary length; Arithmetic
                 kernel; Computational complexity; Computer arithmetic;
                 Computer hardware; Digital arithmetic; Dot product
                 computation; Errors; Exact computer arithmetic; Fast
                 dot-product algorithm; Floating-point operations;
                 Hardware implementation; Machine precision; Matrix
                 algebra; Matrix multiplications; Memory complexity;
                 Minimal rounding errors; Numerical algorithms;
                 Numerical methods; Stability; Summation; Time
                 complexity",
  pubcountry =   "Austria",
  thesaurus =    "Computational complexity; Digital arithmetic; Matrix
                 algebra; Numerical analysis; Roundoff errors; Vectors",
}


bibtype: article
filename: fparith.bib
label: Kornerup:1994:SLA
author: P. Kornerup
title: A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 892--898
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295851
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:57 MDT 2011
bibtimestamp: 2011.07.07 07:13:57 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295851
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: P. Kornerup
rawtitle: A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib; OCLC Proceedings database

entry:
@Article{Kornerup:1994:SLA,
  author =       "P. Kornerup",
  title =        "A Systolic, Linear-Array Multiplier for a Class of
                 Right-Shift Algorithms",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "892--898",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295851",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:57 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295851",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Krandick:1994:EMF
author: W. Krandick and J. R. Johnson
title: Efficient multiprecision floating point multiplication with exact rounding
crossref: Calmet:1994:RWC
pages: 207--??
year: 1994
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
acknowledgement: ack-nhfb
affiliation: Res. Inst. for Symbolic Comput., Johannes Kepler University, Linz, Austria
thesaurus: Digital arithmetic; Mathematics computing
rawauthor: W. Krandick and J. R. Johnson
rawtitle: Efficient multiprecision floating point multiplication with exact rounding
abstract:
An algorithm is described for multiplying multiprecision floating point numbers. The returned result is equal to the floating point number obtained by rounding the exact product. Software implementations of multiprecision floating point multiplication can reduce the computing time by a factor of two if they do not compute the low order digits of the product of the two mantissas. However, these algorithms do not necessarily provide exactly rounded results. The algorithm described in this paper is guaranteed to produce exactly rounded results and typically obtains the same savings. The method can be modified to take advantage of Karatsuba's algorithm for fast integer multiplication.

keywords:
Exact rounding; Fast integer multiplication; Karatsuba's algorithm; Multiprecision floating point multiplication; Software implementations

rawabstract:
An algorithm is described for multiplying multiprecision floating point numbers. The returned result is equal to the floating point number obtained by rounding the exact product. Software implementations of multiprecision floating point multiplication can reduce the computing time by a factor of two if they do not compute the low order digits of the product of the two mantissas. However, these algorithms do not necessarily provide exactly rounded results. The algorithm described in this paper is guaranteed to produce exactly rounded results and typically obtains the same savings. The method can be modified to take advantage of Karatsuba's algorithm for fast integer multiplication.

entry:
@InProceedings{Krandick:1994:EMF,
  author =       "W. Krandick and J. R. Johnson",
  title =        "Efficient multiprecision floating point multiplication
                 with exact rounding",
  crossref =     "Calmet:1994:RWC",
  pages =        "207--??",
  year =         "1994",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "An algorithm is described for multiplying
                 multiprecision floating point numbers. The returned
                 result is equal to the floating point number obtained
                 by rounding the exact product. Software implementations
                 of multiprecision floating point multiplication can
                 reduce the computing time by a factor of two if they do
                 not compute the low order digits of the product of the
                 two mantissas. However, these algorithms do not
                 necessarily provide exactly rounded results. The
                 algorithm described in this paper is guaranteed to
                 produce exactly rounded results and typically obtains
                 the same savings. The method can be modified to take
                 advantage of Karatsuba's algorithm for fast integer
                 multiplication.",
  acknowledgement = ack-nhfb,
  affiliation =  "Res. Inst. for Symbolic Comput., Johannes Kepler
                 University, Linz, Austria",
  classification = "C5230 (Digital arithmetic methods); C7310
                 (Mathematics computing)",
  keywords =     "Exact rounding; Fast integer multiplication;
                 Karatsuba's algorithm; Multiprecision floating point
                 multiplication; Software implementations",
  thesaurus =    "Digital arithmetic; Mathematics computing",
}


bibtype: article
filename: fparith.bib
label: Laakso:1994:BFP
author: T. I. Laakso and L. B. Jackson
title: Bounds for Floating-Point Roundoff Noise
journal: j-IEEE-TRANS-CIRCUITS-SYST-2
volume: 41
number: 6
pages: 424--426
month: jun
monthnumber: 6
year: 1994
CODEN: ICSPE5
DOI: https://doi.org/10.1109/82.300204
ISSN: 1057-7130 (print), 1558-125X (electronic) OR 10577130 (print), 1558125X (electronic)
ISSNL: 1057-7130 OR 10577130
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Circuits and Systems. 2, Analog and Digital Signal Processing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82
rawauthor: T. I. Laakso and L. B. Jackson
rawtitle: Bounds for Floating-Point Roundoff Noise
entry:
@Article{Laakso:1994:BFP,
  author =       "T. I. Laakso and L. B. Jackson",
  title =        "Bounds for Floating-Point Roundoff Noise",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-2,
  volume =       "41",
  number =       "6",
  pages =        "424--426",
  month =        jun,
  year =         "1994",
  CODEN =        "ICSPE5",
  DOI =          "https://doi.org/10.1109/82.300204",
  ISSN =         "1057-7130 (print), 1558-125X (electronic)",
  ISSN-L =       "1057-7130",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems. 2, Analog
                 and Digital Signal Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82",
  summary =      "The dummy multiplier model and the conventional
                 estimates for roundoff noise variance in floating-point
                 implementations are compared. Common upper and lower
                 bounds for the noise estimates are derived and
                 experimental results are presented. Although \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Laakso:1994:ELC
author: T. Laakso and B. Zeng and I. Hartimo and Y. Neuvo
journal: j-IEEE-TRANS-CIRCUITS-SYST-2
volume: 41
number: 4
pages: 308--313
month: apr
monthnumber: 4
year: 1994
CODEN: ICSPE5
DOI: https://doi.org/10.1109/82.285707
ISSN: 1057-7130 (print), 1558-125X (electronic) OR 10577130 (print), 1558125X (electronic)
ISSNL: 1057-7130 OR 10577130
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Circuits and Systems. 2, Analog and Digital Signal Processing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82
rawauthor: T. Laakso and B. Zeng and I. Hartimo and Y. Neuvo
title:
Elimination of limit cycles in floating-point implementations of direct-form recursive digital filters

rawtitle:
Elimination of limit cycles in floating-point implementations of direct-form recursive digital filters

entry:
@Article{Laakso:1994:ELC,
  author =       "T. Laakso and B. Zeng and I. Hartimo and Y. Neuvo",
  title =        "Elimination of limit cycles in floating-point
                 implementations of direct-form recursive digital
                 filters",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-2,
  volume =       "41",
  number =       "4",
  pages =        "308--313",
  month =        apr,
  year =         "1994",
  CODEN =        "ICSPE5",
  DOI =          "https://doi.org/10.1109/82.285707",
  ISSN =         "1057-7130 (print), 1558-125X (electronic)",
  ISSN-L =       "1057-7130",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems. 2, Analog
                 and Digital Signal Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82",
  summary =      "This paper focuses on the limit cycle analysis of
                 floating-point implementations of direct form recursive
                 digital filters. A sufficient criterion for the absence
                 of zero-input limit cycles is derived for a direct-form
                 implementation with a single \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Ledoux:1994:TOW
author: C. Ledoux and J. F. Grandin
title: Two original weight pruning methods based on statistical tests and rounding techniques
journal: Vision, Image and Signal Processing, IEE Proceedings-
volume: 141
number: 4
pages: 230--237
month: aug
monthnumber: 8
year: 1994
bibdate: Sat Jul 16 11:25:03 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:03 MDT
acknowledgement: ack-nhfb
rawauthor: C. Ledoux and J. F. Grandin
rawtitle: Two original weight pruning methods based on statistical tests and rounding techniques
entry:
@Article{Ledoux:1994:TOW,
  author =       "C. Ledoux and J. F. Grandin",
  title =        "Two original weight pruning methods based on
                 statistical tests and rounding techniques",
  journal =      "Vision, Image and Signal Processing, IEE
                 Proceedings-",
  volume =       "141",
  number =       "4",
  pages =        "230--237",
  month =        aug,
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:03 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The authors focus on the use of neural networks to
                 approximate continuous decision functions. In this
                 context, the parameters to be estimated are the
                 synaptic weights of the network. The number of such
                 parameters and the quantity of data \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Lewis:1994:IMF
author: D. M. Lewis
title: Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 974--982
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295859
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:57 MDT 2011
bibtimestamp: 2011.07.07 07:13:57 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295859
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Toronto University, Ont., Canada
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. M. Lewis
rawtitle: Interleaved Memory Function Interpolators with Application to an Accurate {LNS} Arithmetic Unit
abstract:
This paper describes a new method for polynomial interpolation in hardware, with advantages demonstrated by its application to an accurate logarithmic number system (LNS) arithmetic unit. The use of an interleaved memory reduces storage requirements by allowing each stored function value to be used in interpolation across several segments. This strategy can be shown to always use fewer words of memory than an optimized polynomial with stored polynomial coefficients. Interleaved memory function interpolators are then applied to the specific goal of an accurate logarithmic number system arithmetic unit. Many accuracy requirements for the LNS arithmetic unit are possible. Although a round to nearest would be desirable, it cannot be easily achieved. The goal suggested is to insure that the worst case LNS relative error is smaller than the worst case floating point (FP) relative error. Using the interleaved memory interpolator, the detailed design of an LNS arithmetic unit is performed using a second order polynomial interpolator including approximately 91K bits of ROM. This arithmetic unit has better accuracy and less complexity than previous LNS units.

keywords:
32 Bit; 91 Kbit; Accuracy requirements; Accurate logarithmic number system (LNS) arithmetic unit; Floating point; Interleaved memory function interpolators; Polynomial interpolation; ROM; Round to nearest; Storage requirements

thesaurus:
Approximation theory; Digital arithmetic; Error analysis; Interpolation; Polynomials; Read-only storage

rawabstract:
This paper describes a new method for polynomial interpolation in hardware, with advantages demonstrated by its application to an accurate logarithmic number system (LNS) arithmetic unit. The use of an interleaved memory reduces storage requirements by allowing each stored function value to be used in interpolation across several segments. This strategy can be shown to always use fewer words of memory than an optimized polynomial with stored polynomial coefficients. Interleaved memory function interpolators are then applied to the specific goal of an accurate logarithmic number system arithmetic unit. Many accuracy requirements for the LNS arithmetic unit are possible. Although a round to nearest would be desirable, it cannot be easily achieved. The goal suggested is to insure that the worst case LNS relative error is smaller than the worst case floating point (FP) relative error. Using the interleaved memory interpolator, the detailed design of an LNS arithmetic unit is performed using a second order polynomial interpolator including approximately 91K bits of ROM. This arithmetic unit has better accuracy and less complexity than previous LNS units.

entry:
@Article{Lewis:1994:IMF,
  author =       "D. M. Lewis",
  title =        "Interleaved Memory Function Interpolators with
                 Application to an Accurate {LNS} Arithmetic Unit",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "974--982",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295859",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:57 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295859",
  abstract =     "This paper describes a new method for polynomial
                 interpolation in hardware, with advantages demonstrated
                 by its application to an accurate logarithmic number
                 system (LNS) arithmetic unit. The use of an interleaved
                 memory reduces storage requirements by allowing each
                 stored function value to be used in interpolation
                 across several segments. This strategy can be shown to
                 always use fewer words of memory than an optimized
                 polynomial with stored polynomial coefficients.
                 Interleaved memory function interpolators are then
                 applied to the specific goal of an accurate logarithmic
                 number system arithmetic unit. Many accuracy
                 requirements for the LNS arithmetic unit are possible.
                 Although a round to nearest would be desirable, it
                 cannot be easily achieved. The goal suggested is to
                 insure that the worst case LNS relative error is
                 smaller than the worst case floating point (FP)
                 relative error. Using the interleaved memory
                 interpolator, the detailed design of an LNS arithmetic
                 unit is performed using a second order polynomial
                 interpolator including approximately 91K bits of ROM.
                 This arithmetic unit has better accuracy and less
                 complexity than previous LNS units.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. and Comput. Eng., Toronto
                 University, Ont., Canada",
  ajournal =     "IEEE Trans. Comput.",
  classification = "C4110 (Error analysis in numerical methods); C4130
                 (Interpolation and function approximation); C5230
                 (Digital arithmetic methods); C5320G (Semiconductor
                 storage)",
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "32 Bit; 91 Kbit; Accuracy requirements; Accurate
                 logarithmic number system (LNS) arithmetic unit;
                 Floating point; Interleaved memory function
                 interpolators; Polynomial interpolation; ROM; Round to
                 nearest; Storage requirements",
  numericalindex = "Word length 3.2E+01 bit; Storage capacity 9.3E+04
                 bit",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
  summary =      "This paper describes a new method for polynomial
                 interpolation in hardware, with advantages demonstrated
                 by its application to an accurate logarithmic number
                 system (LNS) arithmetic unit. The use of an interleaved
                 memory reduces storage requirements \ldots{}",
  thesaurus =    "Approximation theory; Digital arithmetic; Error
                 analysis; Interpolation; Polynomials; Read-only
                 storage",
}


bibtype: article
filename: fparith.bib
label: Lo:1994:RFP
author: Jien-Chung Lo
title: Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 4
pages: 400--412
month: apr
monthnumber: 4
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.278479
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:55 MDT 2011
bibtimestamp: 2011.07.07 07:13:55 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=278479
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
affiliation: Department of Electr. Eng., Rhode Island University, Kingston, RI, USA
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
thesaurus: Digital arithmetic; Error correction codes; Redundancy
rawauthor: Jien-Chung Lo
rawtitle: Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
abstract:
Reliable floating-point arithmetic is vital for dependable computing systems. It is also important for future high-density VLSI realizations that are vulnerable to soft-errors. However, the direct checking of floating-point arithmetic is still an open problem. The author presents a set of reliable floating-point arithmetic algorithms for low-cost residue encoded and Berger encoded operands, respectively. Closed form equations are derived for floating-point addition, subtraction, multiplication, and division. Given the standard IEEE floating-point numbers, the proposed reliable floating-point multiplication algorithms for low-cost residue encoded operands are extremely low-cost: it requires less than 8% of hardware redundancy in all cases. For reliable floating-point addition and subtraction, the author finds the hardware redundancy ratios of applying low-cost residue code is about the same as that of applying Berger code: less than 40% of hardware redundancy for single precision numbers and about 16% for double precision numbers. For reliable floating-point division, Berger encoded operands yields hardware cost-effectiveness: about 45% for single precision numbers and about 36% for double precision numbers.

keywords:
Berger check prediction; Berger encoded; Computer arithmetic; Concurrent error detection; Error-coded operands; Floating-point arithmetic; Hardware redundancy; High-density VLSI; Low-cost residue codes; Redundancy ratios; Reliable floating-point multiplication; Residue encoded; Soft-errors; Standard IEEE floating-point numbers

rawabstract:
Reliable floating-point arithmetic is vital for dependable computing systems. It is also important for future high-density VLSI realizations that are vulnerable to soft-errors. However, the direct checking of floating-point arithmetic is still an open problem. The author presents a set of reliable floating-point arithmetic algorithms for low-cost residue encoded and Berger encoded operands, respectively. Closed form equations are derived for floating-point addition, subtraction, multiplication, and division. Given the standard IEEE floating-point numbers, the proposed reliable floating-point multiplication algorithms for low-cost residue encoded operands are extremely low-cost: it requires less than 8\% of hardware redundancy in all cases. For reliable floating-point addition and subtraction, the author finds the hardware redundancy ratios of applying low-cost residue code is about the same as that of applying Berger code: less than 40\% of hardware redundancy for single precision numbers and about 16\% for double precision numbers. For reliable floating-point division, Berger encoded operands yields hardware cost-effectiveness: about 45\% for single precision numbers and about 36\% for double precision numbers.

entry:
@Article{Lo:1994:RFP,
  author =       "Jien-Chung Lo",
  title =        "Reliable Floating-Point Arithmetic Algorithms for
                 Error-Coded Operands",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "4",
  pages =        "400--412",
  month =        apr,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.278479",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:55 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=278479",
  abstract =     "Reliable floating-point arithmetic is vital for
                 dependable computing systems. It is also important for
                 future high-density VLSI realizations that are
                 vulnerable to soft-errors. However, the direct checking
                 of floating-point arithmetic is still an open problem.
                 The author presents a set of reliable floating-point
                 arithmetic algorithms for low-cost residue encoded and
                 Berger encoded operands, respectively. Closed form
                 equations are derived for floating-point addition,
                 subtraction, multiplication, and division. Given the
                 standard IEEE floating-point numbers, the proposed
                 reliable floating-point multiplication algorithms for
                 low-cost residue encoded operands are extremely
                 low-cost: it requires less than 8\% of hardware
                 redundancy in all cases. For reliable floating-point
                 addition and subtraction, the author finds the hardware
                 redundancy ratios of applying low-cost residue code is
                 about the same as that of applying Berger code: less
                 than 40\% of hardware redundancy for single precision
                 numbers and about 16\% for double precision numbers.
                 For reliable floating-point division, Berger encoded
                 operands yields hardware cost-effectiveness: about 45\%
                 for single precision numbers and about 36\% for double
                 precision numbers.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. Eng., Rhode Island University,
                 Kingston, RI, USA",
  ajournal =     "IEEE Trans. Comput.",
  classification = "C5230 (Digital arithmetic methods)",
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Berger check prediction; Berger encoded; Computer
                 arithmetic; Concurrent error detection; Error-coded
                 operands; Floating-point arithmetic; Hardware
                 redundancy; High-density VLSI; Low-cost residue codes;
                 Redundancy ratios; Reliable floating-point
                 multiplication; Residue encoded; Soft-errors; Standard
                 IEEE floating-point numbers",
  summary =      "Reliable floating-point arithmetic is vital for
                 dependable computing systems. It is also important for
                 future high-density VLSI realizations that are
                 vulnerable to soft-errors. However, the direct checking
                 of floating-point arithmetic is still an open
                 \ldots{}",
  thesaurus =    "Digital arithmetic; Error correction codes;
                 Redundancy",
}


bibtype: book
filename: fparith.bib
label: May:1994:PAS
editor: Cathy May and Ed Silha and Rick Simpson and Hank Warren
title: The PowerPC Architecture: a Specification for a New Family of RISC Processors
publisher: pub-MORGAN-KAUFMANN
address: pub-MORGAN-KAUFMANN:adr
edition: Second
pages: xxxi + 518
year: 1994
ISBN: 1-55860-316-6 OR 1558603166
ISBN13: 978-1-55860-316-5 OR 9781558603165
LCCN: QA76.8.P67 P68 1994
bibdate: Sat Feb 24 10:55:16 2001
bibtimestamp: 2001.02.24 10:55:16 ???
acknowledgement: ack-nhfb
raweditor: Cathy May and Ed Silha and Rick Simpson and Hank Warren
rawtitle: The {PowerPC} Architecture: a Specification for a New Family of {RISC} Processors
TOC:
Book III. PowerPC Operating Environment Architecture 2. Branch Processor 3. Fixed-Point Processor 4. Storage Control 5. Interrupts 6. Timer Facilities 7. Synchronization Requirements for Special Registers and for Lookaside Buffers Appendix A. Optional Facilities and Instructions Appendix B. Assembler Extended Mnemonics Appendix C. Cross-Reference for Changed POWER Mnemonics Appendix D. New Instructions Appendix E. Implementation-Specific SPRs Appendix F. Interpretation of the DSISR as Set by an Alignment Interrupt Appendix G. PowerPC Operating Environment Instruction Set

rawTOC:
Book III. PowerPC Operating Environment Architecture \\ 2. Branch Processor \\ 3. Fixed-Point Processor \\ 4. Storage Control \\ 5. Interrupts \\ 6. Timer Facilities \\ 7. Synchronization Requirements for Special Registers and for Lookaside Buffers \\ Appendix A. Optional Facilities and Instructions \\ Appendix B. Assembler Extended Mnemonics \\ Appendix C. Cross-Reference for Changed POWER Mnemonics \\ Appendix D. New Instructions \\ Appendix E. Implementation-Specific SPRs \\ Appendix F. Interpretation of the DSISR as Set by an Alignment Interrupt \\ Appendix G. PowerPC Operating Environment Instruction Set

entry:
@Book{May:1994:PAS,
  editor =       "Cathy May and Ed Silha and Rick Simpson and Hank
                 Warren",
  title =        "The {PowerPC} Architecture: a Specification for a New
                 Family of {RISC} Processors",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  edition =      "Second",
  pages =        "xxxi + 518",
  year =         "1994",
  ISBN =         "1-55860-316-6",
  ISBN-13 =      "978-1-55860-316-5",
  LCCN =         "QA76.8.P67 P68 1994",
  bibdate =      "Sat Feb 24 10:55:16 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 https://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$49.95",
  acknowledgement = ack-nhfb,
  oldlabel =     "IBM:1994:PAS",
  tableofcontents = "Book III. PowerPC Operating Environment
                 Architecture \\
                 2. Branch Processor \\
                 3. Fixed-Point Processor \\
                 4. Storage Control \\
                 5. Interrupts \\
                 6. Timer Facilities \\
                 7. Synchronization Requirements for Special Registers
                 and for Lookaside Buffers \\
                 Appendix A. Optional Facilities and Instructions \\
                 Appendix B. Assembler Extended Mnemonics \\
                 Appendix C. Cross-Reference for Changed POWER Mnemonics
                 \\
                 Appendix D. New Instructions \\
                 Appendix E. Implementation-Specific SPRs \\
                 Appendix F. Interpretation of the DSISR as Set by an
                 Alignment Interrupt \\
                 Appendix G. PowerPC Operating Environment Instruction
                 Set",
}


bibtype: article
filename: fparith.bib
label: McGrath:1994:OMC
author: Gary McGrath
title: Optimizing MC68882 Code
journal: j-DDJ
volume: 19
number: 6
pages: 58, 60, 62, 64, 66, 98--99
month: jun
monthnumber: 6
year: 1994
CODEN: DDJOEB
ISSN: 1044-789X OR 1044789X
bibdate: Tue Sep 03 09:15:49 1996
bibtimestamp: 1996.09.03 09:15:49 ???
fjournal: Dr. Dobb's Journal of Software Tools
acknowledgement: ack-nhfb
affiliation: Stanford Linear Accel. Center, Stanford University, CA, USA
rawauthor: Gary McGrath
rawtitle: Optimizing {MC68882} Code
abstract:
The MC68882 floating-point coprocessor adds 46 instructions to the MC68020/030 32-bit microprocessor, substantially increasing the speed of floating-point calculations. Gary examines these instructions and finds certain combinations to be faster than others.

keywords:
32 Bit; 80 Bit; 80-Bit extended precision; ANSI-IEEE 754-1985 binary floating-point arithmetic standard; FPCP; MC68020 microprocessor; MC68030 microprocessor; MC68882 floating-point coprocessor; Optimizing MC68882 code; Parallel operation; Pipeline architecture

thesaurus:
Digital arithmetic; Microprocessor chips; Parallel processing; Pipeline processing; Satellite computers

rawabstract:
The MC68882 floating-point coprocessor adds 46 instructions to the MC68020/030 32-bit microprocessor, substantially increasing the speed of floating-point calculations. Gary examines these instructions and finds certain combinations to be faster than others.

entry:
@Article{McGrath:1994:OMC,
  author =       "Gary McGrath",
  title =        "Optimizing {MC68882} Code",
  journal =      j-DDJ,
  volume =       "19",
  number =       "6",
  pages =        "58, 60, 62, 64, 66, 98--99",
  month =        jun,
  year =         "1994",
  CODEN =        "DDJOEB",
  ISSN =         "1044-789X",
  bibdate =      "Tue Sep 03 09:15:49 1996",
  bibsource =    "http://www.ddj.com/index/author/index.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 UnCover database",
  abstract =     "The MC68882 floating-point coprocessor adds 46
                 instructions to the MC68020/030 32-bit microprocessor,
                 substantially increasing the speed of floating-point
                 calculations. Gary examines these instructions and
                 finds certain combinations to be faster than others.",
  acknowledgement = ack-nhfb,
  affiliation =  "Stanford Linear Accel. Center, Stanford University,
                 CA, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220P (Parallel architecture);
                 C5230 (Digital arithmetic methods)",
  fjournal =     "Dr. Dobb's Journal of Software Tools",
  keywords =     "32 Bit; 80 Bit; 80-Bit extended precision; ANSI-IEEE
                 754-1985 binary floating-point arithmetic standard;
                 FPCP; MC68020 microprocessor; MC68030 microprocessor;
                 MC68882 floating-point coprocessor; Optimizing MC68882
                 code; Parallel operation; Pipeline architecture",
  thesaurus =    "Digital arithmetic; Microprocessor chips; Parallel
                 processing; Pipeline processing; Satellite computers",
}


bibtype: article
filename: fparith.bib
label: Meek:1994:PLT
author: Brian L. Meek
title: Programming languages: towards greater commonality
journal: j-SIGPLAN
volume: 29
number: 4
pages: 49--57
month: apr
monthnumber: 4
year: 1994
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:16:49 MST 2003
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.14 09:16:49 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
corpsource: Comput. Centre, King's Coll., London, UK
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
treatment: G General Review
rawauthor: Brian L. Meek
rawtitle: Programming languages: towards greater commonality
keywords:
cross-language standardisation; JTC1; language independent arithmetic; language independent calling; language independent datatypes; language independent procedure calling; language independent standards; language standardisation; OSI; programming; programming guidelines; programming languages; programming languages commonality; programming languages differences; remote procedure calling; remote procedure calls; SC22; standardisation; standards; subcommittee; working group

entry:
@Article{Meek:1994:PLT,
  author =       "Brian L. Meek",
  title =        "Programming languages: towards greater commonality",
  journal =      j-SIGPLAN,
  volume =       "29",
  number =       "4",
  pages =        "49--57",
  month =        apr,
  year =         "1994",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:49 MST 2003",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "C6110 (Systems analysis and programming); C6140
                 (Programming languages)",
  corpsource =   "Comput. Centre, King's Coll., London, UK",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "cross-language standardisation; JTC1; language
                 independent arithmetic; language independent calling;
                 language independent datatypes; language independent
                 procedure calling; language independent standards;
                 language standardisation; OSI; programming; programming
                 guidelines; programming languages; programming
                 languages commonality; programming languages
                 differences; remote procedure calling; remote procedure
                 calls; SC22; standardisation; standards; subcommittee;
                 working group",
  treatment =    "G General Review",
}


bibtype: inproceedings
filename: fparith.bib
label: Mehlhorn:1994:IGA
author: Kurt Mehlhorn and Stefan Naher
title: The Implementation of Geometric Algorithms
crossref: Pehrson:1994:IPP
volume: 1
pages: 223--231
year: 1994
bibdate: Tue Nov 13 21:47:31 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.13 21:47:31 ???
acknowledgement: ack-nhfb
rawauthor: Kurt Mehlhorn and Stefan Naher
rawtitle: The Implementation of Geometric Algorithms
entry:
@InProceedings{Mehlhorn:1994:IGA,
  author =       "Kurt Mehlhorn and Stefan Naher",
  title =        "The Implementation of Geometric Algorithms",
  crossref =     "Pehrson:1994:IPP",
  volume =       "1",
  pages =        "223--231",
  year =         "1994",
  bibdate =      "Tue Nov 13 21:47:31 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Montgomery:1994:SRP
author: Peter L. Montgomery
title: Square roots of products of algebraic numbers
crossref: Gautschi:1994:MCH
pages: 567--571
year: 1994
bibdate: Thu Oct 25 14:53:00 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.25 14:53:00 ???
acknowledgement: ack-nhfb
rawauthor: Peter L. Montgomery
rawtitle: Square roots of products of algebraic numbers
entry:
@InProceedings{Montgomery:1994:SRP,
  author =       "Peter L. Montgomery",
  title =        "Square roots of products of algebraic numbers",
  crossref =     "Gautschi:1994:MCH",
  pages =        "567--571",
  year =         "1994",
  bibdate =      "Thu Oct 25 14:53:00 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Montuschi:1994:DUN
author: P. Montuschi and L. Ciminiera and A. Giustina
title: Division unit with Newton--Raphson approximation and digit-by-digit refinement of the quotient
journal: j-IEE-PROC-COMPUT-DIGIT-TECH
volume: 141
number: 6
pages: 317--324
month: nov
monthnumber: 11
year: 1994
CODEN: ICDTEA
ISSN: 1350-2387 (print), 1359-7027 (electronic) OR 13502387 (print), 13597027 (electronic)
ISSNL: 1350-2387 OR 13502387
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: IEE Proceedings. Computers and Digital Techniques
acknowledgement: ack-nhfb
affiliation: Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
thesaurus: Dividing circuits; Floating point arithmetic; Newton--Raphson method
rawauthor: P. Montuschi and L. Ciminiera and A. Giustina
rawtitle: Division unit with {Newton--Raphson} approximation and digit-by-digit refinement of the quotient
abstract:
The advantages of the convergence with the square of the Newton--Raphson method are combined with the precision characteristics of digit-by-digit algorithms to obtain units for fast division that satisfy the IEEE 754 floating point standard requirements. A general design methodology that leads to a class of alternative architectures providing interesting performances for division is presented, together with one example of possible implementation. In particular, the proposed implementation achieves a speedup varying from 20% to about 30% in comparison with a previous architecture by Fandrianto, with a relatively small additional hardware cost if a multiplier is already available on the arithmetic unit.

keywords:
Convergence; Digit-by-digit refinement; Fast division; Floating point standard; Newton--Raphson approximation

rawabstract:
The advantages of the convergence with the square of the Newton--Raphson method are combined with the precision characteristics of digit-by-digit algorithms to obtain units for fast division that satisfy the IEEE 754 floating point standard requirements. A general design methodology that leads to a class of alternative architectures providing interesting performances for division is presented, together with one example of possible implementation. In particular, the proposed implementation achieves a speedup varying from 20\% to about 30\% in comparison with a previous architecture by Fandrianto, with a relatively small additional hardware cost if a multiplier is already available on the arithmetic unit.

entry:
@Article{Montuschi:1994:DUN,
  author =       "P. Montuschi and L. Ciminiera and A. Giustina",
  title =        "Division unit with {Newton--Raphson} approximation and
                 digit-by-digit refinement of the quotient",
  journal =      j-IEE-PROC-COMPUT-DIGIT-TECH,
  volume =       "141",
  number =       "6",
  pages =        "317--324",
  month =        nov,
  year =         "1994",
  CODEN =        "ICDTEA",
  ISSN =         "1350-2387 (print), 1359-7027 (electronic)",
  ISSN-L =       "1350-2387",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The advantages of the convergence with the square of
                 the Newton--Raphson method are combined with the
                 precision characteristics of digit-by-digit algorithms
                 to obtain units for fast division that satisfy the IEEE
                 754 floating point standard requirements. A general
                 design methodology that leads to a class of alternative
                 architectures providing interesting performances for
                 division is presented, together with one example of
                 possible implementation. In particular, the proposed
                 implementation achieves a speedup varying from 20\% to
                 about 30\% in comparison with a previous architecture
                 by Fandrianto, with a relatively small additional
                 hardware cost if a multiplier is already available on
                 the arithmetic unit.",
  acknowledgement = ack-nhfb,
  affiliation =  "Dipartimento di Autom. e Inf., Politecnico di Torino,
                 Italy",
  classification = "C4130 (Interpolation and function approximation);
                 C5120 (Logic and switching circuits); C5230 (Digital
                 arithmetic methods)",
  fjournal =     "IEE Proceedings. Computers and Digital Techniques",
  keywords =     "Convergence; Digit-by-digit refinement; Fast division;
                 Floating point standard; Newton--Raphson
                 approximation",
  pubcountry =   "UK",
  thesaurus =    "Dividing circuits; Floating point arithmetic;
                 Newton--Raphson method",
}


bibtype: article
filename: fparith.bib
label: Montuschi:1994:RDO
author: P. Montuschi and L. Ciminiera
title: Radix-8 division with over-redundant digit set
journal: j-J-VLSI-SIGNAL-PROC
volume: 7
number: 3
pages: 259--270
month: may
monthnumber: 5
year: 1994
CODEN: JVSPED
DOI: https://doi.org/10.1007/BF02409402
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
affiliation: Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
thesaurus: Digital arithmetic; Dividing circuits
rawauthor: P. Montuschi and L. Ciminiera
rawtitle: Radix-8 division with over-redundant digit set
abstract:
We present a radix-8 divider that uses an over-redundant digit set for the quotient in order to obtain simple digit selection rules. We show that the proposed enlarged set of values for the quotient digit does not lead to increases both in the complexity and the delay of the adder required to update the remainder, with respect to similar solutions, since the values allowed for the quotient digit have been selected carefully. The digit selection process is subdivided into two concurrent steps, each one making reference to a secondary digit set and the resulting implementation can be cheaper and faster than other units which do not use over-redundant digit sets. A performance analysis estimates a speed improvement from 25% to 35% with respect to a radix-8 architecture by Fandrianto (1987, 1989), and from 21% to 30% with respect to a radix-4 architecture with prescaling, presented by Ercegovac and Lang (1990). As required from the IEEE 754 floating point standard, the proposed algorithm features the correct remainder of the division.

keywords:
Algorithm; Delay; Digit selection rules; IEEE 754 floating point standard; Over-redundant digit set; Performance analysis; Quotient; Radix-8 divider; Radix-8 division; Remainder; Speed improvement

rawabstract:
We present a radix-8 divider that uses an over-redundant digit set for the quotient in order to obtain simple digit selection rules. We show that the proposed enlarged set of values for the quotient digit does not lead to increases both in the complexity and the delay of the adder required to update the remainder, with respect to similar solutions, since the values allowed for the quotient digit have been selected carefully. The digit selection process is subdivided into two concurrent steps, each one making reference to a secondary digit set and the resulting implementation can be cheaper and faster than other units which do not use over-redundant digit sets. A performance analysis estimates a speed improvement from 25\% to 35\% with respect to a radix-8 architecture by Fandrianto (1987, 1989), and from 21\% to 30\% with respect to a radix-4 architecture with prescaling, presented by Ercegovac and Lang (1990). As required from the IEEE 754 floating point standard, the proposed algorithm features the correct remainder of the division.

entry:
@Article{Montuschi:1994:RDO,
  author =       "P. Montuschi and L. Ciminiera",
  title =        "Radix-8 division with over-redundant digit set",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "7",
  number =       "3",
  pages =        "259--270",
  month =        may,
  year =         "1994",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1007/BF02409402",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a radix-8 divider that uses an
                 over-redundant digit set for the quotient in order to
                 obtain simple digit selection rules. We show that the
                 proposed enlarged set of values for the quotient digit
                 does not lead to increases both in the complexity and
                 the delay of the adder required to update the
                 remainder, with respect to similar solutions, since the
                 values allowed for the quotient digit have been
                 selected carefully. The digit selection process is
                 subdivided into two concurrent steps, each one making
                 reference to a secondary digit set and the resulting
                 implementation can be cheaper and faster than other
                 units which do not use over-redundant digit sets. A
                 performance analysis estimates a speed improvement from
                 25\% to 35\% with respect to a radix-8 architecture by
                 Fandrianto (1987, 1989), and from 21\% to 30\% with
                 respect to a radix-4 architecture with prescaling,
                 presented by Ercegovac and Lang (1990). As required
                 from the IEEE 754 floating point standard, the proposed
                 algorithm features the correct remainder of the
                 division.",
  acknowledgement = ack-nhfb,
  affiliation =  "Dipartimento di Autom. e Inf., Politecnico di Torino,
                 Italy",
  classification = "B1265B (Logic circuits); C5120 (Logic and switching
                 circuits); C5230 (Digital arithmetic methods)",
  fjournal =     "Journal of VLSI Signal Processing",
  keywords =     "Algorithm; Delay; Digit selection rules; IEEE 754
                 floating point standard; Over-redundant digit set;
                 Performance analysis; Quotient; Radix-8 divider;
                 Radix-8 division; Remainder; Speed improvement",
  pubcountry =   "Netherlands",
  thesaurus =    "Digital arithmetic; Dividing circuits",
}


bibtype: article
filename: fparith.bib
label: Montuschi:1994:RDS
author: P. Montuschi and L. Ciminiera
title: Over-redundant digit sets and the design of digit-by-digit division units
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 3
pages: 269--277
month: mar
monthnumber: 3
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.272428
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:54 MDT 2011
bibtimestamp: 2011.07.07 07:13:54 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=272428
fjournal: IEEE Transactions on Computers
acknowledgement: ack-sfo
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: P. Montuschi and L. Ciminiera
rawtitle: Over-redundant digit sets and the design of digit-by-digit division units
entry:
@Article{Montuschi:1994:RDS,
  author =       "P. Montuschi and L. Ciminiera",
  title =        "Over-redundant digit sets and the design of
                 digit-by-digit division units",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "3",
  pages =        "269--277",
  month =        mar,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.272428",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:54 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=272428",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Muller:1994:SCF
author: Jean-Michel Muller
title: Some characterizations of functions computable in on-line arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 6
pages: 752--755
month: jun
monthnumber: 6
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.286308
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:56 MDT 2011
bibtimestamp: 2011.07.07 07:13:56 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=286308
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Jean-Michel Muller
rawtitle: Some characterizations of functions computable in on-line arithmetic
entry:
@Article{Muller:1994:SCF,
  author =       "Jean-Michel Muller",
  title =        "Some characterizations of functions computable in
                 on-line arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "6",
  pages =        "752--755",
  month =        jun,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.286308",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:56 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=286308",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Murofushi:1994:RBR
author: Makoto Murofushi and Hideko Nagasaka
title: The relationship between the round-off errors and Moller's algorithm in the extrapolation method
journal: j-ANN-NUM-MATH
volume: 1
number: 1--4
pages: 451--458
year: 1994
ISSN: 1021-2655 OR 10212655
ISSNL: 1021-2655 OR 10212655
MRclass: 65L05 (65L70)
MRnumber: 1340673
MRreviewer: Haydar Ak\c{c}a
bibdate: Sat Feb 08 09:16:09 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 09:16:09 ???
note: Scientific computation and differential equations (Auckland, 1993).
fjournal: Annals of Numerical Mathematics
acknowledgement: ack-nhfb
ajournal: Ann. Numer. Math.
rawauthor: Makoto Murofushi and Hideko Nagasaka
rawnote: Scientific computation and differential equations (Auckland, 1993).
rawtitle:
The relationship between the round-off errors and {M{\o}ller}'s algorithm in the extrapolation method

entry:
@Article{Murofushi:1994:RBR,
  author =       "Makoto Murofushi and Hideko Nagasaka",
  title =        "The relationship between the round-off errors and
                 {M{\o}ller}'s algorithm in the extrapolation method",
  journal =      j-ANN-NUM-MATH,
  volume =       "1",
  number =       "1--4",
  pages =        "451--458",
  year =         "1994",
  ISSN =         "1021-2655",
  ISSN-L =       "1021-2655",
  MRclass =      "65L05 (65L70)",
  MRnumber =     "1340673",
  MRreviewer =   "Haydar Ak\c{c}a",
  bibdate =      "Sat Feb 08 09:16:09 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Scientific computation and differential equations
                 (Auckland, 1993).",
  acknowledgement = ack-nhfb,
  ajournal =     "Ann. Numer. Math.",
  fjournal =     "Annals of Numerical Mathematics",
}


bibtype: inproceedings
filename: fparith.bib
label: Nakamura:1994:EPV
author: H. Nakamura and H. Imori and Y. Yamashita and K. Nakazawa and T. Boku and H. Li and I. Nakata
title: Evaluation of pseudo vector processor based on slide-windowed registers
crossref: Mudge:1994:PTS
pages: 368--377
year: 1994
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
acknowledgement: ack-nhfb
affiliation: Inst. of Inf. Sci. and Electron., Tsukuba University, Ibaraki, Japan
thesaurus: FORTRAN; Performance evaluation; Vector processor systems
rawauthor: H. Nakamura and H. Imori and Y. Yamashita and K. Nakazawa and T. Boku and H. Li and I. Nakata
rawtitle: Evaluation of pseudo vector processor based on slide-windowed registers
abstract:
We present a new scalar processor for high-speed vector processing and its evaluation. The proposed processor can hide long main memory access latency by introducing slide-windowed floating-point registers with data preloading feature and pipelined memory. Owing to the slide-window structure, the proposed processor can utilize more floating-point registers in keeping upward compatibility with existing scalar architecture. We have evaluated its performance on Livermore Fortran Kernels. The evaluation results show that the proposed processor drastically reduces the penalty of main memory access compared with an ordinary scalar processor. For example, the proposed processor with 96 registers hides memory access latency of 70 CPU cycles when the throughput of main memory is 8 byte/cycle. From these results, it is concluded that the proposed architecture is very suitable for high-speed vector processing.

keywords:
Data preloading feature; Floating-point registers; High-speed vector processing; Livermore Fortran Kernels; Performance; Pipelined memory; Pseudo vector processor; Scalar processor; Slide-windowed registers

rawabstract:
We present a new scalar processor for high-speed vector processing and its evaluation. The proposed processor can hide long main memory access latency by introducing slide-windowed floating-point registers with data preloading feature and pipelined memory. Owing to the slide-window structure, the proposed processor can utilize more floating-point registers in keeping upward compatibility with existing scalar architecture. We have evaluated its performance on Livermore Fortran Kernels. The evaluation results show that the proposed processor drastically reduces the penalty of main memory access compared with an ordinary scalar processor. For example, the proposed processor with 96 registers hides memory access latency of 70 CPU cycles when the throughput of main memory is 8 byte/cycle. From these results, it is concluded that the proposed architecture is very suitable for high-speed vector processing.

entry:
@InProceedings{Nakamura:1994:EPV,
  author =       "H. Nakamura and H. Imori and Y. Yamashita and K.
                 Nakazawa and T. Boku and H. Li and I. Nakata",
  title =        "Evaluation of pseudo vector processor based on
                 slide-windowed registers",
  crossref =     "Mudge:1994:PTS",
  pages =        "368--377",
  year =         "1994",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a new scalar processor for high-speed
                 vector processing and its evaluation. The proposed
                 processor can hide long main memory access latency by
                 introducing slide-windowed floating-point registers
                 with data preloading feature and pipelined memory.
                 Owing to the slide-window structure, the proposed
                 processor can utilize more floating-point registers in
                 keeping upward compatibility with existing scalar
                 architecture. We have evaluated its performance on
                 Livermore Fortran Kernels. The evaluation results show
                 that the proposed processor drastically reduces the
                 penalty of main memory access compared with an ordinary
                 scalar processor. For example, the proposed processor
                 with 96 registers hides memory access latency of 70 CPU
                 cycles when the throughput of main memory is 8
                 byte/cycle. From these results, it is concluded that
                 the proposed architecture is very suitable for
                 high-speed vector processing.",
  acknowledgement = ack-nhfb,
  affiliation =  "Inst. of Inf. Sci. and Electron., Tsukuba University,
                 Ibaraki, Japan",
  classification = "C5220P (Parallel architecture); C5440
                 (Multiprocessor systems and techniques); C5470
                 (Performance evaluation and testing)",
  keywords =     "Data preloading feature; Floating-point registers;
                 High-speed vector processing; Livermore Fortran
                 Kernels; Performance; Pipelined memory; Pseudo vector
                 processor; Scalar processor; Slide-windowed registers",
  thesaurus =    "FORTRAN; Performance evaluation; Vector processor
                 systems",
}


bibtype: article
filename: fparith.bib
label: Narayanaswami:1994:AE
author: Chandrasekhar Narayanaswami and William Luken
title: Approximating $ x^n $ efficiently
journal: j-INFO-PROC-LETT
volume: 50
number: 4
pages: 205--210
day: 25
month: may
monthnumber: 5
year: 1994
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
MRclass: 65D20 (41-04 65B99)
MRnumber: 95b:65031
bibdate: Wed Nov 11 12:16:26 MST 1998
bibtimestamp: 1998.11.11 12:16:26 MST
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
affiliation: IBM Advanced Workstations and Systems Div
affiliationaddress: Austin, TX, USA
corpsource: IBM Adv. Workstations and Syst. Div., Austin, TX, USA
journalURL: http://www.sciencedirect.com/science/journal/00200190
journalabr: Inf Process Lett
treatment: T Theoretical or Mathematical
rawauthor: Chandrasekhar Narayanaswami and William Luken
rawtitle: Approximating $ x^n $ efficiently
bibsource:
Compendex database; http://www.elsevier.com:80/inca/publications/store/5/0/5/6/1/2/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
$x^n$ approximation; approximation theory; Approximation theory; Color computer graphics; Computational complexity; Computational methods; computer graphics; elementary functions; floating-point arithmetic; Function evaluation; graphics modeling; Image quality; Light intensity computation; look-up tables; performance requirements; Polynomial evaluation; Polynomials; polynomials; power function; scientific applications; Semiconducting silicon; Table lookup

entry:
@Article{Narayanaswami:1994:AE,
  author =       "Chandrasekhar Narayanaswami and William Luken",
  title =        "Approximating $ x^n $ efficiently",
  journal =      j-INFO-PROC-LETT,
  volume =       "50",
  number =       "4",
  pages =        "205--210",
  day =          "25",
  month =        may,
  year =         "1994",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  MRclass =      "65D20 (41-04 65B99)",
  MRnumber =     "95b:65031",
  bibdate =      "Wed Nov 11 12:16:26 MST 1998",
  bibsource =    "Compendex database;
                 http://www.elsevier.com:80/inca/publications/store/5/0/5/6/1/2/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Advanced Workstations and Systems Div",
  affiliationaddress = "Austin, TX, USA",
  classification = "721.1; 723.2; 723.5; 741.2; 921.1; 921.6; B0290F
                 (Interpolation and function approximation); C4130
                 (Interpolation and function approximation); C6130B
                 (Graphics techniques)",
  corpsource =   "IBM Adv. Workstations and Syst. Div., Austin, TX,
                 USA",
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
  journalabr =   "Inf Process Lett",
  keywords =     "$x^n$ approximation; approximation theory;
                 Approximation theory; Color computer graphics;
                 Computational complexity; Computational methods;
                 computer graphics; elementary functions; floating-point
                 arithmetic; Function evaluation; graphics modeling;
                 Image quality; Light intensity computation; look-up
                 tables; performance requirements; Polynomial
                 evaluation; Polynomials; polynomials; power function;
                 scientific applications; Semiconducting silicon; Table
                 lookup",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: mastersthesis
filename: fparith.bib
label: Nedialkov:1994:PCE
author: Nedialko (Ned) Stoyanov Nedialkov
title: Precision Control and Exception Handling in Scientific Computing
type: M.Sc. Thesis
school: Department of Computer Science, University of Toronto
address: Toronto, ON, Canada
pages: 51
year: 1994
bibdate: Tue May 22 15:44:16 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.05.22 15:44:16 ???
acknowledgement: ack-nhfb
rawauthor: Nedialko (Ned) Stoyanov Nedialkov
rawtitle: Precision Control and Exception Handling in Scientific Computing
URL:
http://www.cs.toronto.edu/NA/reports.html#ned-94-msc; http://www.cs.toronto.edu/pub/reports/na/ned-94-msc.ps.Z

entry:
@MastersThesis{Nedialkov:1994:PCE,
  author =       "Nedialko (Ned) Stoyanov Nedialkov",
  title =        "Precision Control and Exception Handling in Scientific
                 Computing",
  type =         "{M.Sc.} Thesis",
  school =       "Department of Computer Science, University of
                 Toronto",
  address =      "Toronto, ON, Canada",
  pages =        "51",
  year =         "1994",
  bibdate =      "Tue May 22 15:44:16 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.toronto.edu/NA/reports.html#ned-94-msc;
                 http://www.cs.toronto.edu/pub/reports/na/ned-94-msc.ps.Z",
  acknowledgement = ack-nhfb,
}


bibtype: mastersthesis
filename: fparith.bib
label: Niescier:1994:DIC
author: Richard J. Niescier
title: Design of an IEEE compliant 32-bit floating point multiplier / accumulator
type: Thesis (M.S.)
school: Lehigh University
address: Bethlehem, PA, USA
pages: vii + 94
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Floating-point arithmetic.; Microprocessors.
acknowledgement: ack-nhfb
rawauthor: Richard J. Niescier
rawtitle: Design of an {IEEE} compliant 32-bit floating point multiplier\slash accumulator
entry:
@MastersThesis{Niescier:1994:DIC,
  author =       "Richard J. Niescier",
  title =        "Design of an {IEEE} compliant 32-bit floating point
                 multiplier\slash accumulator",
  type =         "Thesis ({M.S.})",
  school =       "Lehigh University",
  address =      "Bethlehem, PA, USA",
  pages =        "vii + 94",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Floating-point arithmetic.; Microprocessors.",
}


bibtype: mastersthesis
filename: fparith.bib
label: Novak:1994:AFP
author: Joseph Herschel Novak
title: An asynchronous floating point unit
type: Thesis (M.S.)
school: Department of Computer Science, University of Utah
address: Salt Lake City, UT, USA
pages: xi + 151
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Asynchronous circuits.; Computers --- Circuits.; Floating-point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Joseph Herschel Novak
rawtitle: An asynchronous floating point unit
entry:
@MastersThesis{Novak:1994:AFP,
  author =       "Joseph Herschel Novak",
  title =        "An asynchronous floating point unit",
  type =         "Thesis ({M.S.})",
  school =       "Department of Computer Science, University of Utah",
  address =      "Salt Lake City, UT, USA",
  pages =        "xi + 151",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Asynchronous circuits.; Computers --- Circuits.;
                 Floating-point arithmetic.",
}


bibtype: techreport
filename: fparith.bib
label: Oberman:1994:DIH
author: S. Oberman and N. Quach and M. Flynn
title: The design and implementation of a high-performance floating-point divider
type: Technical Report
number: CSL-TR-94-599
institution: Computer Systems Laboratory, Stanford University
address: Stanford, CA, USA
pages: xi + 151
month: jan
monthnumber: 1
year: 1994
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
acknowledgement: ack-sfo
rawauthor: S. Oberman and N. Quach and M. Flynn
rawtitle: The design and implementation of a high-performance floating-point divider
entry:
@TechReport{Oberman:1994:DIH,
  author =       "S. Oberman and N. Quach and M. Flynn",
  title =        "The design and implementation of a high-performance
                 floating-point divider",
  type =         "Technical Report",
  number =       "CSL-TR-94-599",
  institution =  "Computer Systems Laboratory, Stanford University",
  address =      "Stanford, CA, USA",
  month =        jan,
  year =         "1994",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Oh:1994:IPDa
author: S. Oh and D. Garcia
title: Implementation of a parallel DFE using residue number system
volume: 3
publisher: pub-IEEE
address: pub-IEEE:adr
pages: III/237--III/240
year: 1994
DOI: https://doi.org/10.1109/ICASSP.1994.390024
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: S. Oh and D. Garcia
rawtitle: Implementation of a parallel {DFE} using residue number system
booktitle:
IEEE International Conference on Acoustics, Speech, and Signal Processing. ICASSP-94, 19--22 April 1994

rawbooktitle:
{IEEE} International Conference on Acoustics, Speech, and Signal Processing. {ICASSP-94, 19--22} April 1994

entry:
@InProceedings{Oh:1994:IPDa,
  author =       "S. Oh and D. Garcia",
  booktitle =    "{IEEE} International Conference on Acoustics, Speech,
                 and Signal Processing. {ICASSP-94, 19--22} April 1994",
  title =        "Implementation of a parallel {DFE} using residue
                 number system",
  volume =       "3",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "III/237--III/240",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1994.390024",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A parallel decision feedback equalizer (DFE)
                 implementation using residue number system (RNS) is
                 considered When the DFE implementation for a system
                 requires a wide input data width and high sampling
                 rates, RNS provides a speed advantage over \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Oh:1994:IPDb
author: S. Oh and D. Garcia
title: Implementation of a parallel DFE using residue number system
volume: 3
publisher: pub-IEEE
address: pub-IEEE:adr
pages: III/237--III/240
year: 1994
DOI: https://doi.org/10.1109/ICASSP.1994.390024
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: S. Oh and D. Garcia
rawtitle: Implementation of a parallel {DFE} using residue number system
booktitle:
IEEE International Conference on Acoustics, Speech, and Signal Processing. ICASSP-94, 19--22 April 1994

rawbooktitle:
{IEEE} International Conference on Acoustics, Speech, and Signal Processing. {ICASSP-94, 19--22} April 1994

entry:
@InProceedings{Oh:1994:IPDb,
  author =       "S. Oh and D. Garcia",
  booktitle =    "{IEEE} International Conference on Acoustics, Speech,
                 and Signal Processing. {ICASSP-94, 19--22} April 1994",
  title =        "Implementation of a parallel {DFE} using residue
                 number system",
  volume =       "3",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "III/237--III/240",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1994.390024",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A parallel decision feedback equalizer (DFE)
                 implementation using residue number system (RNS) is
                 considered When the DFE implementation for a system
                 requires a wide input data width and high sampling
                 rates, RNS provides a speed advantage over \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Ohta:1994:INP
author: S. Ohta and E. Goto and Weng Fai Wong and N. Yoshida
title: Improvement and new proposal on fast evaluation of elementary functions
journal: j-TRANS-INFO-PROCESSING-SOC-JAPAN
volume: 35
number: 5
pages: 926--933
month: may
monthnumber: 5
year: 1994
CODEN: JSGRD5
ISSN: 0387-5806 OR 03875806
ISSNL: 0387-5806 OR 03875806
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: Transactions of the Information Processing Society of Japan
language: Japanese
acknowledgement: ack-nhfb
affiliation: RIKEN, Inst. of Phys. and Chem. Res., Saitama, Japan
thesaurus: Digital arithmetic; Function evaluation; Random number generation; Table lookup
rawauthor: S. Ohta and E. Goto and Weng Fai Wong and N. Yoshida
rawtitle: Improvement and new proposal on fast evaluation of elementary functions
abstract:
Wong, Gore, and Yoshida (ibid., vol. 34, no. 7, pp. 1570-1579, 1993) introduced fast methods for numerical evaluation of elementary functions based on table lookup. They are called ATA (add/table-lookup/add) and ATA-M (add/table-lookup/add and multiply) methods for single- and double-precision calculations respectively. In this paper, an improvement to these methods that shrinks the size of the table by a factor of about 3/16 is presented. Another method called the `split parallel multiplication method', which is characterized by simpler table lookup than ATA-M and by split and parallel use of double-precision floating point circuitry, is also introduced, These new methods fit on to integrated circuits of a size comparable with commercially available floating-point accelerators. Methods for accelerating double-precision division, generating uniform pseudo-random numbers in double-precision, and accelerating the multiplication of single-precision complex numbers using the same circuitry are proposed.

keywords:
Add/table-lookup/add method; Add/table-lookup/add/multiply method; ATA method; ATA-M method; Double-precision calculations; Double-precision division; Double-precision floating point circuitry; Elementary functions evaluation; Floating-point accelerators; Integrated circuits; Numerical evaluation; Single-precision calculations; Single-precision complex number multiplication; Split parallel multiplication method; Table size; Uniform pseudo-random number generation

rawabstract:
Wong, Gore, and Yoshida (ibid., vol. 34, no. 7, pp. 1570-1579, 1993) introduced fast methods for numerical evaluation of elementary functions based on table lookup. They are called ATA (add/table-lookup/add) and ATA-M (add/table-lookup/add and multiply) methods for single- and double-precision calculations respectively. In this paper, an improvement to these methods that shrinks the size of the table by a factor of about 3/16 is presented. Another method called the `split parallel multiplication method', which is characterized by simpler table lookup than ATA-M and by split and parallel use of double-precision floating point circuitry, is also introduced, These new methods fit on to integrated circuits of a size comparable with commercially available floating-point accelerators. Methods for accelerating double-precision division, generating uniform pseudo-random numbers in double-precision, and accelerating the multiplication of single-precision complex numbers using the same circuitry are proposed.

entry:
@Article{Ohta:1994:INP,
  author =       "S. Ohta and E. Goto and Weng Fai Wong and N. Yoshida",
  title =        "Improvement and new proposal on fast evaluation of
                 elementary functions",
  journal =      j-TRANS-INFO-PROCESSING-SOC-JAPAN,
  volume =       "35",
  number =       "5",
  pages =        "926--933",
  month =        may,
  year =         "1994",
  CODEN =        "JSGRD5",
  ISSN =         "0387-5806",
  ISSN-L =       "0387-5806",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Wong, Gore, and Yoshida (ibid., vol. 34, no. 7, pp.
                 1570-1579, 1993) introduced fast methods for numerical
                 evaluation of elementary functions based on table
                 lookup. They are called ATA (add/table-lookup/add) and
                 ATA-M (add/table-lookup/add and multiply) methods for
                 single- and double-precision calculations respectively.
                 In this paper, an improvement to these methods that
                 shrinks the size of the table by a factor of about 3/16
                 is presented. Another method called the `split parallel
                 multiplication method', which is characterized by
                 simpler table lookup than ATA-M and by split and
                 parallel use of double-precision floating point
                 circuitry, is also introduced, These new methods fit on
                 to integrated circuits of a size comparable with
                 commercially available floating-point accelerators.
                 Methods for accelerating double-precision division,
                 generating uniform pseudo-random numbers in
                 double-precision, and accelerating the multiplication
                 of single-precision complex numbers using the same
                 circuitry are proposed.",
  acknowledgement = ack-nhfb,
  affiliation =  "RIKEN, Inst. of Phys. and Chem. Res., Saitama, Japan",
  classification = "C4120 (Functional analysis); C5230 (Digital
                 arithmetic methods); C6130 (Data handling techniques)",
  fjournal =     "Transactions of the Information Processing Society of
                 Japan",
  keywords =     "Add/table-lookup/add method;
                 Add/table-lookup/add/multiply method; ATA method; ATA-M
                 method; Double-precision calculations; Double-precision
                 division; Double-precision floating point circuitry;
                 Elementary functions evaluation; Floating-point
                 accelerators; Integrated circuits; Numerical
                 evaluation; Single-precision calculations;
                 Single-precision complex number multiplication; Split
                 parallel multiplication method; Table size; Uniform
                 pseudo-random number generation",
  language =     "Japanese",
  pubcountry =   "Japan",
  thesaurus =    "Digital arithmetic; Function evaluation; Random number
                 generation; Table lookup",
}


bibtype: book
filename: fparith.bib
label: Omondi:1994:CAS
author: Amos R. Omondi
title: Computer Arithmetic Systems: Algorithms, Architecture, and Implementation
publisher: pub-PH
address: pub-PH:adr
pages: xvi + 520
year: 1994
ISBN: 0-13-334301-4 OR 0133343014
ISBN13: 978-0-13-334301-4 OR 9780133343014
LCCN: QA76.9.C62 O46 1994
bibdate: Sat Dec 09 11:57:03 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib
bibtimestamp: 1995.12.09 11:57:03 ???
acknowledgement: ack-nhfb
rawauthor: Amos R. Omondi
rawtitle: Computer Arithmetic Systems: Algorithms, Architecture, and Implementation
TOC:
Preface Preliminary notes Fixed-point number systems / 3 Fixed-point addition and subtraction / 13 Fixed-point multiplication / 119 Fixed-point division / 192 Floating-point number systems and arithmetic / 293 Basic floating-point operations: implementation / 345 Elementary functions / 371 Unconventional number systems and arithmetic / 439 Bibliography / 469 Appendix A: Pipelining / 489 Appendix B: Design of shifters / 505 Index / 514

rawTOC:
Preface \\ Preliminary notes \\ Fixed-point number systems / 3 \\ Fixed-point addition and subtraction / 13 \\ Fixed-point multiplication / 119 \\ Fixed-point division / 192 \\ Floating-point number systems and arithmetic / 293 \\ Basic floating-point operations: implementation / 345 \\ Elementary functions / 371 \\ Unconventional number systems and arithmetic / 439 \\ Bibliography / 469 \\ Appendix A: Pipelining / 489 \\ Appendix B: Design of shifters / 505 \\ Index / 514

entry:
@Book{Omondi:1994:CAS,
  author =       "Amos R. Omondi",
  title =        "Computer Arithmetic Systems: Algorithms, Architecture,
                 and Implementation",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "xvi + 520",
  year =         "1994",
  ISBN =         "0-13-334301-4",
  ISBN-13 =      "978-0-13-334301-4",
  LCCN =         "QA76.9.C62 O46 1994",
  bibdate =      "Sat Dec 09 11:57:03 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib",
  price =        "US\$40.00",
  acknowledgement = ack-nhfb,
  tableofcontents = "Preface \\
                 Preliminary notes \\
                 Fixed-point number systems / 3 \\
                 Fixed-point addition and subtraction / 13 \\
                 Fixed-point multiplication / 119 \\
                 Fixed-point division / 192 \\
                 Floating-point number systems and arithmetic / 293 \\
                 Basic floating-point operations: implementation / 345
                 \\
                 Elementary functions / 371 \\
                 Unconventional number systems and arithmetic / 439 \\
                 Bibliography / 469 \\
                 Appendix A: Pipelining / 489 \\
                 Appendix B: Design of shifters / 505 \\
                 Index / 514",
}


bibtype: article
filename: fparith.bib
label: Ooyama:1994:CSC
author: M. Ooyama and H. Hamada
journal: j-TRANS-INFO-PROCESSING-SOC-JAPAN
volume: 35
number: 8
pages: 1642--1651
month: aug
monthnumber: 8
year: 1994
CODEN: JSGRD5
ISSN: 0387-5806 OR 03875806
ISSNL: 0387-5806 OR 03875806
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: Transactions of the Information Processing Society of Japan
language: Japanese
acknowledgement: ack-nhfb
affiliation: Central Res. Lab., Hitachi Ltd., Tokyo, Japan
thesaurus: Combinatorial circuits; Digital arithmetic; Parallel processing; Pipeline processing
rawauthor: M. Ooyama and H. Hamada
title:
A circuit to separate and to connect the exponent part and the mantissa part for URR floating point arithmetic and its application to a URR processor

abstract:
To overcome overflows and underflows in computation, several new floating-point arithmetics have been proposed. But in these new arithmetics, a boundary between the exponent part and the mantissa part moves according to the exponent value and data formats are usually more complicated. So, fast separation and connection of the exponent and the mantissa is a key technology to achieve fast computation of these new arithmetics. In this paper, a circuit scheme to separate and connect the exponent and the mantissa for URR floating-point arithmetic based on double exponential cut is presented. To separate the exponent from the mantissa, this circuit scheme firstly detects the boundary and the position is encoded to a short code. Then barrel shifters, logical operation circuits, and bit pattern generators controlled by the code separate the exponent and the mantissa from URR. To form URR from the exponent and the mantissa, a number of bits of the exponent is counted and encoded to a short code. The boundary can be settled by this code, and using the same circuits controlled by the code, the exponent part and the mantissa part are generated and combined into URR. To achieve fast execution, these processes are executed by the combination logic circuits in bit parallel manner and meet to pipelined architectures. We applied this circuit scheme to an experimental 64 bits URR processor and verified its realization. Its performance was also evaluated. (11 Refs.)

keywords:
64 Bit; Barrel shifters; Bit parallel processing; Bit pattern generators; Combination logic circuits; Double exponential cut; Exponent part; Logical operation circuits; Mantissa part; Pipelined architectures; URR floating point arithmetic; URR processor

rawabstract:
To overcome overflows and underflows in computation, several new floating-point arithmetics have been proposed. But in these new arithmetics, a boundary between the exponent part and the mantissa part moves according to the exponent value and data formats are usually more complicated. So, fast separation and connection of the exponent and the mantissa is a key technology to achieve fast computation of these new arithmetics. In this paper, a circuit scheme to separate and connect the exponent and the mantissa for URR floating-point arithmetic based on double exponential cut is presented. To separate the exponent from the mantissa, this circuit scheme firstly detects the boundary and the position is encoded to a short code. Then barrel shifters, logical operation circuits, and bit pattern generators controlled by the code separate the exponent and the mantissa from URR. To form URR from the exponent and the mantissa, a number of bits of the exponent is counted and encoded to a short code. The boundary can be settled by this code, and using the same circuits controlled by the code, the exponent part and the mantissa part are generated and combined into URR. To achieve fast execution, these processes are executed by the combination logic circuits in bit parallel manner and meet to pipelined architectures. We applied this circuit scheme to an experimental 64 bits URR processor and verified its realization. Its performance was also evaluated. (11 Refs.)

rawtitle:
A circuit to separate and to connect the exponent part and the mantissa part for {URR} floating point arithmetic and its application to a {URR} processor

entry:
@Article{Ooyama:1994:CSC,
  author =       "M. Ooyama and H. Hamada",
  title =        "A circuit to separate and to connect the exponent part
                 and the mantissa part for {URR} floating point
                 arithmetic and its application to a {URR} processor",
  journal =      j-TRANS-INFO-PROCESSING-SOC-JAPAN,
  volume =       "35",
  number =       "8",
  pages =        "1642--1651",
  month =        aug,
  year =         "1994",
  CODEN =        "JSGRD5",
  ISSN =         "0387-5806",
  ISSN-L =       "0387-5806",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "To overcome overflows and underflows in computation,
                 several new floating-point arithmetics have been
                 proposed. But in these new arithmetics, a boundary
                 between the exponent part and the mantissa part moves
                 according to the exponent value and data formats are
                 usually more complicated. So, fast separation and
                 connection of the exponent and the mantissa is a key
                 technology to achieve fast computation of these new
                 arithmetics. In this paper, a circuit scheme to
                 separate and connect the exponent and the mantissa for
                 URR floating-point arithmetic based on double
                 exponential cut is presented. To separate the exponent
                 from the mantissa, this circuit scheme firstly detects
                 the boundary and the position is encoded to a short
                 code. Then barrel shifters, logical operation circuits,
                 and bit pattern generators controlled by the code
                 separate the exponent and the mantissa from URR. To
                 form URR from the exponent and the mantissa, a number
                 of bits of the exponent is counted and encoded to a
                 short code. The boundary can be settled by this code,
                 and using the same circuits controlled by the code, the
                 exponent part and the mantissa part are generated and
                 combined into URR. To achieve fast execution, these
                 processes are executed by the combination logic
                 circuits in bit parallel manner and meet to pipelined
                 architectures. We applied this circuit scheme to an
                 experimental 64 bits URR processor and verified its
                 realization. Its performance was also evaluated. (11
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Central Res. Lab., Hitachi Ltd., Tokyo, Japan",
  classification = "B1265B (Logic circuits); C5120 (Logic and switching
                 circuits); C5220P (Parallel architecture); C5230
                 (Digital arithmetic methods)",
  fjournal =     "Transactions of the Information Processing Society of
                 Japan",
  keywords =     "64 Bit; Barrel shifters; Bit parallel processing; Bit
                 pattern generators; Combination logic circuits; Double
                 exponential cut; Exponent part; Logical operation
                 circuits; Mantissa part; Pipelined architectures; URR
                 floating point arithmetic; URR processor",
  language =     "Japanese",
  numericalindex = "Word length 6.4E+01 bit",
  pubcountry =   "Japan",
  thesaurus =    "Combinatorial circuits; Digital arithmetic; Parallel
                 processing; Pipeline processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Paliouras:1994:SDMa
author: V. Paliouras and T. Stouraitis
booktitle: IEEE International Symposium on Circuits and Systems, ISCAS '94, 2 June 1994
title: Systematic design of multi-modulus / multi-function Residue Number System processors
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 79--82
year: 1994
DOI: https://doi.org/10.1109/ISCAS.1994.409201
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: V. Paliouras and T. Stouraitis
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, {ISCAS '94}, 2 June 1994
rawtitle: Systematic design of multi-modulus\slash multi-function {Residue Number System} processors
entry:
@InProceedings{Paliouras:1994:SDMa,
  author =       "V. Paliouras and T. Stouraitis",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, {ISCAS '94}, 2 June 1994",
  title =        "Systematic design of multi-modulus\slash
                 multi-function {Residue Number System} processors",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "79--82",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1994.409201",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A methodology for the design of novel Residue Number
                 System (RNS) processors is presented. It results in
                 ROM-less processors, which perform basic residue
                 arithmetic algorithms in more than one moduli channel,
                 either serially or concurrently. \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Paliouras:1994:SDMb
author: V. Paliouras and T. Stouraitis
booktitle: IEEE International Symposium on Circuits and Systems, ISCAS '94, 2 June 1994
title: Systematic design of multi-modulus / multi-function Residue Number System processors
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 79--82
year: 1994
DOI: https://doi.org/10.1109/ISCAS.1994.409201
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: V. Paliouras and T. Stouraitis
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, {ISCAS '94}, 2 June 1994
rawtitle: Systematic design of multi-modulus\slash multi-function {Residue Number System} processors
entry:
@InProceedings{Paliouras:1994:SDMb,
  author =       "V. Paliouras and T. Stouraitis",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, {ISCAS '94}, 2 June 1994",
  title =        "Systematic design of multi-modulus\slash
                 multi-function {Residue Number System} processors",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "79--82",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1994.409201",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A methodology for the design of novel Residue Number
                 System (RNS) processors is presented. It results in
                 ROM-less processors, which perform basic residue
                 arithmetic algorithms in more than one moduli channel,
                 either serially or concurrently. \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Parhami:1994:OTLa
author: B. Parhami and C. Y. Hung
booktitle: Workshop on VLSI Signal Processing, VII, 1994
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 470--481
year: 1994
DOI: https://doi.org/10.1109/VLSISP.1994.574771
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: B. Parhami and C. Y. Hung
rawbooktitle: Workshop on {VLSI} Signal Processing, {VII, 1994}
title:
Optimal table lookup schemes for VLSI implementation of input / output conversions and other residue number operations

rawtitle:
Optimal table lookup schemes for {VLSI} implementation of input\slash output conversions and other residue number operations

entry:
@InProceedings{Parhami:1994:OTLa,
  author =       "B. Parhami and C. Y. Hung",
  booktitle =    "Workshop on {VLSI} Signal Processing, {VII, 1994}",
  title =        "Optimal table lookup schemes for {VLSI} implementation
                 of input\slash output conversions and other residue
                 number operations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "470--481",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/VLSISP.1994.574771",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Residue number representation has become a viable
                 alternative for fast, area-efficient VLSI realization
                 of high-performance signal processing hardware. Wider
                 applicability and improved cost/performance of
                 residue-based VLSI implementations of signal \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Parhami:1994:OTLb
author: B. Parhami and C. Y. Hung
booktitle: Workshop on VLSI Signal Processing, VII, 1994
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 470--481
year: 1994
DOI: https://doi.org/10.1109/VLSISP.1994.574771
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: B. Parhami and C. Y. Hung
rawbooktitle: Workshop on {VLSI} Signal Processing, {VII, 1994}
title:
Optimal table lookup schemes for VLSI implementation of input / output conversions and other residue number operations

rawtitle:
Optimal table lookup schemes for {VLSI} implementation of input\slash output conversions and other residue number operations

entry:
@InProceedings{Parhami:1994:OTLb,
  author =       "B. Parhami and C. Y. Hung",
  booktitle =    "Workshop on {VLSI} Signal Processing, {VII, 1994}",
  title =        "Optimal table lookup schemes for {VLSI} implementation
                 of input\slash output conversions and other residue
                 number operations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "470--481",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/VLSISP.1994.574771",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Residue number representation has become a viable
                 alternative for fast, area-efficient VLSI realization
                 of high-performance signal processing hardware. Wider
                 applicability and improved cost/performance of
                 residue-based VLSI implementations of signal \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Parker:1994:FTLa
author: M. G. Parker and M. Benaissa
booktitle: IEEE International Symposium on Circuits and Systems, ISCAS '94, 2 June 1994
title: Fault-tolerant linear convolution using residue number systems
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 441--444
year: 1994
DOI: https://doi.org/10.1109/ISCAS.1994.408997
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. G. Parker and M. Benaissa
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, {ISCAS '94}, 2 June 1994
rawtitle: Fault-tolerant linear convolution using residue number systems
entry:
@InProceedings{Parker:1994:FTLa,
  author =       "M. G. Parker and M. Benaissa",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, {ISCAS '94}, 2 June 1994",
  title =        "Fault-tolerant linear convolution using residue number
                 systems",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "441--444",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1994.408997",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "This paper proposes a fault-tolerant linear
                 convolution architecture using Residue Number Systems
                 (RNS) and Polynomial Residue Number Systems (PRNS). The
                 RNS and PRNS are both given error-detection capability
                 by the addition of redundant residue \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Parker:1994:FTLb
author: M. G. Parker and M. Benaissa
booktitle: IEEE International Symposium on Circuits and Systems, ISCAS '94, 2 June 1994
title: Fault-tolerant linear convolution using residue number systems
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 441--444
year: 1994
DOI: https://doi.org/10.1109/ISCAS.1994.408997
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. G. Parker and M. Benaissa
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, {ISCAS '94}, 2 June 1994
rawtitle: Fault-tolerant linear convolution using residue number systems
entry:
@InProceedings{Parker:1994:FTLb,
  author =       "M. G. Parker and M. Benaissa",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, {ISCAS '94}, 2 June 1994",
  title =        "Fault-tolerant linear convolution using residue number
                 systems",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "441--444",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1994.408997",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "This paper proposes a fault-tolerant linear
                 convolution architecture using Residue Number Systems
                 (RNS) and Polynomial Residue Number Systems (PRNS). The
                 RNS and PRNS are both given error-detection capability
                 by the addition of redundant residue \ldots{}",
}


bibtype: mastersthesis
filename: fparith.bib
label: Patankar:1994:SHA
author: Rashmi Arun Patankar
title: Software and hardware approaches to data compression of IEEE 64-bit floating point data
type: Thesis (M.S.)
school: Iowa State University
address: Ames, IA, USA
pages: 55
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Rashmi Arun Patankar
rawtitle: Software and hardware approaches to data compression of {IEEE} 64-bit floating point data
entry:
@MastersThesis{Patankar:1994:SHA,
  author =       "Rashmi Arun Patankar",
  title =        "Software and hardware approaches to data compression
                 of {IEEE} 64-bit floating point data",
  type =         "Thesis ({M.S.})",
  school =       "Iowa State University",
  address =      "Ames, IA, USA",
  pages =        "55",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Phatak:1994:HSD
author: D. S. Phatak and I. Koren
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 880--891
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295850
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:16:49 MDT
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. S. Phatak and I. Koren
title:
Hybrid Signed-Digit Number Systems: a Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains

rawtitle:
Hybrid Signed-Digit Number Systems: a Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains

entry:
@Article{Phatak:1994:HSD,
  author =       "D. S. Phatak and I. Koren",
  title =        "Hybrid Signed-Digit Number Systems: a Unified
                 Framework for Redundant Number Representations With
                 Bounded Carry Propagation Chains",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "880--891",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295850",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: article
filename: fparith.bib
label: Popova:1994:EIA
author: Evgenija D. Popova
title: Extended interval arithmetic in IEEE floating-point environment
journal: j-INTERVAL-COMP
volume: 4
pages: 100--129
year: 1994
ISSN: 0135-4868 OR 01354868
MRclass: 65-04 (65G10)
MRnumber: 1 332 078
bibdate: Fri Dec 8 08:24:14 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:14 ???
fjournal: Interval Computations = Interval'nye vychisleniia
acknowledgement: ack-nhfb
rawauthor: Evgenija D. Popova
rawtitle: Extended interval arithmetic in {IEEE} floating-point environment
entry:
@Article{Popova:1994:EIA,
  author =       "Evgenija D. Popova",
  title =        "Extended interval arithmetic in {IEEE} floating-point
                 environment",
  journal =      j-INTERVAL-COMP,
  volume =       "4",
  pages =        "100--129",
  year =         "1994",
  ISSN =         "0135-4868",
  MRclass =      "65-04 (65G10)",
  MRnumber =     "1 332 078",
  bibdate =      "Fri Dec 8 08:24:14 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Interval Computations = Interval'nye vychisleniia",
  xxnote =       "SCAN-93 (Vienna, 1993)",
}


bibtype: article
filename: fparith.bib
label: Prince:1994:TFM
author: Timothy Prince
title: tt float-Precision Math Library
journal: j-CUJ
volume: 12
number: 6
pages: 45--??
month: jun
monthnumber: 6
year: 1994
ISSN: 0898-9788 OR 08989788
bibdate: Fri Aug 30 16:52:23 MDT 1996
bibsource: http://www.cuj.com/cbklist.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.08.30 16:52:23 MDT
fjournal: C Users Journal
acknowledgement: ack-nhfb
rawauthor: Timothy Prince
rawtitle: {{\tt float}}-Precision Math Library
entry:
@Article{Prince:1994:TFM,
  author =       "Timothy Prince",
  title =        "{{\tt float}}-Precision Math Library",
  journal =      j-CUJ,
  volume =       "12",
  number =       "6",
  pages =        "45--??",
  month =        jun,
  year =         "1994",
  ISSN =         "0898-9788",
  bibdate =      "Fri Aug 30 16:52:23 MDT 1996",
  bibsource =    "http://www.cuj.com/cbklist.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "C Users Journal",
}


bibtype: article
filename: fparith.bib
label: Pritchard:1994:RAR
author: A. J. Pritchard and S. J. Sangwine and R. E. N. Horne
title: Rational arithmetic representation of colour image pixels
journal: j-ELECT-LETTERS
volume: 30
number: 18
pages: 1474--1475
month: sep
monthnumber: 9
year: 1994
CODEN: ELLEAK
ISSN: 0013-5194 (print), 1350-911X (electronic) OR 00135194 (print), 1350911X (electronic)
ISSNL: 0013-5194 OR 00135194
bibdate: Fri Nov 30 07:42:41 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.30 07:42:41 ???
fjournal: Electronics Letters
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220
rawauthor: A. J. Pritchard and S. J. Sangwine and R. E. N. Horne
rawtitle: Rational arithmetic representation of colour image pixels
entry:
@Article{Pritchard:1994:RAR,
  author =       "A. J. Pritchard and S. J. Sangwine and R. E. N.
                 Horne",
  title =        "Rational arithmetic representation of colour image
                 pixels",
  journal =      j-ELECT-LETTERS,
  volume =       "30",
  number =       "18",
  pages =        "1474--1475",
  month =        sep,
  year =         "1994",
  CODEN =        "ELLEAK",
  ISSN =         "0013-5194 (print), 1350-911X (electronic)",
  ISSN-L =       "0013-5194",
  bibdate =      "Fri Nov 30 07:42:41 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronics Letters",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220",
}


bibtype: inproceedings
filename: fparith.bib
label: Rajski:1994:DRP
author: J. Rajski and J. Tyszer
title: Design of random pattern testable floating point adders
crossref: IEEE:1994:PTA
pages: 227--232
year: 1994
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
acknowledgement: ack-nhfb
affiliation: Department of Electr. Eng., McGill University, Montreal, Que., Canada
rawauthor: J. Rajski and J. Tyszer
rawtitle: Design of random pattern testable floating point adders
abstract:
The paper presents a floating point adder with enhanced testability and test response compaction capabilities. It is shown that the testability of the conventional adders can be improved by changing the functionality of some of their internal modules in the testing mode. It is also demonstrated that the floating point units can perform an efficient test response compaction in a built-in self test environment. (7 Refs.)

keywords:
built-in self test environment; enhanced testability; floating point accumulator; floating point units; floating-point testing; functionality; internal modules; random pattern testable floating point adders; rotate shifter; simulation experiments; test response compaction; testability

thesaurus:
adders; built-in self test; design for testability; digital simulation; floating point arithmetic; logic design; modules; shift registers

rawabstract:
The paper presents a floating point adder with enhanced testability and test response compaction capabilities. It is shown that the testability of the conventional adders can be improved by changing the functionality of some of their internal modules in the testing mode. It is also demonstrated that the floating point units can perform an efficient test response compaction in a built-in self test environment. (7 Refs.)

entry:
@InProceedings{Rajski:1994:DRP,
  author =       "J. Rajski and J. Tyszer",
  title =        "Design of random pattern testable floating point
                 adders",
  crossref =     "IEEE:1994:PTA",
  pages =        "227--232",
  year =         "1994",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The paper presents a floating point adder with
                 enhanced testability and test response compaction
                 capabilities. It is shown that the testability of the
                 conventional adders can be improved by changing the
                 functionality of some of their internal modules in the
                 testing mode. It is also demonstrated that the floating
                 point units can perform an efficient test response
                 compaction in a built-in self test environment. (7
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. Eng., McGill University,
                 Montreal, Que., Canada",
  classification = "B0170E (Production facilities and engineering);
                 B1265B (Logic circuits); B7210B (Automatic test and
                 measurement systems); C5120 (Logic and switching
                 circuits); C5210 (Logic design methods); C5230 (Digital
                 arithmetic methods); C7410D (Electronic engineering
                 computing)",
  keywords =     "built-in self test environment; enhanced testability;
                 floating point accumulator; floating point units;
                 floating-point testing; functionality; internal
                 modules; random pattern testable floating point adders;
                 rotate shifter; simulation experiments; test response
                 compaction; testability",
  thesaurus =    "adders; built-in self test; design for testability;
                 digital simulation; floating point arithmetic; logic
                 design; modules; shift registers",
}


bibtype: mastersthesis
filename: fparith.bib
label: Robe:1994:SME
author: Edward D. Robe
type: Thesis (M.S.)
school: Ohio University
address: Athens, OH, USA
pages: v + 130
month: jun
monthnumber: 6
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Digital control systems.; Emulators (Computer programs); Floating-point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Edward D. Robe
title:
SIMULINK modules that emulate digital controllers realized with fixed-point or floating-point arithmetic

rawtitle:
{SIMULINK} modules that emulate digital controllers realized with fixed-point or floating-point arithmetic

entry:
@MastersThesis{Robe:1994:SME,
  author =       "Edward D. Robe",
  title =        "{SIMULINK} modules that emulate digital controllers
                 realized with fixed-point or floating-point
                 arithmetic",
  type =         "Thesis ({M.S.})",
  school =       "Ohio University",
  address =      "Athens, OH, USA",
  pages =        "v + 130",
  month =        jun,
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Digital control systems.; Emulators (Computer
                 programs); Floating-point arithmetic.",
}


bibtype: techreport
filename: fparith.bib
label: Rothberg:1994:ILD
author: Edward Rothberg and Robert Schreiber
title: Improved load distribution in parallel sparse Cholesky factorization
address: Moffett Field, CA, USA
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Edward Rothberg and Robert Schreiber
rawtitle: Improved load distribution in parallel sparse {Cholesky} factorization
institution:
Research Institute for Advanced Computer Science, NASA Ames Research Center; National Technical Information Service, distributor

series:
[NASA contractor report]; NASA CR-196380 RIACS technical report; 94.13 RIACS technical report; TR 94.13.

keywords:
Cholesky factorization.; Computer systems performance.; Floating point arithmetic.; Heuristic methods.; Parallel processing (Computers).

remark:
Distributed to depository libraries in microfiche. Shipping list no.: 94-0871-M. Microfiche. [Washington, D.C.: National Aeronautics and Space Administration, 1994] 1 microfiche.

entry:
@TechReport{Rothberg:1994:ILD,
  author =       "Edward Rothberg and Robert Schreiber",
  title =        "Improved load distribution in parallel sparse
                 {Cholesky} factorization",
  institution =  "Research Institute for Advanced Computer Science, NASA
                 Ames Research Center; National Technical Information
                 Service, distributor",
  address =      "Moffett Field, CA, USA",
  pages =        "????",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "[NASA contractor report]; NASA CR-196380 RIACS
                 technical report; 94.13 RIACS technical report; TR
                 94.13.",
  acknowledgement = ack-nhfb,
  govtdocnumber = "NAS 1.26:196380 0830-H-14 (MF)",
  keywords =     "Cholesky factorization.; Computer systems
                 performance.; Floating point arithmetic.; Heuristic
                 methods.; Parallel processing (Computers).",
  remark =       "Distributed to depository libraries in microfiche.
                 Shipping list no.: 94-0871-M. Microfiche. [Washington,
                 D.C.: National Aeronautics and Space Administration,
                 1994] 1 microfiche.",
}


bibtype: article
filename: fparith.bib
label: Schaefer:1994:POU
author: Mark J. Schaefer
title: Precise optimization using range arithmetic
journal: j-J-COMPUT-APPL-MATH
volume: 53
number: 3
pages: 341--351
day: 30
month: aug
monthnumber: 8
year: 1994
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 12:24:32 MST 2017
bibtimestamp: 2017.02.25 12:24:32 MST
URL: http://www.sciencedirect.com/science/article/pii/0377042794900620
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Mark J. Schaefer
rawtitle: Precise optimization using range arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath1990.bib

entry:
@Article{Schaefer:1994:POU,
  author =       "Mark J. Schaefer",
  title =        "Precise optimization using range arithmetic",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "53",
  number =       "3",
  pages =        "341--351",
  day =          "30",
  month =        aug,
  year =         "1994",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 12:24:32 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath1990.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/0377042794900620",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: mastersthesis
filename: fparith.bib
label: Schaffer:1994:FPM
author: Jonathan T. Schaffer
title: A floating point multiplier for a superscalar microprocessor
type: Thesis (M.S.)
school: North Carolina State University
address: Raleigh, NC, USA
pages: viii + 104
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Jonathan T. Schaffer
rawtitle: A floating point multiplier for a superscalar microprocessor
entry:
@MastersThesis{Schaffer:1994:FPM,
  author =       "Jonathan T. Schaffer",
  title =        "A floating point multiplier for a superscalar
                 microprocessor",
  type =         "Thesis ({M.S.})",
  school =       "North Carolina State University",
  address =      "Raleigh, NC, USA",
  pages =        "viii + 104",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Schorn:1994:DGC
author: Peter Schorn
title: Degeneracy in geometric computation and the perturbation approach
journal: j-COMP-J
volume: 37
number: 1
pages: 35--42
year: 1994
CODEN: CMPJA6
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Wed Jul 21 09:54:00 MDT 1999
bibtimestamp: 1999.07.21 09:54:00 MDT
URL: http://www3.oup.co.uk/computer_journal/Volume_37/Issue_01/Vol37_01.body.html#AbstractSchorn
fjournal: The Computer Journal
acknowledgement: ack-nhfb
affiliation: Inst. fur Theor. Inf., ETH, Zurich, Switzerland
classcodes: C4260 (Computational geometry); C4240 (Programming and algorithm theory)
corpsource: Inst. fur Theor. Inf., ETH, Zurich, Switzerland
journalURL: http://comjnl.oxfordjournals.org/
thesaurus: Algorithm theory; Computational geometry; Perturbation theory
treatment: T Theoretical or Mathematical
rawauthor: Peter Schorn
rawtitle: Degeneracy in geometric computation and the perturbation approach
bibsource:
http://www3.oup.co.uk/computer_journal/Volume_37/Issue_01/Vol37_01.index.html; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
algorithm construction; Algorithm construction; algorithm theory; algorithm-dependent; Algorithm-dependent degeneracies; approach; computational geometry; degeneracies; Euclidean constructions; floating; Floating point arithmetic; geometric computation; Geometric computation; input-output; Input-output specifications; integer arithmetic; Integer arithmetic; lexicographic; Lexicographic ordering; ordering; perturbation; Perturbation approach; point arithmetic; problem-dependent degeneracies; Problem-dependent degeneracies; provably correct results; Provably correct results; specifications; theory; winding number; Winding number

entry:
@Article{Schorn:1994:DGC,
  author =       "Peter Schorn",
  title =        "Degeneracy in geometric computation and the
                 perturbation approach",
  journal =      j-COMP-J,
  volume =       "37",
  number =       "1",
  pages =        "35--42",
  month =        "????",
  year =         "1994",
  CODEN =        "CMPJA6",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Wed Jul 21 09:54:00 MDT 1999",
  bibsource =    "http://www3.oup.co.uk/computer_journal/Volume_37/Issue_01/Vol37_01.index.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www3.oup.co.uk/computer_journal/Volume_37/Issue_01/Vol37_01.body.html#AbstractSchorn",
  acknowledgement = ack-nhfb,
  affiliation =  "Inst. fur Theor. Inf., ETH, Zurich, Switzerland",
  author-1-adr = "Institut f{\"u}r Theoretische Informatik, ETH, CH-8092
                 Zurich, Switzerland",
  classcodes =   "C4260 (Computational geometry); C4240 (Programming and
                 algorithm theory)",
  classification = "C4240 (Programming and algorithm theory); C4260
                 (Computational geometry)",
  corpsource =   "Inst. fur Theor. Inf., ETH, Zurich, Switzerland",
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "algorithm construction; Algorithm construction;
                 algorithm theory; algorithm-dependent;
                 Algorithm-dependent degeneracies; approach;
                 computational geometry; degeneracies; Euclidean
                 constructions; floating; Floating point arithmetic;
                 geometric computation; Geometric computation;
                 input-output; Input-output specifications; integer
                 arithmetic; Integer arithmetic; lexicographic;
                 Lexicographic ordering; ordering; perturbation;
                 Perturbation approach; point arithmetic;
                 problem-dependent degeneracies; Problem-dependent
                 degeneracies; provably correct results; Provably
                 correct results; specifications; theory; winding
                 number; Winding number",
  thesaurus =    "Algorithm theory; Computational geometry; Perturbation
                 theory",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: mastersthesis
filename: fparith.bib
label: Schoss:1994:ISF
author: H. Schoss
type: Diplomarbeit
school: Institut fur angewandte Mathematik, Universitat Karlsruhe
address: Karlsruhe, Germany
month: mar
monthnumber: 3
year: 1994
bibdate: Fri Sep 16 16:30:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:40 ???
acknowledgement: ack-nj
rawauthor: H. Schoss
title:
Intervall Standardfunktionen fur das binare IEEE Zahlenformat toenglish Interval Standard Functions for the Binary IEEE Number Format endtoenglish 

rawtitle:
{Intervall Standardfunktionen f{\"u}r das bin{\"a}re IEEE Zahlenformat} \toenglish {Interval Standard Functions for the Binary IEEE Number Format} \endtoenglish

entry:
@MastersThesis{Schoss:1994:ISF,
  author =       "H. Schoss",
  title =        "{Intervall Standardfunktionen f{\"u}r das bin{\"a}re
                 IEEE Zahlenformat} \toenglish {Interval Standard
                 Functions for the Binary IEEE Number Format}
                 \endtoenglish",
  type =         "{Diplomarbeit}",
  school =       "Institut f{\"u}r angewandte Mathematik,
                 Universit{\"a}t Karlsruhe",
  address =      "Karlsruhe, Germany",
  pages =        "??",
  month =        mar,
  year =         "1994",
  bibdate =      "Fri Sep 16 16:30:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Schulte:1994:HDE
author: M. J. Schulte and E. E. Swartzlander, Jr.
title: Hardware Designs for Exactly Rounded Elementary Functions
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 964--973
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295858
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:16:49 MDT
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Texas University, Austin, TX, USA
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. J. Schulte and E. E. {Swartzlander, Jr.}
rawtitle: Hardware Designs for Exactly Rounded Elementary Functions
abstract:
This paper presents hardware designs that produce exactly rounded results for the functions of reciprocal, square-root, 2/sup x/, and log/sub 2/(x). These designs use polynomial approximation in which the terms in the approximation are generated in parallel, and then summed by using a multi-operand adder. To reduce the number of terms in the approximation, the input interval is partitioned into subintervals of equal size, and different coefficients are used for each subinterval. The coefficients used in the approximation are initially determined based on the Chebyshev series approximation. They are then adjusted to obtain exactly rounded results for all inputs. Hardware designs are presented, and delay and area comparisons are made based on the degree of the approximating polynomial and the accuracy of the final result. For single-precision floating point numbers, a design that produces exactly rounded results for all four functions has an estimated delay of 80 ns and a total chip area of 98 mm/sup 2/ in a 1.0-micron CMOS technology. Allowing the results to have a maximum error of one unit in the last place reduces the computational delay by 5% to 30% and the area requirements by 33% to 77%.

keywords:
1 Micron; 1.0-Micron CMOS technology; Argument reduction; Chebyshev series approximation; Chip area; Computational delay; Computer arithmetic; Exact rounding; Exactly rounded elementary functions; Hardware designs; Multi-operand adder; Parallel multiplier; Polynomial approximation; Reciprocal; Single-precision floating point numbers; Special-purpose hardware; Square-root

thesaurus:
Approximation theory; Chebyshev approximation; CMOS integrated circuits; Digital arithmetic; Multiplying circuits; Polynomials; Summing circuits

rawabstract:
This paper presents hardware designs that produce exactly rounded results for the functions of reciprocal, square-root, 2/sup x/, and log/sub 2/(x). These designs use polynomial approximation in which the terms in the approximation are generated in parallel, and then summed by using a multi-operand adder. To reduce the number of terms in the approximation, the input interval is partitioned into subintervals of equal size, and different coefficients are used for each subinterval. The coefficients used in the approximation are initially determined based on the Chebyshev series approximation. They are then adjusted to obtain exactly rounded results for all inputs. Hardware designs are presented, and delay and area comparisons are made based on the degree of the approximating polynomial and the accuracy of the final result. For single-precision floating point numbers, a design that produces exactly rounded results for all four functions has an estimated delay of 80 ns and a total chip area of 98 mm/sup 2/ in a 1.0-micron CMOS technology. Allowing the results to have a maximum error of one unit in the last place reduces the computational delay by 5\% to 30\% and the area requirements by 33\% to 77\%.

entry:
@Article{Schulte:1994:HDE,
  author =       "M. J. Schulte and E. E. {Swartzlander, Jr.}",
  title =        "Hardware Designs for Exactly Rounded Elementary
                 Functions",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "964--973",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295858",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  abstract =     "This paper presents hardware designs that produce
                 exactly rounded results for the functions of
                 reciprocal, square-root, 2/sup x/, and log/sub 2/(x).
                 These designs use polynomial approximation in which the
                 terms in the approximation are generated in parallel,
                 and then summed by using a multi-operand adder. To
                 reduce the number of terms in the approximation, the
                 input interval is partitioned into subintervals of
                 equal size, and different coefficients are used for
                 each subinterval. The coefficients used in the
                 approximation are initially determined based on the
                 Chebyshev series approximation. They are then adjusted
                 to obtain exactly rounded results for all inputs.
                 Hardware designs are presented, and delay and area
                 comparisons are made based on the degree of the
                 approximating polynomial and the accuracy of the final
                 result. For single-precision floating point numbers, a
                 design that produces exactly rounded results for all
                 four functions has an estimated delay of 80 ns and a
                 total chip area of 98 mm/sup 2/ in a 1.0-micron CMOS
                 technology. Allowing the results to have a maximum
                 error of one unit in the last place reduces the
                 computational delay by 5\% to 30\% and the area
                 requirements by 33\% to 77\%.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Department of Electr. and Comput. Eng., Texas
                 University, Austin, TX, USA",
  ajournal =     "IEEE Trans. Comput.",
  classification = "B0290F (Interpolation and function approximation);
                 B1265B (Logic circuits); B2570D (CMOS integrated
                 circuits); C4130 (Interpolation and function
                 approximation); C5120 (Logic and switching circuits);
                 C5230 (Digital arithmetic methods)",
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "1 Micron; 1.0-Micron CMOS technology; Argument
                 reduction; Chebyshev series approximation; Chip area;
                 Computational delay; Computer arithmetic; Exact
                 rounding; Exactly rounded elementary functions;
                 Hardware designs; Multi-operand adder; Parallel
                 multiplier; Polynomial approximation; Reciprocal;
                 Single-precision floating point numbers;
                 Special-purpose hardware; Square-root",
  numericalindex = "Size 1.0E-06 m",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
  thesaurus =    "Approximation theory; Chebyshev approximation; CMOS
                 integrated circuits; Digital arithmetic; Multiplying
                 circuits; Polynomials; Summing circuits",
  xxtitle =      "Hardware Design for Exactly Rounded Elementary
                 Functions",
}


bibtype: article
filename: fparith.bib
label: Schulte:1994:OIA
author: M. J. Schulte and J. Omar and E. E. Swartzlander, Jr.
title: Optimal initial approximations for the Newton--Raphson division algorithm
journal: j-COMPUTING
volume: 53
number: 3/4
pages: 233--242
year: 1994
CODEN: CMPTA2
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
fjournal: Computing: Archiv fur informatik und numerik
acknowledgement: ack-sfo
journalURL: http://link.springer.com/journal/607
rawauthor: M. J. Schulte and J. Omar and E. E. {Swartzlander, Jr.}
rawtitle: Optimal initial approximations for the {Newton--Raphson} division algorithm
entry:
@Article{Schulte:1994:OIA,
  author =       "M. J. Schulte and J. Omar and E. E. {Swartzlander,
                 Jr.}",
  title =        "Optimal initial approximations for the
                 {Newton--Raphson} division algorithm",
  journal =      j-COMPUTING,
  volume =       "53",
  number =       "3/4",
  pages =        "233--242",
  month =        "????",
  year =         "1994",
  CODEN =        "CMPTA2",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1994:VIA
author: M. J. Schulte and E. E. Swartzlander, Jr.
title: A variable-precision interval arithmetic processor
crossref: Cappello:1994:PIC
pages: 248--258
year: 1994
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Texas University, Austin, TX, USA
thesaurus: Digital arithmetic; Error analysis; Microprocessor chips; Parallel architectures
rawauthor: M. J. Schulte and E. E. {Swartzlander, Jr.}
rawtitle: A variable-precision interval arithmetic processor
abstract:
This paper presents a special-purpose processor which implements variable-precision, interval arithmetic. Variable-precision arithmetic allows the precision of the computation to be specified, based on the problem to be solved and the required accuracy of the computation. Interval arithmetic produces two values for each result, such that the true result is guaranteed to be between the two values. The distance between the two values gives an upper bound on the error. Direct hardware support for variable-precision, interval arithmetic greatly improves the accuracy of the computation, and is much faster than existing software methods for controlling numerical error. Area and delay estimates indicate that the processor can be implemented on a single chip with a cycle time which is comparable to existing IEEE double-precision floating point processors. For computationally intensive problems, an application-specific array of variable-precision, interval arithmetic processors can execute in parallel to provide high-performance and numerically reliable results.

keywords:
Application-specific array; Hardware support; IEEE double-precision floating point processors; Numerical error; Parallel arithmetic; Special-purpose processor; Variable-precision interval arithmetic processor

rawabstract:
This paper presents a special-purpose processor which implements variable-precision, interval arithmetic. Variable-precision arithmetic allows the precision of the computation to be specified, based on the problem to be solved and the required accuracy of the computation. Interval arithmetic produces two values for each result, such that the true result is guaranteed to be between the two values. The distance between the two values gives an upper bound on the error. Direct hardware support for variable-precision, interval arithmetic greatly improves the accuracy of the computation, and is much faster than existing software methods for controlling numerical error. Area and delay estimates indicate that the processor can be implemented on a single chip with a cycle time which is comparable to existing IEEE double-precision floating point processors. For computationally intensive problems, an application-specific array of variable-precision, interval arithmetic processors can execute in parallel to provide high-performance and numerically reliable results.

entry:
@InProceedings{Schulte:1994:VIA,
  author =       "M. J. Schulte and E. E. {Swartzlander, Jr.}",
  title =        "A variable-precision interval arithmetic processor",
  crossref =     "Cappello:1994:PIC",
  pages =        "248--258",
  year =         "1994",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents a special-purpose processor which
                 implements variable-precision, interval arithmetic.
                 Variable-precision arithmetic allows the precision of
                 the computation to be specified, based on the problem
                 to be solved and the required accuracy of the
                 computation. Interval arithmetic produces two values
                 for each result, such that the true result is
                 guaranteed to be between the two values. The distance
                 between the two values gives an upper bound on the
                 error. Direct hardware support for variable-precision,
                 interval arithmetic greatly improves the accuracy of
                 the computation, and is much faster than existing
                 software methods for controlling numerical error. Area
                 and delay estimates indicate that the processor can be
                 implemented on a single chip with a cycle time which is
                 comparable to existing IEEE double-precision floating
                 point processors. For computationally intensive
                 problems, an application-specific array of
                 variable-precision, interval arithmetic processors can
                 execute in parallel to provide high-performance and
                 numerically reliable results.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. and Comput. Eng., Texas
                 University, Austin, TX, USA",
  classification = "B0290B (Error analysis in numerical methods); B1265F
                 (Microprocessors and microcomputers); C4110 (Error
                 analysis in numerical methods); C5130 (Microprocessor
                 chips); C5220P (Parallel architecture); C5230 (Digital
                 arithmetic methods)",
  keywords =     "Application-specific array; Hardware support; IEEE
                 double-precision floating point processors; Numerical
                 error; Parallel arithmetic; Special-purpose processor;
                 Variable-precision interval arithmetic processor",
  thesaurus =    "Digital arithmetic; Error analysis; Microprocessor
                 chips; Parallel architectures",
}


bibtype: article
filename: fparith.bib
label: Schwandt:1994:IAD
author: Hartmut Schwandt
journal: j-J-COMPUT-APPL-MATH
volume: 50
number: 1--3
pages: 509--521
day: 20
month: may
monthnumber: 5
year: 1994
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:02:23 MST 2017
bibtimestamp: 2017.02.25 13:02:23 MST
URL: http://www.sciencedirect.com/science/article/pii/0377042794903247
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Hartmut Schwandt
title:
An interval arithmetic domain decomposition method for a class of elliptic PDEs on nonrectangular domains

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath1990.bib

rawtitle:
An interval arithmetic domain decomposition method for a class of elliptic {PDEs} on nonrectangular domains

entry:
@Article{Schwandt:1994:IAD,
  author =       "Hartmut Schwandt",
  title =        "An interval arithmetic domain decomposition method for
                 a class of elliptic {PDEs} on nonrectangular domains",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "50",
  number =       "1--3",
  pages =        "509--521",
  day =          "20",
  month =        may,
  year =         "1994",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:02:23 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath1990.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/0377042794903247",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: techreport
filename: fparith.bib
label: Sharangpani:1994:SAF
author: H. P. Sharangpani and M. L. Barton
title: Statistical analysis of floating point flaw in the Pentium processor
institution: pub-INTEL
address: pub-INTEL:adr
pages: 509--521
month: nov
monthnumber: 11
year: 1994
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
keywords: Intel Pentium divide flaw; Thomas R. Nicely
acknowledgement: ack-sfo
rawauthor: H. P. Sharangpani and M. L. Barton
rawtitle: Statistical analysis of floating point flaw in the {Pentium} processor
URL:
http://home1.gte.net/deleyd/pentbug/white11.ps; http://www.intel.com/procs/support/pentium/fdiv/white11.ps

abstract:
A subtle flaw in the hardware divide unit of the PentiumTM Processor was discovered by Intel. Subsequently, a characterization of its impact to the end-user application base was conducted. The flaw is rare and data-dependent, and causes a reduction in precision of the divide instruction and certain other operations in certain cases.par The significance of the flaw depends upon (a) the rate of use of specific FP instructions in the PentiumTM CPU, (b) the data fed to them, (c) the way in which the results of these instructions are propagated into further computation in the application; and (d) the way in which the final results of the application are interpreted.par The thorough and detailed characterization of the flaw and the subsequent investigations of its impact on applications through elaborate surveys, analyses and empirical observation lead us to the overall conclusion that the flaw is of no concern to the vast majority of users of Pentium processor based systems. A few users of applications in the scientific/engineering and financial engineering fields who require unusual precision and invoke millions of divides per day may need to employ either an updated Pentium processor without the flaw or a software workaround.

remark:
This Intel white paper was controversial, and its minimization of the problem was refuted by others: see cite Edelman:1997:MPD.

rawabstract:
A subtle flaw in the hardware divide unit of the PentiumTM Processor was discovered by Intel. Subsequently, a characterization of its impact to the end-user application base was conducted. The flaw is rare and data-dependent, and causes a reduction in precision of the divide instruction and certain other operations in certain cases.\par The significance of the flaw depends upon (a) the rate of use of specific FP instructions in the PentiumTM CPU, (b) the data fed to them, (c) the way in which the results of these instructions are propagated into further computation in the application; and (d) the way in which the final results of the application are interpreted.\par The thorough and detailed characterization of the flaw and the subsequent investigations of its impact on applications through elaborate surveys, analyses and empirical observation lead us to the overall conclusion that the flaw is of no concern to the vast majority of users of Pentium processor based systems. A few users of applications in the scientific/engineering and financial engineering fields who require unusual precision and invoke millions of divides per day may need to employ either an updated Pentium processor without the flaw or a software workaround.

entry:
@TechReport{Sharangpani:1994:SAF,
  author =       "H. P. Sharangpani and M. L. Barton",
  title =        "Statistical analysis of floating point flaw in the
                 {Pentium} processor",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  month =        nov,
  year =         "1994",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://home1.gte.net/deleyd/pentbug/white11.ps;
                 http://www.intel.com/procs/support/pentium/fdiv/white11.ps",
  abstract =     "A subtle flaw in the hardware divide unit of the
                 PentiumTM Processor was discovered by Intel.
                 Subsequently, a characterization of its impact to the
                 end-user application base was conducted. The flaw is
                 rare and data-dependent, and causes a reduction in
                 precision of the divide instruction and certain other
                 operations in certain cases.\par

                 The significance of the flaw depends upon (a) the rate
                 of use of specific FP instructions in the PentiumTM
                 CPU, (b) the data fed to them, (c) the way in which the
                 results of these instructions are propagated into
                 further computation in the application; and (d) the way
                 in which the final results of the application are
                 interpreted.\par

                 The thorough and detailed characterization of the flaw
                 and the subsequent investigations of its impact on
                 applications through elaborate surveys, analyses and
                 empirical observation lead us to the overall conclusion
                 that the flaw is of no concern to the vast majority of
                 users of Pentium processor based systems. A few users
                 of applications in the scientific/engineering and
                 financial engineering fields who require unusual
                 precision and invoke millions of divides per day may
                 need to employ either an updated Pentium processor
                 without the flaw or a software workaround.",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  keywords =     "Intel Pentium divide flaw; Thomas R. Nicely",
  remark =       "This Intel white paper was controversial, and its
                 minimization of the problem was refuted by others: see
                 \cite{Edelman:1997:MPD}.",
}


bibtype: article
filename: fparith.bib
label: Shippy:1994:PFD
author: D. J. Shippy and T. W. Griffith
title: POWER2 fixed-point, data cache, and storage control units
journal: j-IBM-JRD
volume: 38
number: 5
pages: 503--524
month: sep
monthnumber: 9
year: 1994
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Tue Mar 25 14:26:59 MST 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.03.25 14:26:59 MST
URL: http://www.almaden.ibm.com/journal/rd38-5.html#three
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
affiliation: IBM Corp., Austin, TX, USA
corpsource: IBM Corp., Austin, TX, USA
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
treatment: P Practical
rawauthor: D. J. Shippy and T. W. Griffith
rawtitle: {POWER2} fixed-point, data cache, and storage control units
abstract:
The POWER2* fixed-point, data cache, and storage control units provide a tightly integrated subunit for a second-generation high-performance superscalar RISC processor. These functional units provide dual fixed-point execution units and a large multiported data cache, as well as high-performance interfaces to memory, I/O, and the other execution units in the processor. These units provide the following features: dual fixed-point execution units, improved fixed-point/floating-point synchronization, new floating-point load and store quadword instructions, improved address translation, improved fixed-point multiply/divide, large multiported D-cache, increased bandwidth into and out of the caches through wider data buses, an improved external interrupt mechanism, and an improved I/O DMA mechanism to support multiple-streaming Micro Channels.*

keywords:
address translation; Address translation; cache; cache storage; data buses; Data buses; data cache; Data cache; dual fixed-point; Dual fixed-point execution units; execution units; external interrupt; External interrupt mechanism; floating-; Floating-point; mechanism; memory interface; Memory interface; microprocessor chips; multiple-streaming micro channels; Multiple-streaming micro channels; multiported data; Multiported data cache; performance evaluation; point; POWER2; reduced instruction set computing; storage control units; Storage control units; storage management; superscalar RISC processor; Superscalar RISC processor; synchronisation; synchronization; Synchronization; system buses

classcodes:
B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C5470 (Performance evaluation and testing); C5610S (System buses); C5320G (Semiconductor storage)

thesaurus:
Cache storage; Microprocessor chips; Performance evaluation; Reduced instruction set computing; Storage management; Synchronisation; System buses

rawabstract:
The POWER2* fixed-point, data cache, and storage control units provide a tightly integrated subunit for a second-generation high-performance superscalar RISC processor. These functional units provide dual fixed-point execution units and a large multiported data cache, as well as high-performance interfaces to memory, I/O, and the other execution units in the processor. These units provide the following features: dual fixed-point execution units, improved fixed-point/floating-point synchronization, new floating-point load and store quadword instructions, improved address translation, improved fixed-point multiply/divide, large multiported D-cache, increased bandwidth into and out of the caches through wider data buses, an improved external interrupt mechanism, and an improved I/O DMA mechanism to support multiple-streaming Micro Channels.*

entry:
@Article{Shippy:1994:PFD,
  author =       "D. J. Shippy and T. W. Griffith",
  title =        "{POWER2} fixed-point, data cache, and storage control
                 units",
  journal =      j-IBM-JRD,
  volume =       "38",
  number =       "5",
  pages =        "503--524",
  month =        sep,
  year =         "1994",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Tue Mar 25 14:26:59 MST 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.almaden.ibm.com/journal/rd38-5.html#three",
  abstract =     "The POWER2* fixed-point, data cache, and storage
                 control units provide a tightly integrated subunit for
                 a second-generation high-performance superscalar RISC
                 processor. These functional units provide dual
                 fixed-point execution units and a large multiported
                 data cache, as well as high-performance interfaces to
                 memory, I/O, and the other execution units in the
                 processor. These units provide the following features:
                 dual fixed-point execution units, improved
                 fixed-point/floating-point synchronization, new
                 floating-point load and store quadword instructions,
                 improved address translation, improved fixed-point
                 multiply/divide, large multiported D-cache, increased
                 bandwidth into and out of the caches through wider data
                 buses, an improved external interrupt mechanism, and an
                 improved I/O DMA mechanism to support
                 multiple-streaming Micro Channels.*",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Austin, TX, USA",
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5470 (Performance evaluation
                 and testing); C5610S (System buses); C5320G
                 (Semiconductor storage)",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5320G (Semiconductor storage);
                 C5470 (Performance evaluation and testing); C5610S
                 (System buses)",
  corpsource =   "IBM Corp., Austin, TX, USA",
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "address translation; Address translation; cache; cache
                 storage; data buses; Data buses; data cache; Data
                 cache; dual fixed-point; Dual fixed-point execution
                 units; execution units; external interrupt; External
                 interrupt mechanism; floating-; Floating-point;
                 mechanism; memory interface; Memory interface;
                 microprocessor chips; multiple-streaming micro
                 channels; Multiple-streaming micro channels;
                 multiported data; Multiported data cache; performance
                 evaluation; point; POWER2; reduced instruction set
                 computing; storage control units; Storage control
                 units; storage management; superscalar RISC processor;
                 Superscalar RISC processor; synchronisation;
                 synchronization; Synchronization; system buses",
  thesaurus =    "Cache storage; Microprocessor chips; Performance
                 evaluation; Reduced instruction set computing; Storage
                 management; Synchronisation; System buses",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Smith:1994:PAT
author: James E. Smith and Shlomo Weiss
title: PowerPC 601 and Alpha 21064: a Tale of Two RISCs
journal: j-COMPUTER
volume: 27
number: 6
pages: 46--58
month: jun
monthnumber: 6
year: 1994
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Mon Feb 3 07:28:57 MST 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.02.03 07:28:57 MST
fjournal: Computer
acknowledgement: ack-nhfb
affiliation: Cray Res. Inc., Chippewa Falls, WI, USA
affiliationaddress: Chippewa Falls, WI, USA
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
journalabr: Computer
thesaurus: Instruction sets; Pipeline processing; Reduced instruction set computing
rawauthor: James E. Smith and Shlomo Weiss
rawtitle: {PowerPC 601} and {Alpha 21064}: a Tale of Two {RISCs}
abstract:
Both PowerPC and Alpha are RISC architectures, but they have little in common beyond that. The design philosophy of one emphasizes powerful instructions, the other simplicity.

keywords:
Access memory; Alpha 21064; Buffering; Cache memory; Computer software; Data storage equipment; Digital arithmetic; Digital Equipment Corporation; Floating point instructions; High performance; IBM/Motorola/Apple; Implementation philosophies; Instruction sets; Load/store architecture; Microprocessor chips; Out of order dispatch; Parallel processing systems; Performance; Philosophical aspects; Pipeline processing systems; Pipelined implementations; PowerPC 601; Processing order; Program compilers; Program debugging; Reduced instruction set computing; RISC implementations; RISC microprocessors; Streamlined implementation structure; Superscalar implementations; User interfaces; Very fast clock; Virtual storage

rawabstract:
Both PowerPC and Alpha are RISC architectures, but they have little in common beyond that. The design philosophy of one emphasizes powerful instructions, the other simplicity.

entry:
@Article{Smith:1994:PAT,
  author =       "James E. Smith and Shlomo Weiss",
  title =        "{PowerPC 601} and {Alpha 21064}: a Tale of Two
                 {RISCs}",
  journal =      j-COMPUTER,
  volume =       "27",
  number =       "6",
  pages =        "46--58",
  month =        jun,
  year =         "1994",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Mon Feb 3 07:28:57 MST 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Both PowerPC and Alpha are RISC architectures, but
                 they have little in common beyond that. The design
                 philosophy of one emphasizes powerful instructions, the
                 other simplicity.",
  acknowledgement = ack-nhfb,
  affiliation =  "Cray Res. Inc., Chippewa Falls, WI, USA",
  affiliationaddress = "Chippewa Falls, WI, USA",
  classification = "721.3; 722.1; 722.4; 723.1; C5220P (Parallel
                 architecture); C5440 (Multiprocessor systems and
                 techniques); C6140B (Machine-oriented languages)",
  conferenceyear = "1994",
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  journalabr =   "Computer",
  keywords =     "Access memory; Alpha 21064; Buffering; Cache memory;
                 Computer software; Data storage equipment; Digital
                 arithmetic; Digital Equipment Corporation; Floating
                 point instructions; High performance;
                 IBM/Motorola/Apple; Implementation philosophies;
                 Instruction sets; Load/store architecture;
                 Microprocessor chips; Out of order dispatch; Parallel
                 processing systems; Performance; Philosophical aspects;
                 Pipeline processing systems; Pipelined implementations;
                 PowerPC 601; Processing order; Program compilers;
                 Program debugging; Reduced instruction set computing;
                 RISC implementations; RISC microprocessors; Streamlined
                 implementation structure; Superscalar implementations;
                 User interfaces; Very fast clock; Virtual storage",
  publisherinfo = "IEEE Service Center",
  thesaurus =    "Instruction sets; Pipeline processing; Reduced
                 instruction set computing",
}


bibtype: article
filename: fparith.bib
label: Smith:1994:SFT
author: William Smith
title: A Short Floating-Point Type in C++
journal: j-CUJ
volume: 12
number: 1
pages: 23--??
month: jan
monthnumber: 1
year: 1994
ISSN: 0898-9788 OR 08989788
bibdate: Fri Aug 30 16:52:23 MDT 1996
bibsource: http://www.cuj.com/cbklist.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.08.30 16:52:23 MDT
fjournal: C Users Journal
acknowledgement: ack-nhfb
rawauthor: William Smith
rawtitle: A Short Floating-Point Type in {C++}
entry:
@Article{Smith:1994:SFT,
  author =       "William Smith",
  title =        "A Short Floating-Point Type in {C++}",
  journal =      j-CUJ,
  volume =       "12",
  number =       "1",
  pages =        "23--??",
  month =        jan,
  year =         "1994",
  ISSN =         "0898-9788",
  bibdate =      "Fri Aug 30 16:52:23 MDT 1996",
  bibsource =    "http://www.cuj.com/cbklist.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "C Users Journal",
}


bibtype: techreport
filename: fparith.bib
label: Solhaug:1994:FDK
author: Fredrik Solhaug
title: Flyttalls A/D-konverter = Floating Point A/D Converter
type: Hovedoppgave
institution: Institutt for teleteknikk, NTH
address: Trondheim, Norway
pages: 23--??
year: 1994
bibdate: Thu May 09 08:14:17 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.05.09 08:14:17 ???
acknowledgement: ack-nhfb
rawauthor: Fredrik Solhaug
rawtitle: Flyttalls {A/D}-konverter = Floating Point {A/D} Converter
entry:
@TechReport{Solhaug:1994:FDK,
  author =       "Fredrik Solhaug",
  title =        "Flyttalls {A/D}-konverter = Floating Point {A/D}
                 Converter",
  type =         "Hovedoppgave",
  institution =  "Institutt for teleteknikk, NTH",
  address =      "Trondheim, Norway",
  year =         "1994",
  bibdate =      "Thu May 09 08:14:17 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Srivastava:1994:ASB
author: A. Srivastava and A. Eustace
title: ATOM: a system for building customized program analysis tools
journal: j-SIGPLAN
volume: 29
number: 6
pages: 196--205
month: jun
monthnumber: 6
year: 1994
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
note: ACM SIGPLAN '94 Conference on Programming Language Design and Implementation (PLDI).
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-sfo
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: A. Srivastava and A. Eustace
rawnote: ACM SIGPLAN '94 Conference on Programming Language Design and Implementation (PLDI).
rawtitle: {ATOM}: a system for building customized program analysis tools
entry:
@Article{Srivastava:1994:ASB,
  author =       "A. Srivastava and A. Eustace",
  title =        "{ATOM}: a system for building customized program
                 analysis tools",
  journal =      j-SIGPLAN,
  volume =       "29",
  number =       "6",
  pages =        "196--205",
  month =        jun,
  year =         "1994",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "ACM SIGPLAN '94 Conference on Programming Language
                 Design and Implementation (PLDI).",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
}


bibtype: article
filename: fparith.bib
label: Stockman:1994:OMM
author: Harlan W. Stockman
title: Optimizing Matrix Math On The Pentium
journal: j-DDJ
volume: 19
number: 5
pages: 52, 54, 56, 60, 62, 66
month: may
monthnumber: 5
year: 1994
CODEN: DDJOEB
ISSN: 1044-789X OR 1044789X
bibdate: Tue Sep 03 09:15:49 1996
bibtimestamp: 1996.09.03 09:15:49 ???
fjournal: Dr. Dobb's Journal of Software Tools
acknowledgement: ack-nhfb
affiliation: Department of Geochem., Sandia Nat. Labs., Albuquerque, NM, USA
rawauthor: Harlan W. Stockman
rawtitle: Optimizing Matrix Math On The {Pentium}
abstract:
The Pentium processor is more than just a fast 486. Its pipeline and floating-point and integer operations require that you pay more attention to the flow of data on the off the FPU. Harlan presents and measures methods for speeding up Pentium matrix-math operations.

keywords:
1 MByte; 100 MHz; 256 KByte; 33 MHz; 486DX; 60 MHz; 64 Bit; 64 KByte; 8 Bit; 8-Byte boundaries; Code optimization; Data alignment; Floating-point unit; Gateway 486/33C; Gateway P5-60; Global register allocation; IRIX 4.0.5H; LINPACK routines; Loop unrolling; Matrix multiplication; Matrix operations optimization; MIPS R4000; Pentium microprocessor chip; Pentium-optimized compilers; Performance gains; SGI Elan; Simultaneous linear equations; Symantec C++ 6.0 for DOS; UNIX cc version 3.1; Write-through L2 cache

thesaurus:
Assembly language listings; Digital arithmetic; Mathematics computing; Matrix algebra; Microprocessor chips; Optimisation

rawabstract:
The Pentium processor is more than just a fast 486. Its pipeline and floating-point and integer operations require that you pay more attention to the flow of data on the off the FPU. Harlan presents and measures methods for speeding up Pentium matrix-math operations.

entry:
@Article{Stockman:1994:OMM,
  author =       "Harlan W. Stockman",
  title =        "Optimizing Matrix Math On The {Pentium}",
  journal =      j-DDJ,
  volume =       "19",
  number =       "5",
  pages =        "52, 54, 56, 60, 62, 66",
  month =        may,
  year =         "1994",
  CODEN =        "DDJOEB",
  ISSN =         "1044-789X",
  bibdate =      "Tue Sep 03 09:15:49 1996",
  bibsource =    "http://www.ddj.com/index/author/index.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 UnCover database",
  abstract =     "The Pentium processor is more than just a fast 486.
                 Its pipeline and floating-point and integer operations
                 require that you pay more attention to the flow of data
                 on the off the FPU. Harlan presents and measures
                 methods for speeding up Pentium matrix-math
                 operations.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Geochem., Sandia Nat. Labs.,
                 Albuquerque, NM, USA",
  classification = "C1180 (Optimisation techniques); C4140 (Linear
                 algebra); C5130 (Microprocessor chips); C5230 (Digital
                 arithmetic methods); C7310 (Mathematics)",
  fjournal =     "Dr. Dobb's Journal of Software Tools",
  keywords =     "1 MByte; 100 MHz; 256 KByte; 33 MHz; 486DX; 60 MHz; 64
                 Bit; 64 KByte; 8 Bit; 8-Byte boundaries; Code
                 optimization; Data alignment; Floating-point unit;
                 Gateway 486/33C; Gateway P5-60; Global register
                 allocation; IRIX 4.0.5H; LINPACK routines; Loop
                 unrolling; Matrix multiplication; Matrix operations
                 optimization; MIPS R4000; Pentium microprocessor chip;
                 Pentium-optimized compilers; Performance gains; SGI
                 Elan; Simultaneous linear equations; Symantec C++ 6.0
                 for DOS; UNIX cc version 3.1; Write-through L2 cache",
  thesaurus =    "Assembly language listings; Digital arithmetic;
                 Mathematics computing; Matrix algebra; Microprocessor
                 chips; Optimisation",
}


bibtype: article
filename: fparith.bib
label: Thompson:1994:PSN
author: Tom Thompson and Bob Ryan
journal: j-BYTE
volume: 19
number: 11
pages: 113--??
month: nov
monthnumber: 11
year: 1994
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Tue Jan 2 10:01:41 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.01.02 10:01:41 MST
fjournal: BYTE Magazine
acknowledgement: ack-nhfb
rawauthor: Tom Thompson and Bob Ryan
title:
PowerPC 620 Soars: The newest member of the PowerPC family targets the workstation market with fast throughput and speedy floating-point performance

rawtitle:
{PowerPC} 620 Soars: The newest member of the {PowerPC} family targets the workstation market with fast throughput and speedy floating-point performance

entry:
@Article{Thompson:1994:PSN,
  author =       "Tom Thompson and Bob Ryan",
  title =        "{PowerPC} 620 Soars: The newest member of the
                 {PowerPC} family targets the workstation market with
                 fast throughput and speedy floating-point performance",
  journal =      j-BYTE,
  volume =       "19",
  number =       "11",
  pages =        "113--??",
  month =        nov,
  year =         "1994",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Tue Jan 2 10:01:41 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "BYTE Magazine",
}


bibtype: article
filename: fparith.bib
label: Timmermann:1994:CFP
author: D. Timmermann and B. Rix and H. Hahn and B. J. Hosticka
title: A CMOS Floating-Point Vector-Arithmetic Unit
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 29
number: 5
pages: 634--639
month: may
monthnumber: 5
year: 1994
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nj
rawauthor: D. Timmermann and B. Rix and H. Hahn and B. J. Hosticka
rawtitle: A {CMOS} Floating-Point Vector-Arithmetic Unit
entry:
@Article{Timmermann:1994:CFP,
  author =       "D. Timmermann and B. Rix and H. Hahn and B. J.
                 Hosticka",
  title =        "A {CMOS} Floating-Point Vector-Arithmetic Unit",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "29",
  number =       "5",
  pages =        "634--639",
  month =        may,
  year =         "1994",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "This work describes a floating-point arithmetic unit
                 based on the CORDIC algorithm. The unit computes a full
                 set of high level arithmetic and elementary functions:
                 multiplication, division, (co)sine, hyperbolic
                 (co)sine, square root, natural logarithm \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Timmermann:1994:CFV
author: D. Timmermann and B. Rix and H. Hahn and B. J. Hosticka
title: A CMOS floating-point vector-arithmetic unit
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 29
number: 5
pages: 634--639
month: may
monthnumber: 5
year: 1994
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
affiliation: Fraunhofer Inst. of Microelectron. Circuits and Syst., Duisburg, Germany
rawauthor: D. Timmermann and B. Rix and H. Hahn and B. J. Hosticka
rawtitle: A {CMOS} floating-point vector-arithmetic unit
abstract:
This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 mu m double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS.

keywords:
1.6 Micron; 220 MFLOPS; CORDIC algorithm; Cosine; Division; Double-metal n-well CMOS technology; Floating-point vector-arithmetic unit; Hyperbolic sine; Inverse tangent; Multiplication; Natural logarithm; Phase; Sine; Square root; Vector norm

thesaurus:
CMOS integrated circuits; Digital arithmetic; Integrated logic circuits; Parallel architectures; Pipeline processing; Vector processor systems

rawabstract:
This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 mu m double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS.

entry:
@Article{Timmermann:1994:CFV,
  author =       "D. Timmermann and B. Rix and H. Hahn and B. J.
                 Hosticka",
  title =        "A {CMOS} floating-point vector-arithmetic unit",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "29",
  number =       "5",
  pages =        "634--639",
  month =        may,
  year =         "1994",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This work describes a floating-point arithmetic unit
                 based on the CORDIC algorithm. The unit computes a full
                 set of high level arithmetic and elementary functions:
                 multiplication, division, (co)sine, hyperbolic
                 (co)sine, square root, natural logarithm, inverse
                 (hyperbolic) tangent, vector norm, and phase. The chip
                 has been integrated in 1.6 mu m double-metal n-well
                 CMOS technology and achieves a normalized peak
                 performance of 220 MFLOPS.",
  acknowledgement = ack-nhfb,
  affiliation =  "Fraunhofer Inst. of Microelectron. Circuits and Syst.,
                 Duisburg, Germany",
  classification = "B1265B (Logic circuits); B2570D (CMOS integrated
                 circuits); C5120 (Logic and switching circuits); C5220P
                 (Parallel architecture); C5230 (Digital arithmetic
                 methods)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "1.6 Micron; 220 MFLOPS; CORDIC algorithm; Cosine;
                 Division; Double-metal n-well CMOS technology;
                 Floating-point vector-arithmetic unit; Hyperbolic sine;
                 Inverse tangent; Multiplication; Natural logarithm;
                 Phase; Sine; Square root; Vector norm",
  numericalindex = "Size 1.6E-06 m; Computer speed 2.2E+08 FLOPS",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Integrated logic circuits; Parallel architectures;
                 Pipeline processing; Vector processor systems",
}


bibtype: article
filename: fparith.bib
label: Turner:1994:SRM
author: Stephen M. Turner
title: Square roots mod $p$
journal: j-AMER-MATH-MONTHLY
volume: 101
number: 5
pages: 443--449
month: may
monthnumber: 5
year: 1994
CODEN: AMMYAE
ISSN: 0002-9890 (print), 1930-0972 (electronic) OR 00029890 (print), 19300972 (electronic)
ISSNL: 0002-9890 OR 00029890
MRclass: 11A07
MRnumber: 95c:11004
MRreviewer: David Lee Hilliker
bibdate: Wed Dec 3 17:17:33 MST 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.12.03 17:17:33 MST
fjournal: American Mathematical Monthly
acknowledgement: ack-nhfb
journalURL: https://www.jstor.org/journals/00029890.htm
rawauthor: Stephen M. Turner
rawtitle: Square roots mod $p$
entry:
@Article{Turner:1994:SRM,
  author =       "Stephen M. Turner",
  title =        "Square roots mod $p$",
  journal =      j-AMER-MATH-MONTHLY,
  volume =       "101",
  number =       "5",
  pages =        "443--449",
  month =        may,
  year =         "1994",
  CODEN =        "AMMYAE",
  ISSN =         "0002-9890 (print), 1930-0972 (electronic)",
  ISSN-L =       "0002-9890",
  MRclass =      "11A07",
  MRnumber =     "95c:11004",
  MRreviewer =   "David Lee Hilliker",
  bibdate =      "Wed Dec 3 17:17:33 MST 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "American Mathematical Monthly",
  journal-URL =  "https://www.jstor.org/journals/00029890.htm",
}


bibtype: article
filename: fparith.bib
label: Tydeman:1994:WCT
author: Fred Tydeman
title: What causes a Trap in IEEE-754 Floating-Point?
journal: j-SIGNUM
volume: 29
number: 1
pages: 2--4
month: jan
monthnumber: 1
year: 1994
CODEN: SNEWD6
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Tue Apr 12 07:50:24 MDT 2005
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.12 07:50:24 MDT
fjournal: ACM SIGNUM Newsletter
acknowledgement: ack-nhfb
affiliation: IBM Corp., Austin, TX, USA
journalURL: https://dl.acm.org/loi/signum
thesaurus: Digital arithmetic; Standards
rawauthor: Fred Tydeman
rawtitle: What causes a Trap in {IEEE-754} Floating-Point?
abstract:
In the ANSI/IEEE Std 754-1985 (IEEE standard for binary floating-point arithmetic), and the ANSI/IEEE Std 854-1987 (IEEE standard for radix-independent floating-point arithmetic), is signaling a trap an `edge-triggered' or a `level-sensitive' event? The authors discusses the question: Does it matter if an exception is signaled by an arithmetic operation versus a user setting a status flag?.

keywords:
ANSI/IEEE Std 754-1985; ANSI/IEEE Std 854-1987; Binary floating-point arithmetic; Exception; IEEE standard; Radix-independent floating-point arithmetic

rawabstract:
In the ANSI/IEEE Std 754-1985 (IEEE standard for binary floating-point arithmetic), and the ANSI/IEEE Std 854-1987 (IEEE standard for radix-independent floating-point arithmetic), is signaling a trap an `edge-triggered' or a `level-sensitive' event? The authors discusses the question: Does it matter if an exception is signaled by an arithmetic operation versus a user setting a status flag?.

entry:
@Article{Tydeman:1994:WCT,
  author =       "Fred Tydeman",
  title =        "What causes a Trap in {IEEE-754} Floating-Point?",
  journal =      j-SIGNUM,
  volume =       "29",
  number =       "1",
  pages =        "2--4",
  month =        jan,
  year =         "1994",
  CODEN =        "SNEWD6",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Tue Apr 12 07:50:24 MDT 2005",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In the ANSI/IEEE Std 754-1985 (IEEE standard for
                 binary floating-point arithmetic), and the ANSI/IEEE
                 Std 854-1987 (IEEE standard for radix-independent
                 floating-point arithmetic), is signaling a trap an
                 `edge-triggered' or a `level-sensitive' event? The
                 authors discusses the question: Does it matter if an
                 exception is signaled by an arithmetic operation versus
                 a user setting a status flag?.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Austin, TX, USA",
  classification = "C5230 (Digital arithmetic methods)",
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "https://dl.acm.org/loi/signum",
  keywords =     "ANSI/IEEE Std 754-1985; ANSI/IEEE Std 854-1987; Binary
                 floating-point arithmetic; Exception; IEEE standard;
                 Radix-independent floating-point arithmetic",
  thesaurus =    "Digital arithmetic; Standards",
}


bibtype: article
filename: fparith.bib
label: Upton:1994:RAH
author: Michael Upton and Thomas Huff and Trevor Mudge and Richard Brown
title: Resource allocation in a high clock rate microprocessor
journal: j-SIGPLAN
volume: 29
number: 11
pages: 98--109
month: nov
monthnumber: 11
year: 1994
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:16:57 MST 2003
bibtimestamp: 2003.12.14 09:16:57 MST
URL: http://www.acm.org:80/pubs/citations/proceedings/asplos/195473/p98-upton/
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliation: Department of Electr. Eng. and Computer Science, Michigan University, Ann Arbor, MI, USA
corpsource: Department of Electr. Eng. and Computer Science, Michigan University, Ann Arbor, MI, USA
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
treatment: P Practical; T Theoretical or Mathematical
rawauthor: Michael Upton and Thomas Huff and Trevor Mudge and Richard Brown
rawtitle: Resource allocation in a high clock rate microprocessor
bibsource:
http://portal.acm.org/; http://www.acm.org/pubs/toc/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
This paper discusses the design of a high clock rate (300 MHz) processor. The architecture is described, and the goals for the design are explained. The performance of three processor models is evaluated using trace-driven simulation. A cost model is used to estimate the resources required to build processors with varying sizes of on-chip memories, in both single and dual issue models. Recommendations are then made to increase the effectiveness of each of the models.

keywords:
computer architecture; Cost model; cost model; design; floating point arithmetic; Floating point latency; floating point latency; High clock rate microprocessor; high clock rate microprocessor; measurement; microprocessor chips; Nonblocking cache; nonblocking cache; On-chip memories; on-chip memories; performance; performance evaluation; Pipelining; pipelining; Prefetching; prefetching; Processor model performance; processor model performance; Resource allocation; resource allocation; theory; Trace-driven simulation; trace-driven simulation; virtual machines

subject:
bf C.1.2 Computer Systems Organization, PROCESSOR ARCHITECTURES, Multiple Data Stream Architectures (Multiprocessors), Pipeline processors**. bf D.4.2 Software, OPERATING SYSTEMS, Storage Management, Allocation/deallocation strategies. bf C.4 Computer Systems Organization, PERFORMANCE OF SYSTEMS.

thesaurus:
Computer architecture; Floating point arithmetic; Microprocessor chips; Performance evaluation; Resource allocation; Virtual machines

rawabstract:
This paper discusses the design of a high clock rate (300 MHz) processor. The architecture is described, and the goals for the design are explained. The performance of three processor models is evaluated using trace-driven simulation. A cost model is used to estimate the resources required to build processors with varying sizes of on-chip memories, in both single and dual issue models. Recommendations are then made to increase the effectiveness of each of the models.

entry:
@Article{Upton:1994:RAH,
  author =       "Michael Upton and Thomas Huff and Trevor Mudge and
                 Richard Brown",
  title =        "Resource allocation in a high clock rate
                 microprocessor",
  journal =      j-SIGPLAN,
  volume =       "29",
  number =       "11",
  pages =        "98--109",
  month =        nov,
  year =         "1994",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:57 MST 2003",
  bibsource =    "http://portal.acm.org/; http://www.acm.org/pubs/toc/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org:80/pubs/citations/proceedings/asplos/195473/p98-upton/",
  abstract =     "This paper discusses the design of a high clock rate
                 (300 MHz) processor. The architecture is described, and
                 the goals for the design are explained. The performance
                 of three processor models is evaluated using
                 trace-driven simulation. A cost model is used to
                 estimate the resources required to build processors
                 with varying sizes of on-chip memories, in both single
                 and dual issue models. Recommendations are then made to
                 increase the effectiveness of each of the models.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. Eng. and Computer Science,
                 Michigan University, Ann Arbor, MI, USA",
  classification = "C5130 (Microprocessor chips); C5220 (Computer
                 architecture); C5230 (Digital arithmetic methods);
                 C6150J (Operating systems)",
  confdate =     "4-7 Oct. 1994",
  conflocation = "San Jose, CA, USA; 4--7 Oct. 1994",
  confsponsor =  "ACM; IEEE Comput. Soc",
  conftitle =    "Sixth International Conference on Architectural
                 Support for Programming Languages and Operating Systems
                 (ASPLOS-VI)",
  corpsource =   "Department of Electr. Eng. and Computer Science,
                 Michigan University, Ann Arbor, MI, USA",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "computer architecture; Cost model; cost model; design;
                 floating point arithmetic; Floating point latency;
                 floating point latency; High clock rate microprocessor;
                 high clock rate microprocessor; measurement;
                 microprocessor chips; Nonblocking cache; nonblocking
                 cache; On-chip memories; on-chip memories; performance;
                 performance evaluation; Pipelining; pipelining;
                 Prefetching; prefetching; Processor model performance;
                 processor model performance; Resource allocation;
                 resource allocation; theory; Trace-driven simulation;
                 trace-driven simulation; virtual machines",
  sponsororg =   "ACM; IEEE Comput. Soc",
  subject =      "{\bf C.1.2} Computer Systems Organization, PROCESSOR
                 ARCHITECTURES, Multiple Data Stream Architectures
                 (Multiprocessors), Pipeline processors**. {\bf D.4.2}
                 Software, OPERATING SYSTEMS, Storage Management,
                 Allocation/deallocation strategies. {\bf C.4} Computer
                 Systems Organization, PERFORMANCE OF SYSTEMS.",
  thesaurus =    "Computer architecture; Floating point arithmetic;
                 Microprocessor chips; Performance evaluation; Resource
                 allocation; Virtual machines",
  treatment =    "P Practical; T Theoretical or Mathematical",
}


bibtype: book
filename: fparith.bib
label: vanSomeren:1994:ARC
author: Alex van Someren and Carol Atack
title: The ARM RISC Chip: a Programmer's Guide
publisher: pub-AW
address: pub-AW:adr
pages: xviii + 346
year: 1994
ISBN: 0-201-62410-9 OR 0201624109
ISBN13: 978-0-201-62410-6 OR 9780201624106
LCCN: QA76.5.V275 1994
bibdate: Wed Sep 14 22:16:36 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.14 22:16:36 ???
acknowledgement: ack-nhfb
rawauthor: Alex {van Someren} and Carol Atack
rawtitle: The {ARM RISC} Chip: a Programmer's Guide
entry:
@Book{vanSomeren:1994:ARC,
  author =       "Alex {van Someren} and Carol Atack",
  title =        "The {ARM RISC} Chip: a Programmer's Guide",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "xviii + 346",
  year =         "1994",
  ISBN =         "0-201-62410-9",
  ISBN-13 =      "978-0-201-62410-6",
  LCCN =         "QA76.5.V275 1994",
  bibdate =      "Wed Sep 14 22:16:36 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Vinnakota:1994:FCTa
author: B. Vinnakota and V. V. Bapeswara Rao
title: Fast conversion techniques for binary-residue number systems
journal: j-IEEE-TRANS-CIRCUITS-SYST-I-FUNDAM-THEORY-APPL
volume: 41
number: 12
pages: 927--929
month: dec
monthnumber: 12
year: 1994
CODEN: ITCAEX
DOI: https://doi.org/10.1109/81.340862
ISSNL: 1057-7122 OR 10577122
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7979
fjournal: IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=81
rawauthor: B. Vinnakota and V. V. Bapeswara Rao
rawtitle: Fast conversion techniques for binary-residue number systems
entry:
@Article{Vinnakota:1994:FCTa,
  author =       "B. Vinnakota and V. V. Bapeswara Rao",
  title =        "Fast conversion techniques for binary-residue number
                 systems",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-I-FUNDAM-THEORY-APPL,
  volume =       "41",
  number =       "12",
  pages =        "927--929",
  month =        dec,
  year =         "1994",
  CODEN =        "ITCAEX",
  DOI =          "https://doi.org/10.1109/81.340862",
  ISSN =         "????",
  ISSN-L =       "1057-7122",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7979",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I:
                 Fundamental Theory and Applications",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=81",
  keywords =     "residue arithmetic; residue number system",
  summary =      "An easy and efficient procedure for converting a
                 binary number into a residue number on moduli 2 n -1, 2
                 n, 2 n+1 is presented. The procedure presented reveals
                 an inversion technique. The paper also includes a
                 \ldots{}",
}


