# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Ho:2023:BBE
author: Nhut-Minh Ho and Duy-Thanh Nguyen and John L. Gustafson and Weng-Fai Wong
title: Bedot: Bit Efficient Dot Product for Deep Generative Models
crossref: Gustafson:2023:NGA
pages: 19--37
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_2
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
acknowledgement: ack-nhfb
rawauthor: Nhut-Minh Ho and Duy-Thanh Nguyen and John L. Gustafson and Weng-Fai Wong
rawtitle: {Bedot}: Bit Efficient Dot Product for Deep Generative Models
entry:
@InProceedings{Ho:2023:BBE,
  author =       "Nhut-Minh Ho and Duy-Thanh Nguyen and John L.
                 Gustafson and Weng-Fai Wong",
  title =        "{Bedot}: Bit Efficient Dot Product for Deep Generative
                 Models",
  crossref =     "Gustafson:2023:NGA",
  pages =        "19--37",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_2",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Hoffmann:2023:ASE
author: Alexandre Hoffmann and Yves Durand and Jerome Fereyre
title: Accelerating spectral elements method with extended precision: a case study
journal: International Journal of Applied Physics and Mathematics
volume: 14
number: 2
pages: 45--58
year: 2023
CODEN: IJAPJ3
DOI: https://doi.org/10.17706/ijapm
ISSN: 2010-362X OR 2010362X
ISSNL: 2010-362X OR 2010362X
bibdate: Wed Jun 12 16:34:44 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.06.12 16:34:44 ???
remark: In Proc. 12th Int. Conf. Pure Appl. Math. (ICPAM).
acknowledgement: ack-nhfb
ajournal: Int. J. Appl. Phys. Math.
rawauthor: Alexandre Hoffmann and Yves Durand and J{\'e}r{\^o}me Fereyre
rawtitle: Accelerating spectral elements method with extended precision: a case study
entry:
@Article{Hoffmann:2023:ASE,
  author =       "Alexandre Hoffmann and Yves Durand and J{\'e}r{\^o}me
                 Fereyre",
  title =        "Accelerating spectral elements method with extended
                 precision: a case study",
  journal =      "International Journal of Applied Physics and
                 Mathematics",
  volume =       "14",
  number =       "2",
  pages =        "45--58",
  year =         "2023",
  CODEN =        "IJAPJ3",
  DOI =          "https://doi.org/10.17706/ijapm",
  ISSN =         "2010-362X",
  ISSN-L =       "2010-362X",
  bibdate =      "Wed Jun 12 16:34:44 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "Int. J. Appl. Phys. Math.",
  remark =       "In Proc. 12th Int. Conf. Pure Appl. Math. (ICPAM).",
}


bibtype: techreport
filename: fparith.bib
label: Hubrecht:2023:TCRa
author: Tom Hubrecht and Claude-Pierre Jeannerod and Paul Zimmermann
title: Towards a correctly-rounded and fast power function in binary64 arithmetic
type: Report
institution: DI-ENS --- Departement d'informatique --- ENS Paris
address: Paris, France
pages: 45--58
day: 12
month: jul
monthnumber: 7
year: 2023
bibdate: Mon May 13 12:00:21 2024
bibtimestamp: 2024.05.13 12:00:21 ???
URL: https://inria.hal.science/hal-04159652v1/
remark: This is a longer version of cite Hubrecht:2023:TCRb with proofs.
acknowledgement: ack-nhfb
rawauthor: Tom Hubrecht and Claude-Pierre Jeannerod and Paul Zimmermann
rawtitle: Towards a correctly-rounded and fast power function in binary64 arithmetic
abstract:
We design algorithms for the correct rounding of the power function $ x^y $ in the binary64 IEEE 754 format, for all rounding modes, modulo the knowledge of hardest-to-round cases. Our implementation of these algorithms largely outperforms previous correctly-rounded implementations and is not far from the efficiency of current mathematical libraries, which are not correctly-rounded. Still, we expect our algorithms can be further improved for speed. The proofs of correctness are fully detailed in an extended version of this paper, with the goal to enable a formal proof of these algorithms. We hope this work will motivate the next IEEE 754 revision committee to require correct rounding for mathematical functions.

rawabstract:
We design algorithms for the correct rounding of the power function $ x^y $ in the binary64 IEEE 754 format, for all rounding modes, modulo the knowledge of hardest-to-round cases. Our implementation of these algorithms largely outperforms previous correctly-rounded implementations and is not far from the efficiency of current mathematical libraries, which are not correctly-rounded. Still, we expect our algorithms can be further improved for speed. The proofs of correctness are fully detailed in an extended version of this paper, with the goal to enable a formal proof of these algorithms. We hope this work will motivate the next IEEE 754 revision committee to require correct rounding for mathematical functions.

entry:
@TechReport{Hubrecht:2023:TCRa,
  author =       "Tom Hubrecht and Claude-Pierre Jeannerod and Paul
                 Zimmermann",
  title =        "Towards a correctly-rounded and fast power function in
                 binary64 arithmetic",
  type =         "Report",
  institution =  "DI-ENS --- D{\'e}partement d'informatique --- ENS
                 Paris",
  address =      "Paris, France",
  day =          "12",
  month =        jul,
  year =         "2023",
  bibdate =      "Mon May 13 12:00:21 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://inria.hal.science/hal-04159652v1/",
  abstract =     "We design algorithms for the correct rounding of the
                 power function $ x^y $ in the binary64 IEEE 754 format,
                 for all rounding modes, modulo the knowledge of
                 hardest-to-round cases. Our implementation of these
                 algorithms largely outperforms previous
                 correctly-rounded implementations and is not far from
                 the efficiency of current mathematical libraries, which
                 are not correctly-rounded. Still, we expect our
                 algorithms can be further improved for speed. The
                 proofs of correctness are fully detailed in an extended
                 version of this paper, with the goal to enable a formal
                 proof of these algorithms. We hope this work will
                 motivate the next IEEE 754 revision committee to
                 require correct rounding for mathematical functions.",
  acknowledgement = ack-nhfb,
  remark =       "This is a longer version of \cite{Hubrecht:2023:TCRb}
                 with proofs.",
}


bibtype: inproceedings
filename: fparith.bib
label: Hubrecht:2023:TCRb
author: Tom Hubrecht and Claude-Pierre Jeannerod and Paul Zimmermann
title: Towards a correctly-rounded and fast power function in binary64 arithmetic
crossref: IEEE:2023:PIS
pages: 111--118
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00028
bibdate: Fri Dec 08 15:03:08 2023
bibtimestamp: 2023.12.08 15:03:08 ???
remark: See also longer versions cite Hubrecht:2023:TCRa,Hubrecht:2024:TCR.
acknowledgement: ack-nhfb
rawauthor: Tom Hubrecht and Claude-Pierre Jeannerod and Paul Zimmermann
rawtitle: Towards a correctly-rounded and fast power function in binary64 arithmetic
URL:
https://arith2023.arithsymposium.org/slides/S6_PaulZimmermannS6P1.pdf; https://inria.hal.science/hal-04326201 https://inria.hal.science/hal-04159652v1/file/pow.pdf

abstract:
We design algorithms for the correct rounding of the power function $ x^y $ in the binary64 IEEE 754 format, for all rounding modes, modulo the knowledge of hardest-to-round cases. Our implementation of these algorithms largely outperforms previous correctly-rounded implementations and is not far from the efficiency of current mathematical libraries, which are not correctly-rounded. Still, we expect our algorithms can be further improved for speed. The proofs of correctness are fully detailed, with the goal to enable a formal proof of these algorithms. We hope this work will motivate the next IEEE 754 revision committee to require correct rounding for mathematical functions.

keywords:
ARITH-30; binary64 format; correct rounding; Digital arithmetic; double precision; efficiency; Error analysis; IEEE 754; Libraries; power function; Prediction algorithms; Software; Software algorithms; Switches

rawabstract:
We design algorithms for the correct rounding of the power function $ x^y $ in the binary64 IEEE 754 format, for all rounding modes, modulo the knowledge of hardest-to-round cases. Our implementation of these algorithms largely outperforms previous correctly-rounded implementations and is not far from the efficiency of current mathematical libraries, which are not correctly-rounded. Still, we expect our algorithms can be further improved for speed. The proofs of correctness are fully detailed, with the goal to enable a formal proof of these algorithms. We hope this work will motivate the next IEEE 754 revision committee to require correct rounding for mathematical functions.

entry:
@InProceedings{Hubrecht:2023:TCRb,
  author =       "Tom Hubrecht and Claude-Pierre Jeannerod and Paul
                 Zimmermann",
  title =        "Towards a correctly-rounded and fast power function in
                 binary64 arithmetic",
  crossref =     "IEEE:2023:PIS",
  pages =        "111--118",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00028",
  bibdate =      "Fri Dec 08 15:03:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arith2023.arithsymposium.org/slides/S6_PaulZimmermannS6P1.pdf;
                 https://inria.hal.science/hal-04326201
                 https://inria.hal.science/hal-04159652v1/file/pow.pdf",
  abstract =     "We design algorithms for the correct rounding of the
                 power function $ x^y $ in the binary64 IEEE 754 format,
                 for all rounding modes, modulo the knowledge of
                 hardest-to-round cases. Our implementation of these
                 algorithms largely outperforms previous
                 correctly-rounded implementations and is not far from
                 the efficiency of current mathematical libraries, which
                 are not correctly-rounded. Still, we expect our
                 algorithms can be further improved for speed. The
                 proofs of correctness are fully detailed, with the goal
                 to enable a formal proof of these algorithms. We hope
                 this work will motivate the next IEEE 754 revision
                 committee to require correct rounding for mathematical
                 functions.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-30; binary64 format; correct rounding; Digital
                 arithmetic; double precision; efficiency; Error
                 analysis; IEEE 754; Libraries; power function;
                 Prediction algorithms; Software; Software algorithms;
                 Switches",
  remark =       "See also longer versions
                 \cite{Hubrecht:2023:TCRa,Hubrecht:2024:TCR}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Hulsmeier:2023:HSH
author: Nils Hulsmeier and Moritz Barthel and Jochen Rust and Steffen Paul
title: Hybrid SORN Hardware Accelerator for Support Vector Machines
crossref: Gustafson:2023:NGA
pages: 77--87
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_5
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
acknowledgement: ack-nhfb
rawauthor: Nils H{\"u}lsmeier and Moritz B{\"a}rthel and Jochen Rust and Steffen Paul
rawtitle: Hybrid {SORN} Hardware Accelerator for Support Vector Machines
entry:
@InProceedings{Hulsmeier:2023:HSH,
  author =       "Nils H{\"u}lsmeier and Moritz B{\"a}rthel and Jochen
                 Rust and Steffen Paul",
  title =        "Hybrid {SORN} Hardware Accelerator for Support Vector
                 Machines",
  crossref =     "Gustafson:2023:NGA",
  pages =        "77--87",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_5",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: IEEE:2023:MIS
author: IEEE
title: Milestones: IEEE Standard 754 for Binary Floating-Point Arithmetic, 1985. (J. Coonen, proposer)
pages: 77--87
day: 3
month: may
monthnumber: 5
year: 2023
DOI: https://ethw.org/Milestones:IEEE_Standard_754_for_Binary_Floating-Point_Arithmetic,_1985
bibdate: Wed Aug 07 15:36:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.07 15:36:31 ???
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: {IEEE}
rawtitle: Milestones: {IEEE Standard 754 for Binary Floating-Point Arithmetic, 1985. (J. Coonen, proposer)}
entry:
@Misc{IEEE:2023:MIS,
  author =       "{IEEE}",
  title =        "Milestones: {IEEE Standard 754 for Binary
                 Floating-Point Arithmetic, 1985. (J. Coonen,
                 proposer)}",
  howpublished = "Web site",
  day =          "3",
  month =        may,
  year =         "2023",
  DOI =          "https://ethw.org/Milestones:IEEE_Standard_754_for_Binary_Floating-Point_Arithmetic,_1985",
  bibdate =      "Wed Aug 07 15:36:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: IEEE:2023:UWG
author: IEEE
title: IEEE Working Group P3109 Interim Report on 8-bit Binary Floating-point Formats
pages: 18
day: 24
month: nov
monthnumber: 11
year: 2023
bibdate: Sat Dec 16 10:36:07 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 10:36:07 ???
URL: https://github.com/P3109/Public/blob/main/Shared%20Reports/P3109%20WG%20Interim%20report.pdf
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: {IEEE}
rawtitle: {IEEE Working Group P3109} Interim Report on 8-bit Binary Floating-point Formats
remark:
Table 2 on page 4 contains a compact summary of binary8pp, binary8p5, binary8p4, binary8p3, binary16, binary32, and binary64 data layouts.

entry:
@Misc{IEEE:2023:UWG,
  author =       "{IEEE}",
  title =        "{IEEE Working Group P3109} Interim Report on 8-bit
                 Binary Floating-point Formats",
  howpublished = "Web document",
  pages =        "18",
  day =          "24",
  month =        nov,
  year =         "2023",
  bibdate =      "Sat Dec 16 10:36:07 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://github.com/P3109/Public/blob/main/Shared%20Reports/P3109%20WG%20Interim%20report.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Table 2 on page 4 contains a compact summary of
                 binary8p\{p\}, binary8p5, binary8p4, binary8p3,
                 binary16, binary32, and binary64 data layouts.",
}


bibtype: techreport
filename: fparith.bib
label: Innocente:2023:AMF
author: Vincenzo Innocente and Paul Zimmermann
title: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
pages: 21
day: 14
month: feb
monthnumber: 2
year: 2023
bibdate: Fri Dec 08 08:28:52 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 08:28:52 ???
acknowledgement: ack-nhfb
rawauthor: Vincenzo Innocente and Paul Zimmermann
rawtitle: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
URL:
https://inria.hal.science/hal-03141101; https://members.loria.fr/PZimmermann/papers/glibc237-20230214.pdf

remark:
Tabular comparison of AMD, Apple, CUDA, GNU, Intel, Musl, Newlib, OpenLibm, and RadeonOpenCompute (ROCm) lm libraries for correct rounding, versus results from MPFR.

entry:
@TechReport{Innocente:2023:AMF,
  author =       "Vincenzo Innocente and Paul Zimmermann",
  title =        "Accuracy of Mathematical Functions in Single, Double,
                 Double Extended, and Quadruple Precision",
  institution =  "????",
  pages =        "21",
  day =          "14",
  month =        feb,
  year =         "2023",
  bibdate =      "Fri Dec 08 08:28:52 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://inria.hal.science/hal-03141101;
                 https://members.loria.fr/PZimmermann/papers/glibc237-20230214.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Tabular comparison of AMD, Apple, CUDA, GNU, Intel,
                 Musl, Newlib, OpenLibm, and RadeonOpenCompute (ROCm) lm
                 libraries for correct rounding, versus results from
                 MPFR.",
}


bibtype: inproceedings
filename: fparith.bib
label: Jaberipur:2023:MMF
author: Ghassem Jaberipur and Saeid Gorgin and Navid Ahamadian and Jeong-A Lee
title: Modulo-($ 2^q - 3$) Multiplication with Fully Modular Partial Product Generation and Reduction
crossref: IEEE:2023:PIS
pages: 68--75
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00023
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Ghassem Jaberipur and Saeid Gorgin and Navid Ahamadian and Jeong-A Lee
rawtitle: Modulo-($ 2^q - 3$) Multiplication with Fully Modular Partial Product Generation and Reduction
keywords:
ARITH-30; Costs; Delays; Digital arithmetic; Energy measurement; Fully modular multiplication; Market research; Partial product reduction; Residue number system; Software; Software algorithms

entry:
@InProceedings{Jaberipur:2023:MMF,
  author =       "Ghassem Jaberipur and Saeid Gorgin and Navid Ahamadian
                 and Jeong-A Lee",
  title =        "Modulo-($ 2^q - 3$) Multiplication with Fully Modular
                 Partial Product Generation and Reduction",
  crossref =     "IEEE:2023:PIS",
  pages =        "68--75",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00023",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-30; Costs; Delays; Digital arithmetic; Energy
                 measurement; Fully modular multiplication; Market
                 research; Partial product reduction; Residue number
                 system; Software; Software algorithms",
}


bibtype: inproceedings
filename: fparith.bib
label: K:2023:DEE
editor: IEEE
title: Design of Energy Efficient and Low Delay Posit Multiplier
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2023
DOI: https://doi.org/10.1109/VLSID57277.2023.00042
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
raweditor: {IEEE}
rawtitle: Design of Energy Efficient and Low Delay Posit Multiplier
author:
Lakshmi Bhanuprakash Reddy K and Haripriya R S and Keerthija Puli and Subba Ramkumar Reddy Annapalli and Vikramkumar Pudi

booktitle:
2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)

rawauthor:
Lakshmi Bhanuprakash Reddy K and Haripriya R S and Keerthija Puli and Subba Ramkumar Reddy Annapalli and Vikramkumar Pudi

rawbooktitle:
{2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)}

entry:
@InProceedings{K:2023:DEE,
  author =       "Lakshmi Bhanuprakash Reddy K and Haripriya R S and
                 Keerthija Puli and Subba Ramkumar Reddy Annapalli and
                 Vikramkumar Pudi",
  editor =       "{IEEE}",
  booktitle =    "{2023 36th International Conference on VLSI Design and
                 2023 22nd International Conference on Embedded Systems
                 (VLSID)}",
  title =        "Design of Energy Efficient and Low Delay Posit
                 Multiplier",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/VLSID57277.2023.00042",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kapoor:2023:FVF
author: Ashish Kapoor and Warren Ferguson and Himanshu Jain and Sudipta Kundu
title: Formal Verification of Floating-Point Division
crossref: IEEE:2023:PIS
pages: 93--96
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00018
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Ashish Kapoor and Warren Ferguson and Himanshu Jain and Sudipta Kundu
rawtitle: Formal Verification of Floating-Point Division
keywords:
ARITH-30; datapath verification; Digital arithmetic; equivalence checking; floating-point division; Formal verification; formal verification; Software

entry:
@InProceedings{Kapoor:2023:FVF,
  author =       "Ashish Kapoor and Warren Ferguson and Himanshu Jain
                 and Sudipta Kundu",
  title =        "Formal Verification of Floating-Point Division",
  crossref =     "IEEE:2023:PIS",
  pages =        "93--96",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00018",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-30; datapath verification; Digital arithmetic;
                 equivalence checking; floating-point division; Formal
                 verification; formal verification; Software",
}


bibtype: inproceedings
filename: fparith.bib
label: Kavvousanos:2023:IRL
author: E. Kavvousanos and V. Sakellariou and I. Kouretas and V. Paliouras and T. Stouraitis
crossref: IEEE:2023:PIS
pages: 102--109
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00020
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: E. Kavvousanos and V. Sakellariou and I. Kouretas and V. Paliouras and T. Stouraitis
title:
Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization

keywords:
ARITH-30; Artificial neural networks; Computer architecture; Degradation; Digital arithmetic; hardware acceleration; Machine learning; Neural network hardware; neural networks; residue number system; sparsity; Training

rawtitle:
Improving Residue-Level Sparsity in {RNS-based} Neural Network Hardware Accelerators via Regularization

entry:
@InProceedings{Kavvousanos:2023:IRL,
  author =       "E. Kavvousanos and V. Sakellariou and I. Kouretas and
                 V. Paliouras and T. Stouraitis",
  title =        "Improving Residue-Level Sparsity in {RNS-based} Neural
                 Network Hardware Accelerators via Regularization",
  crossref =     "IEEE:2023:PIS",
  pages =        "102--109",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00020",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-30; Artificial neural networks; Computer
                 architecture; Degradation; Digital arithmetic; hardware
                 acceleration; Machine learning; Neural network
                 hardware; neural networks; residue number system;
                 sparsity; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Kellison:2023:LLF
author: Ariel E. Kellison and Andrew W. Appel and Mohit Tekriwal and David Bindel
title: LAProof: a Library of Formal Proofs of Accuracy and Correctness for Linear Algebra Programs
crossref: IEEE:2023:PIS
pages: 36--43
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00021
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Ariel E. Kellison and Andrew W. Appel and Mohit Tekriwal and David Bindel
rawtitle: {LAProof}: a Library of Formal Proofs of Accuracy and Correctness for Linear Algebra Programs
keywords:
ARITH-30; Error analysis; floating-point arithmetic; formal verification; Libraries; Mathematical models; program verification; rounding error analysis; Roundoff errors; Sparse matrices; Stability analysis; Vectors

entry:
@InProceedings{Kellison:2023:LLF,
  author =       "Ariel E. Kellison and Andrew W. Appel and Mohit
                 Tekriwal and David Bindel",
  title =        "{LAProof}: a Library of Formal Proofs of Accuracy and
                 Correctness for Linear Algebra Programs",
  crossref =     "IEEE:2023:PIS",
  pages =        "36--43",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00021",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-30; Error analysis; floating-point arithmetic;
                 formal verification; Libraries; Mathematical models;
                 program verification; rounding error analysis; Roundoff
                 errors; Sparse matrices; Stability analysis; Vectors",
}


bibtype: article
filename: fparith.bib
label: Klwer:2023:POC
author: Milan Klower and Peter V. Coveney and E. Adam Paxton and Tim N. Palmer
title: Periodic orbits in chaotic systems simulated at low precision
journal: j-SCI-REP
volume: 13
number: 1
publisher: pub-SV
address: pub-SV:adr
pages: 36--43
month: jul
monthnumber: 7
year: 2023
CODEN: SRCEC3
DOI: https://doi.org/10.1038/s41598-023-37004-4
ISSN: 2045-2322 OR 20452322
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
fjournal: Scientific Reports
keywords: posit arithmetic
acknowledgement: ack-nhfb
journalURL: http://www.nature.com/srep/
rawauthor: Milan Kl{\"o}wer and Peter V. Coveney and E. Adam Paxton and Tim N. Palmer
rawtitle: Periodic orbits in chaotic systems simulated at low precision
entry:
@Article{Klwer:2023:POC,
  author =       "Milan Kl{\"o}wer and Peter V. Coveney and E. Adam
                 Paxton and Tim N. Palmer",
  title =        "Periodic orbits in chaotic systems simulated at low
                 precision",
  journal =      j-SCI-REP,
  volume =       "13",
  number =       "1",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  month =        jul,
  year =         "2023",
  CODEN =        "SRCEC3",
  DOI =          "https://doi.org/10.1038/s41598-023-37004-4",
  ISSN =         "2045-2322",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Scientific Reports",
  journal-URL =  "http://www.nature.com/srep/",
  keywords =     "posit arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Krishna:2023:RNF
author: Bharath Krishna
title: Rounding Numbers in the Financial Domain!
pages: 36--43
day: 1
month: jan
monthnumber: 1
year: 2023
bibdate: Tue Feb 27 14:40:22 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.02.27 14:40:22 ???
URL: https://www.foundingminds.com/rounding-numbers-in-the-financial-domain/
keywords: decimal floating-point arithmetic; rounding errors
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Bharath Krishna
rawtitle: Rounding Numbers in the Financial Domain!
note:
Includes important mention of financial regulatory sites, with this text taken verbatim from the article, because such information may be hard to find elsewhere: * International Financial Reporting Standards (IFRS): IFRS is a set of accounting standards developed by the International Accounting Standards Board (IASB). It includes guidelines on rounding financial numbers in financial statements, such as the requirement to round amounts to the nearest whole number or the nearest multiple of 10; * Generally Accepted Accounting Principles (GAAP): GAAP is a set of accounting standards used in the United States. It includes similar guidelines on rounding financial numbers as IFRS and requires that any rounding errors should be immaterial and insignificant. * International Organization for Standardization (ISO): ISO has a standard for Rounding off numerical values, which is ISO 80000-1:2009. It provides guidelines on rounding numerical values in general and not specific to the finance domain, but it's widely used in financial systems. * The Federal Reserve Board (FRB): The FRB, the central banking system of the United States, has guidelines on rounding financial numbers for bank reporting and financial statement preparation. * The European Central Bank (ECB): The ECB, the central banking system of the European Union, has similar guidelines on rounding financial numbers as the FRB.

rawnote:
Includes important mention of financial regulatory sites, with this text taken verbatim from the article, because such information may be hard to find elsewhere: * International Financial Reporting Standards (IFRS): IFRS is a set of accounting standards developed by the International Accounting Standards Board (IASB). It includes guidelines on rounding financial numbers in financial statements, such as the requirement to round amounts to the nearest whole number or the nearest multiple of 10; * Generally Accepted Accounting Principles (GAAP): GAAP is a set of accounting standards used in the United States. It includes similar guidelines on rounding financial numbers as IFRS and requires that any rounding errors should be immaterial and insignificant. * International Organization for Standardization (ISO): ISO has a standard for Rounding off numerical values, which is ISO 80000-1:2009. It provides guidelines on rounding numerical values in general and not specific to the finance domain, but it's widely used in financial systems. * The Federal Reserve Board (FRB): The FRB, the central banking system of the United States, has guidelines on rounding financial numbers for bank reporting and financial statement preparation. * The European Central Bank (ECB): The ECB, the central banking system of the European Union, has similar guidelines on rounding financial numbers as the FRB.

entry:
@Misc{Krishna:2023:RNF,
  author =       "Bharath Krishna",
  title =        "Rounding Numbers in the Financial Domain!",
  howpublished = "Web site",
  day =          "1",
  month =        jan,
  year =         "2023",
  bibdate =      "Tue Feb 27 14:40:22 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Includes important mention of financial regulatory
                 sites, with this text taken verbatim from the article,
                 because such information may be hard to find
                 elsewhere:

                 * International Financial Reporting Standards (IFRS):
                 IFRS is a set of accounting standards developed by the
                 International Accounting Standards Board (IASB). It
                 includes guidelines on rounding financial numbers in
                 financial statements, such as the requirement to round
                 amounts to the nearest whole number or the nearest
                 multiple of 10;

                 * Generally Accepted Accounting Principles (GAAP): GAAP
                 is a set of accounting standards used in the United
                 States. It includes similar guidelines on rounding
                 financial numbers as IFRS and requires that any
                 rounding errors should be immaterial and
                 insignificant.

                 * International Organization for Standardization (ISO):
                 ISO has a standard for Rounding off numerical values,
                 which is ISO 80000-1:2009. It provides guidelines on
                 rounding numerical values in general and not specific
                 to the finance domain, but it's widely used in
                 financial systems.

                 * The Federal Reserve Board (FRB): The FRB, the central
                 banking system of the United States, has guidelines on
                 rounding financial numbers for bank reporting and
                 financial statement preparation.

                 * The European Central Bank (ECB): The ECB, the central
                 banking system of the European Union, has similar
                 guidelines on rounding financial numbers as the FRB.",
  URL =          "https://www.foundingminds.com/rounding-numbers-in-the-financial-domain/",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic; rounding errors",
}


bibtype: inproceedings
filename: fparith.bib
label: Kurian:2023:PER
author: Ashley Kurian and M. Ramesh Kini
booktitle: Lecture Notes in Networks and Systems
title: Posit Extended RISC-V Processor and Its Enhancement Using Data Type Casting
publisher: Springer Nature
address: Singapore
pages: 571--586
year: 2023
DOI: https://doi.org/10.1007/978-981-19-6634-7_40
ISBN: 981-19663-4-6 OR 9811966346
ISBN13: 978-981-19663-4-7 OR 9789811966347
ISSN: 2367-3389 OR 23673389
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Ashley Kurian and M. Ramesh Kini
rawbooktitle: Lecture Notes in Networks and Systems
rawtitle: Posit Extended {RISC-V} Processor and Its Enhancement Using Data Type Casting
entry:
@InProceedings{Kurian:2023:PER,
  author =       "Ashley Kurian and M. Ramesh Kini",
  booktitle =    "Lecture Notes in Networks and Systems",
  title =        "Posit Extended {RISC-V} Processor and Its Enhancement
                 Using Data Type Casting",
  publisher =    "Springer Nature",
  address =      "Singapore",
  pages =        "571--586",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-981-19-6634-7_40",
  ISBN =         "981-19663-4-6",
  ISBN-13 =      "978-981-19663-4-7",
  ISSN =         "2367-3389",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Laguna:2023:FIT
author: Ignacio Laguna and Anh Tran and Ganesh Gopalakrishnan
journal: j-PARALLEL-COMPUTING
volume: 117
pages: 103042:1--103042:13
month: sep
monthnumber: 9
year: 2023
CODEN: PACOEJ
DOI: https://doi.org/10.1016/j.parco.2023.103042
ISSN: 0167-8191 (print), 1872-7336 (electronic) OR 01678191 (print), 18727336 (electronic)
ISSNL: 0167-8191 OR 01678191
bibdate: Thu Sep 7 08:37:05 MDT 2023
bibtimestamp: 2023.09.07 08:37:05 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0167819123000480
fjournal: Parallel Computing
acknowledgement: ack-nhfb
articleno: 103042
journalURL: http://www.sciencedirect.com/science/journal/01678191
rawauthor: Ignacio Laguna and Anh Tran and Ganesh Gopalakrishnan
title:
Finding inputs that trigger floating-point exceptions in heterogeneous computing via Bayesian optimization

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/parallelcomputing.bib

rawtitle:
Finding inputs that trigger floating-point exceptions in heterogeneous computing via {Bayesian} optimization

entry:
@Article{Laguna:2023:FIT,
  author =       "Ignacio Laguna and Anh Tran and Ganesh
                 Gopalakrishnan",
  title =        "Finding inputs that trigger floating-point exceptions
                 in heterogeneous computing via {Bayesian}
                 optimization",
  journal =      j-PARALLEL-COMPUTING,
  volume =       "117",
  number =       "??",
  pages =        "103042:1--103042:13",
  month =        sep,
  year =         "2023",
  CODEN =        "PACOEJ",
  DOI =          "https://doi.org/10.1016/j.parco.2023.103042",
  ISSN =         "0167-8191 (print), 1872-7336 (electronic)",
  ISSN-L =       "0167-8191",
  bibdate =      "Thu Sep 7 08:37:05 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/parallelcomputing.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0167819123000480",
  acknowledgement = ack-nhfb,
  articleno =    "103042",
  fjournal =     "Parallel Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01678191",
}


bibtype: article
filename: fparith.bib
label: Leitersdorf:2023:AHT
title: AritPIM: High-Throughput In-Memory Arithmetic
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 11
number: 3
pages: 720--735
month: jul
monthnumber: 7
year: 2023
DOI: https://doi.org/10.1109/TETC.2023.3268137
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawtitle: {AritPIM}: High-Throughput In-Memory Arithmetic
author:
Orian Leitersdorf and Dean Leitersdorf and Jonathan Gal and Mor Dahan and Ronny Ronen and Shahar Kvatinsky

abstract:
Digital processing-in-memory (PIM) architectures are rapidly emerging to overcome the memory-wall bottleneck by integrating logic within memory elements. Such architectures provide vast computational power within the memory itself in the form of parallel bitwise logic operations. We develop novel algorithmic techniques for PIM that, combined with new perspectives on computer arithmetic, extend this bitwise parallelism to the four fundamental arithmetic operations (addition, subtraction, multiplication, and division), for both fixed-point and floating-point numbers, and using both bit-serial and bit-parallel approaches. We propose a state-of-the-art suite of arithmetic algorithms, demonstrating the first algorithm in the literature of digital PIM for a majority of cases --- including cases previously considered impossible for digital PIM, such as floating-point addition. Through a case study on memristive PIM, we compare the proposed algorithms to an NVIDIA RTX 3070 GPU and demonstrate significant throughput and energy improvements.

rawabstract:
Digital processing-in-memory (PIM) architectures are rapidly emerging to overcome the memory-wall bottleneck by integrating logic within memory elements. Such architectures provide vast computational power within the memory itself in the form of parallel bitwise logic operations. We develop novel algorithmic techniques for PIM that, combined with new perspectives on computer arithmetic, extend this bitwise parallelism to the four fundamental arithmetic operations (addition, subtraction, multiplication, and division), for both fixed-point and floating-point numbers, and using both bit-serial and bit-parallel approaches. We propose a state-of-the-art suite of arithmetic algorithms, demonstrating the first algorithm in the literature of digital PIM for a majority of cases --- including cases previously considered impossible for digital PIM, such as floating-point addition. Through a case study on memristive PIM, we compare the proposed algorithms to an NVIDIA RTX 3070 GPU and demonstrate significant throughput and energy improvements.

rawauthor:
Orian Leitersdorf and Dean Leitersdorf and Jonathan Gal and Mor Dahan and Ronny Ronen and Shahar Kvatinsky

entry:
@Article{Leitersdorf:2023:AHT,
  author =       "Orian Leitersdorf and Dean Leitersdorf and Jonathan
                 Gal and Mor Dahan and Ronny Ronen and Shahar
                 Kvatinsky",
  title =        "{AritPIM}: High-Throughput In-Memory Arithmetic",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "11",
  number =       "3",
  pages =        "720--735",
  month =        jul # "\slash " # sep,
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TETC.2023.3268137",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  abstract =     "Digital processing-in-memory (PIM) architectures are
                 rapidly emerging to overcome the memory-wall bottleneck
                 by integrating logic within memory elements. Such
                 architectures provide vast computational power within
                 the memory itself in the form of parallel bitwise logic
                 operations. We develop novel algorithmic techniques for
                 PIM that, combined with new perspectives on computer
                 arithmetic, extend this bitwise parallelism to the four
                 fundamental arithmetic operations (addition,
                 subtraction, multiplication, and division), for both
                 fixed-point and floating-point numbers, and using both
                 bit-serial and bit-parallel approaches. We propose a
                 state-of-the-art suite of arithmetic algorithms,
                 demonstrating the first algorithm in the literature of
                 digital PIM for a majority of cases --- including cases
                 previously considered impossible for digital PIM, such
                 as floating-point addition. Through a case study on
                 memristive PIM, we compare the proposed algorithms to
                 an NVIDIA RTX 3070 GPU and demonstrate significant
                 throughput and energy improvements.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: inproceedings
filename: fparith.bib
label: Leong:2023:LFU
author: Siew Hoon Leong and John L. Gustafson
title: Lossless FFTs Using Posit Arithmetic
crossref: Gustafson:2023:NGA
pages: 1--18
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_1
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
acknowledgement: ack-nhfb
rawauthor: Siew Hoon Leong and John L. Gustafson
rawtitle: Lossless {FFTs} Using Posit Arithmetic
entry:
@InProceedings{Leong:2023:LFU,
  author =       "Siew Hoon Leong and John L. Gustafson",
  title =        "Lossless {FFTs} Using Posit Arithmetic",
  crossref =     "Gustafson:2023:NGA",
  pages =        "1--18",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_1",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2023:DEG
publisher: pub-ACM
address: pub-ACM:adr
pages: 59--71
month: aug
monthnumber: 8
year: 2023
DOI: https://doi.org/10.1145/3588195.3592991
bibdate: Thu Sep 7 09:13:15 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.07 09:13:15 ???
URL: https://dl.acm.org/doi/10.1145/3588195.3592991; https://github.com/LLNL/GPU-FPX
acknowledgement: ack-nhfb
author:
Xinyi Li and Ignacio Laguna and Bo Fang and Katarzyna Swirydowicz and Ang Li and Ganesh Gopalakrishnan

booktitle:
Proceedings of the 32nd International Symposium on High-Performance Parallel and Distributed Computing

title:
Design and Evaluation of GPU-FPX: a Low-Overhead tool for Floating-Point Exception Detection in NVIDIA GPUs

abstract:
Floating-point exceptions occurring during numerical computations can be a serious threat to the validity of the computed results if they are not caught and diagnosed Unfortunately, on NVIDIA GPUs --- today's most widely used types and which do not have hardware exception traps --- this task must be carried out in software. Given the prevalence of closed-source kernels, efficient binary-level exception tracking is essential. It is also important to know how exceptions flow through the code, whether they alter the code behavior and additionally whether these exceptions can be detected at the program outputs or are killed inside program flow-paths. In this paper, we introduce GPU-FPX, a tool that has low overhead, allows for deep understanding of the origin and flow of exceptions, and also how exceptions are modified by code optimizations. We measure GPU-FPX's performance over 151 widely used GPU programs coming from HPC and ML, detecting 26 serious exceptions that were previously not reported. Our results show that GPU-FPX is $ 16 times $ faster with respect to the geometric-mean runtime in relation to the only comparable prior tool, while also helping debug a larger class of codes more effectively.

rawabstract:
Floating-point exceptions occurring during numerical computations can be a serious threat to the validity of the computed results if they are not caught and diagnosed Unfortunately, on NVIDIA GPUs --- today's most widely used types and which do not have hardware exception traps --- this task must be carried out in software. Given the prevalence of closed-source kernels, efficient binary-level exception tracking is essential. It is also important to know how exceptions flow through the code, whether they alter the code behavior and additionally whether these exceptions can be detected at the program outputs or are killed inside program flow-paths. In this paper, we introduce GPU-FPX, a tool that has low overhead, allows for deep understanding of the origin and flow of exceptions, and also how exceptions are modified by code optimizations. We measure GPU-FPX's performance over 151 widely used GPU programs coming from HPC and ML, detecting 26 serious exceptions that were previously not reported. Our results show that GPU-FPX is $ 16 \times $ faster with respect to the geometric-mean runtime in relation to the only comparable prior tool, while also helping debug a larger class of codes more effectively.

rawauthor:
Xinyi Li and Ignacio Laguna and Bo Fang and Katarzyna Swirydowicz and Ang Li and Ganesh Gopalakrishnan

rawbooktitle:
Proceedings of the {32nd International Symposium on High-Performance Parallel and Distributed Computing}

rawtitle:
Design and Evaluation of {GPU-FPX}: a Low-Overhead tool for Floating-Point Exception Detection in {NVIDIA GPUs}

entry:
@InProceedings{Li:2023:DEG,
  author =       "Xinyi Li and Ignacio Laguna and Bo Fang and Katarzyna
                 Swirydowicz and Ang Li and Ganesh Gopalakrishnan",
  booktitle =    "Proceedings of the {32nd International Symposium on
                 High-Performance Parallel and Distributed Computing}",
  title =        "Design and Evaluation of {GPU-FPX}: a Low-Overhead
                 tool for Floating-Point Exception Detection in {NVIDIA
                 GPUs}",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "59--71",
  month =        aug,
  year =         "2023",
  DOI =          "https://doi.org/10.1145/3588195.3592991",
  bibdate =      "Thu Sep 7 09:13:15 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3588195.3592991;
                 https://github.com/LLNL/GPU-FPX",
  abstract =     "Floating-point exceptions occurring during numerical
                 computations can be a serious threat to the validity of
                 the computed results if they are not caught and
                 diagnosed Unfortunately, on NVIDIA GPUs --- today's
                 most widely used types and which do not have hardware
                 exception traps --- this task must be carried out in
                 software. Given the prevalence of closed-source
                 kernels, efficient binary-level exception tracking is
                 essential. It is also important to know how exceptions
                 flow through the code, whether they alter the code
                 behavior and additionally whether these exceptions can
                 be detected at the program outputs or are killed inside
                 program flow-paths. In this paper, we introduce
                 GPU-FPX, a tool that has low overhead, allows for deep
                 understanding of the origin and flow of exceptions, and
                 also how exceptions are modified by code optimizations.
                 We measure GPU-FPX's performance over 151 widely used
                 GPU programs coming from HPC and ML, detecting 26
                 serious exceptions that were previously not reported.
                 Our results show that GPU-FPX is $ 16 \times $ faster
                 with respect to the geometric-mean runtime in relation
                 to the only comparable prior tool, while also helping
                 debug a larger class of codes more effectively.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Li:2023:DSE
author: He Li and Jiawei Liang and Hongxiang Fan and Yongming Tang
title: Design Space Exploration for Efficient Quantum Most-Significant Digit-First Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 6
pages: 1822--1829
month: jun
monthnumber: 6
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2022.3215891
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed May 17 10:34:15 2023
bibtimestamp: 2023.05.17 10:34:15 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: He Li and Jiawei Liang and Hongxiang Fan and Yongming Tang
rawtitle: Design Space Exploration for Efficient Quantum Most-Significant Digit-First Arithmetic
abstract:
Quantum computing has been considered as an emerging approach in addressing problems which are not easily solvable using classical computers. In parallel to the physical implementation of quantum processors, quantum algorithms have been actively developed for real-life applications to show quantum advantages, many of which benefit from quantum arithmetic algorithms and their efficient implementations. As one of the most important operations, quantum addition has been adopted in Shor's algorithm and quantum linear algebra algorithms. Although various least-significant digit-first quantum adders have been introduced in previous work, interest in investigating the efficient implementation of most-significant digit-first addition is growing. In this work, we propose a novel design method for most-significant digit-first addition with several quantum circuit optimisations to reduce the number of quantum bits (i.e. qubits), quantum gates, and circuit depth. An open-source library of different arithmetic operators based on our proposed method is presented, where all circuits are implemented on IBM Qiskit SDK. Extensive experiments demonstrate that our proposed design, together with the optimisation techniques, reduces T-depth by up-to 4.0$ times $, T-count by 3.5$ times $, and qubit consumption by 1.2$ times $.

rawabstract:
Quantum computing has been considered as an emerging approach in addressing problems which are not easily solvable using classical computers. In parallel to the physical implementation of quantum processors, quantum algorithms have been actively developed for real-life applications to show quantum advantages, many of which benefit from quantum arithmetic algorithms and their efficient implementations. As one of the most important operations, quantum addition has been adopted in Shor's algorithm and quantum linear algebra algorithms. Although various least-significant digit-first quantum adders have been introduced in previous work, interest in investigating the efficient implementation of most-significant digit-first addition is growing. In this work, we propose a novel design method for most-significant digit-first addition with several quantum circuit optimisations to reduce the number of quantum bits (i.e. qubits), quantum gates, and circuit depth. An open-source library of different arithmetic operators based on our proposed method is presented, where all circuits are implemented on IBM Qiskit SDK. Extensive experiments demonstrate that our proposed design, together with the optimisation techniques, reduces T-depth by up-to 4.0$ \times $, T-count by 3.5$ \times $, and qubit consumption by 1.2$ \times $.

entry:
@Article{Li:2023:DSE,
  author =       "He Li and Jiawei Liang and Hongxiang Fan and Yongming
                 Tang",
  title =        "Design Space Exploration for Efficient Quantum
                 Most-Significant Digit-First Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "6",
  pages =        "1822--1829",
  month =        jun,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2022.3215891",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed May 17 10:34:15 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  abstract =     "Quantum computing has been considered as an emerging
                 approach in addressing problems which are not easily
                 solvable using classical computers. In parallel to the
                 physical implementation of quantum processors, quantum
                 algorithms have been actively developed for real-life
                 applications to show quantum advantages, many of which
                 benefit from quantum arithmetic algorithms and their
                 efficient implementations. As one of the most important
                 operations, quantum addition has been adopted in Shor's
                 algorithm and quantum linear algebra algorithms.
                 Although various least-significant digit-first quantum
                 adders have been introduced in previous work, interest
                 in investigating the efficient implementation of
                 most-significant digit-first addition is growing. In
                 this work, we propose a novel design method for
                 most-significant digit-first addition with several
                 quantum circuit optimisations to reduce the number of
                 quantum bits (i.e. qubits), quantum gates, and circuit
                 depth. An open-source library of different arithmetic
                 operators based on our proposed method is presented,
                 where all circuits are implemented on IBM Qiskit SDK.
                 Extensive experiments demonstrate that our proposed
                 design, together with the optimisation techniques,
                 reduces T-depth by up-to 4.0$ \times $, T-count by 3.5$
                 \times $, and qubit consumption by 1.2$ \times $.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Li:2023:EEB
author: Ruiyuan Li and Zheng Li and Yi Wu and Chao Chen and Yu Zheng
title: Elf: Erasing-Based Lossless Floating-Point Compression
journal: j-PROC-VLDB-ENDOWMENT
volume: 16
number: 7
pages: 1763--1776
month: mar
monthnumber: 3
year: 2023
DOI: https://doi.org/10.14778/3587136.3587149
ISSN: 2150-8097 OR 21508097
bibdate: Tue May 9 09:08:30 MDT 2023
bibtimestamp: 2023.05.09 09:08:30 MDT
URL: https://dl.acm.org/doi/10.14778/3587136.3587149
fjournal: Proceedings of the VLDB Endowment
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/pvldb
rawauthor: Ruiyuan Li and Zheng Li and Yi Wu and Chao Chen and Yu Zheng
rawtitle: {Elf}: Erasing-Based Lossless Floating-Point Compression
bibsource:
https://www.math.utah.edu/pub/tex/bib/datacompression.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/vldbe.bib

abstract:
There are a prohibitively large number of floating-point time series data generated at an unprecedentedly high rate. An efficient, compact and lossless compression for time series data is of great importance for a wide range of scenarios. Most existing lossless floating-point compression methods are based on the XOR operation, but they do not fully exploit the trailing zeros, which usually results in an unsatisfactory compression ratio. This paper proposes an Erasing-based Lossless Floating-point compression algorithm, i.e., pkg Elf. The main idea of pkg Elf is to erase the last few bits (i.e., set them to zero) of floating-point values, so the XORed values are supposed to contain many trailing zeros. The challenges of the erasing-based method are three-fold. First, how to quickly determine the erased bits? Second, how to losslessly recover the original data from the erased ones? Third, how to compactly encode the erased data? Through rigorous mathematical analysis, pkg Elf can directly determine the erased bits and restore the original values without losing any precision. To further improve the compression ratio, we propose a novel encoding strategy for the XORed values with many trailing zeros. pkg Elf works in a streaming fashion. It takes only $ O(N) $ (where $N$ is the length of a time series) in time and $ O(1)$ in space, and achieves a notable compression ratio with a theoretical guarantee. Extensive experiments using 22 datasets show the powerful performance of pkg Elf compared with 9 advanced competitors.

rawabstract:
There are a prohibitively large number of floating-point time series data generated at an unprecedentedly high rate. An efficient, compact and lossless compression for time series data is of great importance for a wide range of scenarios. Most existing lossless floating-point compression methods are based on the XOR operation, but they do not fully exploit the trailing zeros, which usually results in an unsatisfactory compression ratio. This paper proposes an Erasing-based Lossless Floating-point compression algorithm, i.e., \pkg{Elf}. The main idea of \pkg{Elf} is to erase the last few bits (i.e., set them to zero) of floating-point values, so the XORed values are supposed to contain many trailing zeros. The challenges of the erasing-based method are three-fold. First, how to quickly determine the erased bits? Second, how to losslessly recover the original data from the erased ones? Third, how to compactly encode the erased data? Through rigorous mathematical analysis, \pkg{Elf} can directly determine the erased bits and restore the original values without losing any precision. To further improve the compression ratio, we propose a novel encoding strategy for the XORed values with many trailing zeros. \pkg{Elf} works in a streaming fashion. It takes only $ O(N) $ (where $N$ is the length of a time series) in time and $ O(1)$ in space, and achieves a notable compression ratio with a theoretical guarantee. Extensive experiments using 22 datasets show the powerful performance of \pkg{Elf} compared with 9 advanced competitors.

entry:
@Article{Li:2023:EEB,
  author =       "Ruiyuan Li and Zheng Li and Yi Wu and Chao Chen and Yu
                 Zheng",
  title =        "{Elf}: Erasing-Based Lossless Floating-Point
                 Compression",
  journal =      j-PROC-VLDB-ENDOWMENT,
  volume =       "16",
  number =       "7",
  pages =        "1763--1776",
  month =        mar,
  year =         "2023",
  CODEN =        "????",
  DOI =          "https://doi.org/10.14778/3587136.3587149",
  ISSN =         "2150-8097",
  bibdate =      "Tue May 9 09:08:30 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/datacompression.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/vldbe.bib",
  URL =          "https://dl.acm.org/doi/10.14778/3587136.3587149",
  abstract =     "There are a prohibitively large number of
                 floating-point time series data generated at an
                 unprecedentedly high rate. An efficient, compact and
                 lossless compression for time series data is of great
                 importance for a wide range of scenarios. Most existing
                 lossless floating-point compression methods are based
                 on the XOR operation, but they do not fully exploit the
                 trailing zeros, which usually results in an
                 unsatisfactory compression ratio. This paper proposes
                 an Erasing-based Lossless Floating-point compression
                 algorithm, i.e., \pkg{Elf}. The main idea of \pkg{Elf}
                 is to erase the last few bits (i.e., set them to zero)
                 of floating-point values, so the XORed values are
                 supposed to contain many trailing zeros. The challenges
                 of the erasing-based method are three-fold. First, how
                 to quickly determine the erased bits? Second, how to
                 losslessly recover the original data from the erased
                 ones? Third, how to compactly encode the erased data?
                 Through rigorous mathematical analysis, \pkg{Elf} can
                 directly determine the erased bits and restore the
                 original values without losing any precision. To
                 further improve the compression ratio, we propose a
                 novel encoding strategy for the XORed values with many
                 trailing zeros. \pkg{Elf} works in a streaming fashion.
                 It takes only $ O(N) $ (where $N$ is the length of a
                 time series) in time and $ O(1)$ in space, and achieves
                 a notable compression ratio with a theoretical
                 guarantee. Extensive experiments using 22 datasets show
                 the powerful performance of \pkg{Elf} compared with 9
                 advanced competitors.",
  acknowledgement = ack-nhfb,
  fjournal =     "Proceedings of the VLDB Endowment",
  journal-URL =  "https://dl.acm.org/loi/pvldb",
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2023:POS
author: Qiong Li and Chao Fang and Zhongfeng Wang
editor: IEEE
booktitle: 2023 IEEE International Symposium on Circuits and Systems (ISCAS)
title: PDPU: an Open-Source Posit Dot-Product Unit for Deep Learning Applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2023
DOI: https://doi.org/10.1109/ISCAS46773.2023.10182007
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Qiong Li and Chao Fang and Zhongfeng Wang
rawbooktitle: {2023 IEEE International Symposium on Circuits and Systems (ISCAS)}
raweditor: {IEEE}
rawtitle: {PDPU}: an Open-Source Posit Dot-Product Unit for Deep Learning Applications
entry:
@InProceedings{Li:2023:POS,
  author =       "Qiong Li and Chao Fang and Zhongfeng Wang",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "{PDPU}: an Open-Source Posit Dot-Product Unit for Deep
                 Learning Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCAS46773.2023.10182007",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Liu:2023:CHR
author: Zixuan Liu and Xiaoyu Song and Zhuowei Wang and Yan Wang and Jian-Tao Zhou
title: Constructing High Radix Quotient Digit Selection Tables for SRT Division and Square Root
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 7
pages: 2111--2119
month: jul
monthnumber: 7
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2023.3235978
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 1 10:59:22 2023
bibtimestamp: 2023.07.01 10:59:22 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Zixuan Liu and Xiaoyu Song and Zhuowei Wang and Yan Wang and Jian-Tao Zhou
rawtitle: Constructing High Radix Quotient Digit Selection Tables for {SRT} Division and Square Root
entry:
@Article{Liu:2023:CHR,
  author =       "Zixuan Liu and Xiaoyu Song and Zhuowei Wang and Yan
                 Wang and Jian-Tao Zhou",
  title =        "Constructing High Radix Quotient Digit Selection
                 Tables for {SRT} Division and Square Root",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "7",
  pages =        "2111--2119",
  month =        jul,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3235978",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 1 10:59:22 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Livesay:2023:AFF
title: Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs
journal: j-IEEE-MICRO
volume: 43
number: 5
pages: 55--63
month: sep
monthnumber: 9
year: 2023
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/MM.2023.3253052
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Thu Sep 14 06:42:28 2023
bibtimestamp: 2023.09.14 06:42:28 ???
fjournal: IEEE Micro
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40
rawtitle: Accelerating Finite Field Arithmetic for Homomorphic Encryption on {GPUs}
author:
Neal Livesay and Gilbert Jonatan and Evelio Mora and Kaustubh Shivdikar and Rashmi Agrawal and Ajay Joshi and Jose L. Abellan and John Kim and David Kaeli

bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib

rawauthor:
Neal Livesay and Gilbert Jonatan and Evelio Mora and Kaustubh Shivdikar and Rashmi Agrawal and Ajay Joshi and Jos{\'e} L. Abell{\'a}n and John Kim and David Kaeli

entry:
@Article{Livesay:2023:AFF,
  author =       "Neal Livesay and Gilbert Jonatan and Evelio Mora and
                 Kaustubh Shivdikar and Rashmi Agrawal and Ajay Joshi
                 and Jos{\'e} L. Abell{\'a}n and John Kim and David
                 Kaeli",
  title =        "Accelerating Finite Field Arithmetic for Homomorphic
                 Encryption on {GPUs}",
  journal =      j-IEEE-MICRO,
  volume =       "43",
  number =       "5",
  pages =        "55--63",
  month =        sep # "\slash " # oct,
  year =         "2023",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2023.3253052",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Sep 14 06:42:28 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
}


bibtype: inproceedings
filename: fparith.bib
label: Malathi:2023:DRV
author: D Malathi and R Sneha and M Shanmugapriya and S Sethurajan
editor: IEEE
booktitle: 2023 4th International Conference on Signal Processing and Communication (ICSPC)
title: Design of RISC-V Processing Unit Using Posit Number System
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 427--431
year: 2023
DOI: https://doi.org/10.1109/ICSPC57692.2023.10125646
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: D Malathi and R Sneha and M Shanmugapriya and S Sethurajan
rawbooktitle: {2023 4th International Conference on Signal Processing and Communication (ICSPC)}
raweditor: {IEEE}
rawtitle: Design of {RISC-V} Processing Unit Using Posit Number System
entry:
@InProceedings{Malathi:2023:DRV,
  author =       "D Malathi and R Sneha and M Shanmugapriya and S
                 Sethurajan",
  editor =       "{IEEE}",
  booktitle =    "{2023 4th International Conference on Signal
                 Processing and Communication (ICSPC)}",
  title =        "Design of {RISC-V} Processing Unit Using Posit Number
                 System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "427--431",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICSPC57692.2023.10125646",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Mansfield:2023:MSR
author: Daniel F. Mansfield
title: Mesopotamian square root approximation by a sequence of rectangles
journal: j-BRITISH-J-HIST-MATH
volume: 38
number: 3
pages: 175--188
year: 2023
DOI: https://doi.org/10.1080/26375451.2023.2215652
ISSN: 1749-8430 (print), 1749-8341 (electronic) OR 17498430 (print), 17498341 (electronic)
ISSNL: 1749-8341 OR 17498341
bibdate: Thu Apr 25 11:06:30 MDT 2024
bibtimestamp: 2024.04.25 11:06:30 MDT
URL: http://www.tandfonline.com/doi/full/10.1080/26375451.2023.2215652
fjournal: BSHM Bulletin: Journal of the British Society for the History of Mathematics
acknowledgement: ack-nhfb
ajournal: BSHM Bull.
journalURL: http://www.tandfonline.com/loi/tbsh20
onlinedate: 09 Jun 2023
rawauthor: Daniel F. Mansfield
rawtitle: {Mesopotamian} square root approximation by a sequence of rectangles
bibsource:
https://www.math.utah.edu/pub/tex/bib/bshm.bib; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Mansfield:2023:MSR,
  author =       "Daniel F. Mansfield",
  title =        "{Mesopotamian} square root approximation by a sequence
                 of rectangles",
  journal =      j-BRITISH-J-HIST-MATH,
  volume =       "38",
  number =       "3",
  pages =        "175--188",
  year =         "2023",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1080/26375451.2023.2215652",
  ISSN =         "1749-8430 (print), 1749-8341 (electronic)",
  ISSN-L =       "1749-8341",
  bibdate =      "Thu Apr 25 11:06:30 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/bshm.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.tandfonline.com/doi/full/10.1080/26375451.2023.2215652",
  acknowledgement = ack-nhfb,
  ajournal =     "BSHM Bull.",
  fjournal =     "BSHM Bulletin: Journal of the British Society for the
                 History of Mathematics",
  journal-URL =  "http://www.tandfonline.com/loi/tbsh20",
  onlinedate =   "09 Jun 2023",
}


bibtype: article
filename: fparith.bib
label: Martin-Dorel:2023:EFP
author: Erik Martin-Dorel and Guillaume Melquiond and Pierre Roux
title: Enabling Floating-Point Arithmetic in the Coq Proof Assistant
journal: j-J-AUTOM-REASON
volume: 67
number: 4
pages: ??--??
month: dec
monthnumber: 12
year: 2023
CODEN: JAREEW
DOI: https://doi.org/10.1007/s10817-023-09679-x
ISSN: 0168-7433 (print), 1573-0670 (electronic) OR 01687433 (print), 15730670 (electronic)
ISSNL: 0168-7433 OR 01687433
bibdate: Mon Nov 27 10:14:54 MST 2023
bibtimestamp: 2023.11.27 10:14:54 MST
URL: https://link.springer.com/article/10.1007/s10817-023-09679-x
fjournal: Journal of Automated Reasoning
acknowledgement: ack-nhfb
ajournal: J. Autom. Reason.
articleno: 33
journalURL: http://link.springer.com/journal/10817
rawauthor: {\'E}rik Martin-Dorel and Guillaume Melquiond and Pierre Roux
rawtitle: Enabling Floating-Point Arithmetic in the {Coq} Proof Assistant
entry:
@Article{Martin-Dorel:2023:EFP,
  author =       "{\'E}rik Martin-Dorel and Guillaume Melquiond and
                 Pierre Roux",
  title =        "Enabling Floating-Point Arithmetic in the {Coq} Proof
                 Assistant",
  journal =      j-J-AUTOM-REASON,
  volume =       "67",
  number =       "4",
  pages =        "??--??",
  month =        dec,
  year =         "2023",
  CODEN =        "JAREEW",
  DOI =          "https://doi.org/10.1007/s10817-023-09679-x",
  ISSN =         "0168-7433 (print), 1573-0670 (electronic)",
  ISSN-L =       "0168-7433",
  bibdate =      "Mon Nov 27 10:14:54 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jautomreason.bib",
  URL =          "https://link.springer.com/article/10.1007/s10817-023-09679-x",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Autom. Reason.",
  articleno =    "33",
  fjournal =     "Journal of Automated Reasoning",
  journal-URL =  "http://link.springer.com/journal/10817",
}


bibtype: article
filename: fparith.bib
label: Melquiond:2023:WFV
author: Guillaume Melquiond and Raphael Rieu-Helft
title: WhyMP, a formally verified arbitrary-precision integer library
journal: j-J-SYMBOLIC-COMP
volume: 115
pages: 74--95
month: mar
monthnumber: 3
year: 2023
CODEN: JSYCEH
DOI: https://doi.org/10.1016/j.jsc.2022.07.007
ISSN: 0747-7171 (print), 1095-855X (electronic) OR 07477171 (print), 1095855X (electronic)
ISSNL: 0747-7171 OR 07477171
bibdate: Sat Sep 17 06:23:51 MDT 2022
bibtimestamp: 2022.09.17 06:23:51 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0747717122000657
fjournal: Journal of Symbolic Computation
keywords: Deductive program verification; Integer arithmetic; Mathematical library
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07477171
rawauthor: Guillaume Melquiond and Rapha{\"e}l Rieu-Helft
rawtitle: {WhyMP}, a formally verified arbitrary-precision integer library
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/gnu.bib; https://www.math.utah.edu/pub/tex/bib/jsymcomp.bib

abstract:
Arbitrary-precision integer libraries such as GMP are a critical building block of computer algebra systems. GMP provides state-of-the-art algorithms that are intricate enough to justify formal verification. In this paper, we present a C library that has been formally verified using the Why3 verification platform in about four person-years. This verification deals not only with safety, but with full functional correctness. It has been performed using a mixture of mechanically checked handwritten proofs and automated theorem proving. We have implemented and verified a nontrivial subset of GMP's algorithms, including their optimizations and intricacies. Our library provides the same interface as GMP and is almost as efficient for smaller inputs. We detail our verification methodology and the algorithms we have implemented, and include some benchmarks to compare our library with GMP.

rawabstract:
Arbitrary-precision integer libraries such as GMP are a critical building block of computer algebra systems. GMP provides state-of-the-art algorithms that are intricate enough to justify formal verification. In this paper, we present a C library that has been formally verified using the Why3 verification platform in about four person-years. This verification deals not only with safety, but with full functional correctness. It has been performed using a mixture of mechanically checked handwritten proofs and automated theorem proving. We have implemented and verified a nontrivial subset of GMP's algorithms, including their optimizations and intricacies. Our library provides the same interface as GMP and is almost as efficient for smaller inputs. We detail our verification methodology and the algorithms we have implemented, and include some benchmarks to compare our library with GMP.

entry:
@Article{Melquiond:2023:WFV,
  author =       "Guillaume Melquiond and Rapha{\"e}l Rieu-Helft",
  title =        "{WhyMP}, a formally verified arbitrary-precision
                 integer library",
  journal =      j-J-SYMBOLIC-COMP,
  volume =       "115",
  number =       "??",
  pages =        "74--95",
  month =        mar # "\slash " # apr,
  year =         "2023",
  CODEN =        "JSYCEH",
  DOI =          "https://doi.org/10.1016/j.jsc.2022.07.007",
  ISSN =         "0747-7171 (print), 1095-855X (electronic)",
  ISSN-L =       "0747-7171",
  bibdate =      "Sat Sep 17 06:23:51 MDT 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/gnu.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsymcomp.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0747717122000657",
  abstract =     "Arbitrary-precision integer libraries such as GMP are
                 a critical building block of computer algebra systems.
                 GMP provides state-of-the-art algorithms that are
                 intricate enough to justify formal verification. In
                 this paper, we present a C library that has been
                 formally verified using the Why3 verification platform
                 in about four person-years. This verification deals not
                 only with safety, but with full functional correctness.
                 It has been performed using a mixture of mechanically
                 checked handwritten proofs and automated theorem
                 proving. We have implemented and verified a nontrivial
                 subset of GMP's algorithms, including their
                 optimizations and intricacies. Our library provides the
                 same interface as GMP and is almost as efficient for
                 smaller inputs. We detail our verification methodology
                 and the algorithms we have implemented, and include
                 some benchmarks to compare our library with GMP.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Symbolic Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07477171",
  keywords =     "Deductive program verification; Integer arithmetic;
                 Mathematical library",
}


bibtype: article
filename: fparith.bib
label: Mezzarobba:2023:REA
author: Marc Mezzarobba
title: Rounding error analysis of linear recurrences using generating series
journal: j-ELECTRON-TRANS-NUMER-ANAL
volume: 58
pages: 196--227
year: 2023
ISSN: 1068-9613 (print), 1097-4067 (electronic) OR 10689613 (print), 10974067 (electronic)
ISSNL: 1068-9613 OR 10689613
bibdate: Mon Jun 3 08:23:58 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/etna.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.06.03 08:23:58 MDT
fjournal: Electronic Transactions on Numerical Analysis
acknowledgement: ack-nhfb
ajournal: Electron. Trans. Numer. Anal.
journalURL: http://etna.mcs.kent.edu/
rawauthor: Marc Mezzarobba
rawtitle: Rounding error analysis of linear recurrences using generating series
URL:
https://etna.math.kent.edu/vol.58.2023/pp196-227.dir/pp196-227.pdf; https://etna.math.kent.edu/volumes/2021-2030/vol58/abstract.php?vol=58&pages=196-227

abstract:
We develop a toolbox for the error analysis of linear recurrences with constant or polynomial coefficients, based on generating series, Cauchy's method of majorants, and simple results from analytic combinatorics. We illustrate the power of the approach by several nontrivial application examples. Among these examples are a new worst-case analysis of an algorithm for computing the Bernoulli numbers and a new algorithm for evaluating differentially finite functions in interval arithmetic while avoiding interval blow-up

rawabstract:
We develop a toolbox for the error analysis of linear recurrences with constant or polynomial coefficients, based on generating series, Cauchy's method of majorants, and simple results from analytic combinatorics. We illustrate the power of the approach by several nontrivial application examples. Among these examples are a new worst-case analysis of an algorithm for computing the Bernoulli numbers and a new algorithm for evaluating differentially finite functions in interval arithmetic while avoiding interval blow-up

entry:
@Article{Mezzarobba:2023:REA,
  author =       "Marc Mezzarobba",
  title =        "Rounding error analysis of linear recurrences using
                 generating series",
  journal =      j-ELECTRON-TRANS-NUMER-ANAL,
  volume =       "58",
  pages =        "196--227",
  year =         "2023",
  CODEN =        "????",
  ISSN =         "1068-9613 (print), 1097-4067 (electronic)",
  ISSN-L =       "1068-9613",
  bibdate =      "Mon Jun 3 08:23:58 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/etna.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://etna.math.kent.edu/vol.58.2023/pp196-227.dir/pp196-227.pdf;
                 https://etna.math.kent.edu/volumes/2021-2030/vol58/abstract.php?vol=58&pages=196-227",
  abstract =     "We develop a toolbox for the error analysis of linear
                 recurrences with constant or polynomial coefficients,
                 based on generating series, Cauchy's method of
                 majorants, and simple results from analytic
                 combinatorics. We illustrate the power of the approach
                 by several nontrivial application examples. Among these
                 examples are a new worst-case analysis of an algorithm
                 for computing the Bernoulli numbers and a new algorithm
                 for evaluating differentially finite functions in
                 interval arithmetic while avoiding interval blow-up",
  acknowledgement = ack-nhfb,
  ajournal =     "Electron. Trans. Numer. Anal.",
  fjournal =     "Electronic Transactions on Numerical Analysis",
  journal-URL =  "http://etna.mcs.kent.edu/",
}


bibtype: techreport
filename: fparith.bib
label: Micikevicius:2023:OBF
title: OCP 8-bit floating point specification (OFP8): Revision 1.0.
type: Technical report
institution: Open Compute Project
pages: 16
day: 20
month: jun
monthnumber: 6
year: 2023
bibdate: Thu Nov 30 05:39:50 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.30 05:39:50 ???
acknowledgement: ack-nhfb
rawtitle: {OCP} 8-bit floating point specification ({OFP8}): Revision 1.0.
author:
Paulius Micikevicius and Stuart Oberman and Marius Cornea Pradeep Dubey and Andres Rodriguez and Ian Bratt and Richard Grisenthwaite and Chiachen Chou Norm Jouppi and Amber Huffman and Michael Schulte and Ralph Wittig and Dharmesh Jani and Summer Deng

URL:
https://www.opencompute.org/documents/ocp-8-bit-floating-point-specification-ofp8-revision-1-0-2023-06-20-pdf

rawauthor:
Paulius Micikevicius and Stuart Oberman and Marius Cornea Pradeep Dubey and Andres Rodriguez and Ian Bratt and Richard Grisenthwaite and Chiachen Chou Norm Jouppi and Amber Huffman and Michael Schulte and Ralph Wittig and Dharmesh Jani and Summer Deng

entry:
@TechReport{Micikevicius:2023:OBF,
  author =       "Paulius Micikevicius and Stuart Oberman and Marius
                 Cornea Pradeep Dubey and Andres Rodriguez and Ian Bratt
                 and Richard Grisenthwaite and Chiachen Chou Norm Jouppi
                 and Amber Huffman and Michael Schulte and Ralph Wittig
                 and Dharmesh Jani and Summer Deng",
  title =        "{OCP} 8-bit floating point specification ({OFP8}):
                 Revision 1.0.",
  type =         "Technical report",
  institution =  "Open Compute Project",
  address =      "????",
  pages =        "16",
  day =          "20",
  month =        jun,
  year =         "2023",
  bibdate =      "Thu Nov 30 05:39:50 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.opencompute.org/documents/ocp-8-bit-floating-point-specification-ofp8-revision-1-0-2023-06-20-pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Mikaitis:2023:MMT
author: Mantas Mikaitis
title: Monotonicity of Multi-Term Floating-Point Adders
journal: arxiv.org
pages: 1--13
day: 3
month: apr
monthnumber: 4
year: 2023
bibdate: Thu Apr 06 15:33:19 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib
bibtimestamp: 2023.04.06 15:33:19 ???
URL: https://arxiv.org/pdf/2304.01407.pdf
keywords: dot product; floating-point arithmetic; matrix multiply; monotonicity; multi-term addition
remark: arXiv:2304.01407v1
acknowledgement: ack-nhfb
rawauthor: Mantas Mikaitis
rawtitle: Monotonicity of Multi-Term Floating-Point Adders
abstract:
In the literature on algorithms for performing the multi-term addition $ s_n = sum _i = 1^n x_i $ using floating-point arithmetic it is often shown that a hardware unit that has single normalization and rounding improves precision, area, latency, and power consumption, compared with the use of standard add or fused multiply--add units. However, non-monotonicity can appear when computing sums with a subclass of multi-term addition units, which currently is not explored in the literature. We demonstrate that common techniques for performing multi-term addition with $ n geq 4 $, without normalization of intermediate quantities, can result in non-monotonicity-increasing one of the addends $ x_i $ decreases the sum sn. Summation is required in dot product and matrix multiplication operations, operations that have increasingly started appearing in the hardware of supercomputers, thus knowing where monotonicity is preserved can be of interest to the users of these machines. Our results suggest that non-monotonicity of summation, in some of the commercial hardware devices that implement a specific class of multi-term adders, is a feature that may have appeared unintentionally as a consequence of design choices that reduce circuit area and other metrics. To demonstrate our findings, we use formal proofs as well as a numerical simulation of non-monotonic multi-term adders in MATLAB

rawabstract:
In the literature on algorithms for performing the multi-term addition $ s_n = \sum_{i = 1}^n x_i $ using floating-point arithmetic it is often shown that a hardware unit that has single normalization and rounding improves precision, area, latency, and power consumption, compared with the use of standard add or fused multiply--add units. However, non-monotonicity can appear when computing sums with a subclass of multi-term addition units, which currently is not explored in the literature. We demonstrate that common techniques for performing multi-term addition with $ n \geq 4 $, without normalization of intermediate quantities, can result in non-monotonicity-increasing one of the addends $ x_i $ decreases the sum sn. Summation is required in dot product and matrix multiplication operations, operations that have increasingly started appearing in the hardware of supercomputers, thus knowing where monotonicity is preserved can be of interest to the users of these machines. Our results suggest that non-monotonicity of summation, in some of the commercial hardware devices that implement a specific class of multi-term adders, is a feature that may have appeared unintentionally as a consequence of design choices that reduce circuit area and other metrics. To demonstrate our findings, we use formal proofs as well as a numerical simulation of non-monotonic multi-term adders in MATLAB

entry:
@Article{Mikaitis:2023:MMT,
  author =       "Mantas Mikaitis",
  title =        "Monotonicity of Multi-Term Floating-Point Adders",
  journal =      "arxiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--13",
  day =          "3",
  month =        apr,
  year =         "2023",
  bibdate =      "Thu Apr 06 15:33:19 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib",
  URL =          "https://arxiv.org/pdf/2304.01407.pdf",
  abstract =     "In the literature on algorithms for performing the
                 multi-term addition $ s_n = \sum_{i = 1}^n x_i $ using
                 floating-point arithmetic it is often shown that a
                 hardware unit that has single normalization and
                 rounding improves precision, area, latency, and power
                 consumption, compared with the use of standard add or
                 fused multiply--add units. However, non-monotonicity
                 can appear when computing sums with a subclass of
                 multi-term addition units, which currently is not
                 explored in the literature. We demonstrate that common
                 techniques for performing multi-term addition with $ n
                 \geq 4 $, without normalization of intermediate
                 quantities, can result in non-monotonicity-increasing
                 one of the addends $ x_i $ decreases the sum sn.
                 Summation is required in dot product and matrix
                 multiplication operations, operations that have
                 increasingly started appearing in the hardware of
                 supercomputers, thus knowing where monotonicity is
                 preserved can be of interest to the users of these
                 machines. Our results suggest that non-monotonicity of
                 summation, in some of the commercial hardware devices
                 that implement a specific class of multi-term adders,
                 is a feature that may have appeared unintentionally as
                 a consequence of design choices that reduce circuit
                 area and other metrics. To demonstrate our findings, we
                 use formal proofs as well as a numerical simulation of
                 non-monotonic multi-term adders in MATLAB",
  acknowledgement = ack-nhfb,
  keywords =     "dot product; floating-point arithmetic; matrix
                 multiply; monotonicity; multi-term addition",
  remark =       "arXiv:2304.01407v1",
}


bibtype: article
filename: fparith.bib
label: Murillo:2023:GPB
author: Raul Murillo and Alberto A. Del Barrio and Guillermo Botella and Christian Pilato
title: Generating Posit-Based Accelerators With High-Level Synthesis
journal: j-IEEE-TRANS-CIRCUITS-SYST-1
volume: 70
number: 10
pages: 4040--4052
year: 2023
DOI: https://doi.org/10.1109/TCSI.2023.3299009
ISSN: 1549-8328 (print), 1558-0806 (electronic) OR 15498328 (print), 15580806 (electronic)
ISSNL: 1549-8328 OR 15498328
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
fjournal: IEEE Transactions on Circuits and Systems I: Regular Papers
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919
rawauthor: Raul Murillo and Alberto A. {Del Barrio} and Guillermo Botella and Christian Pilato
rawtitle: Generating Posit-Based Accelerators With High-Level Synthesis
entry:
@Article{Murillo:2023:GPB,
  author =       "Raul Murillo and Alberto A. {Del Barrio} and Guillermo
                 Botella and Christian Pilato",
  title =        "Generating Posit-Based Accelerators With High-Level
                 Synthesis",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  volume =       "70",
  number =       "10",
  pages =        "4040--4052",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSI.2023.3299009",
  ISSN =         "1549-8328 (print), 1558-0806 (electronic)",
  ISSN-L =       "1549-8328",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I: Regular
                 Papers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
}


bibtype: article
filename: fparith.bib
label: Murillo:2023:HMP
author: Raul Murillo and Javier Hormigo and Alberto A. Del Barrio and Guillermo Botella
title: HUB Meets Posit: Arithmetic Units Implementation
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
pages: 1--1
year: 2023
DOI: https://doi.org/10.1109/TCSII.2023.3307488
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Raul Murillo and Javier Hormigo and Alberto A. {Del Barrio} and Guillermo Botella
rawtitle: {HUB} Meets Posit: Arithmetic Units Implementation
entry:
@Article{Murillo:2023:HMP,
  author =       "Raul Murillo and Javier Hormigo and Alberto A. {Del
                 Barrio} and Guillermo Botella",
  title =        "{HUB} Meets Posit: Arithmetic Units Implementation",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  pages =        "1--1",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSII.2023.3307488",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
}


bibtype: inproceedings
filename: fparith.bib
label: Murillo:2023:PPL
author: Raul Murillo and David Mallasen and Alberto A. Del Barrio and Guillermo Botella
title: PLAUs: Posit Logarithmic Approximate Units to Implement Low-Cost Operations with Real Numbers
crossref: Gustafson:2023:NGA
pages: 171--188
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_11
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Raul Murillo and David Mallas{\'e}n and Alberto A. Del Barrio and Guillermo Botella
rawtitle: {PLAUs}: Posit Logarithmic Approximate Units to Implement Low-Cost Operations with Real Numbers
entry:
@InProceedings{Murillo:2023:PPL,
  author =       "Raul Murillo and David Mallas{\'e}n and Alberto A. Del
                 Barrio and Guillermo Botella",
  title =        "{PLAUs}: Posit Logarithmic Approximate Units to
                 Implement Low-Cost Operations with Real Numbers",
  crossref =     "Gustafson:2023:NGA",
  pages =        "171--188",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_11",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Murillo:2023:SDA
author: Raul Murillo and Alberto A. Del Barrio and Guillermo Botella
editor: IEEE
title: A Suite of Division Algorithms for Posit Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 41--44
year: 2023
DOI: https://doi.org/10.1109/ASAP57973.2023.00020
bibdate: Thu Nov 16 15:55:09 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.16 15:55:09 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Raul Murillo and Alberto A. {Del Barrio} and Guillermo Botella
raweditor: {IEEE}
rawtitle: A Suite of Division Algorithms for Posit Arithmetic
booktitle:
2023 IEEE 34th International Conference on Application-specific Systems, Architectures and Processors (ASAP): ASAP 2023, 19--21 July 2023, Porto, Portugal

ISBN13:
979-83-503-4686-2 (print), 979-83-503-4685-5 (e-book) OR 9798350346862 (print), 9798350346855 (ebook)

rawbooktitle:
2023 {IEEE 34th International Conference on Application-specific Systems, Architectures and Processors (ASAP): ASAP 2023, 19--21 July 2023, Porto, Portugal}

entry:
@InProceedings{Murillo:2023:SDA,
  author =       "Raul Murillo and Alberto A. {Del Barrio} and Guillermo
                 Botella",
  editor =       "{IEEE}",
  booktitle =    "2023 {IEEE 34th International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP): ASAP 2023, 19--21 July 2023, Porto,
                 Portugal}",
  title =        "A Suite of Division Algorithms for Posit Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "41--44",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ASAP57973.2023.00020",
  ISBN-13 =      "979-83-503-4686-2 (print), 979-83-503-4685-5
                 (e-book)",
  bibdate =      "Thu Nov 16 15:55:09 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Mushtak:2023:FNP
author: Noble Mushtak and Daniel Lemire
title: Fast number parsing without fallback
journal: j-SPE
volume: 53
number: 7
pages: 1467--1471
month: jul
monthnumber: 7
year: 2023
CODEN: SPEXBL
DOI: https://doi.org/10.1002/spe.3198
ISSN: 0038-0644 (print), 1097-024X (electronic) OR 00380644 (print), 1097024X (electronic)
ISSNL: 0038-0644 OR 00380644
bibdate: Thu Jun 29 14:46:14 MDT 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/spe.bib
bibtimestamp: 2023.06.29 14:46:14 MDT
note: See original work cite Lemire:2021:NPG.
fjournal: Software --- Practice and Experience
acknowledgement: ack-nhfb
ajournal: Softw. Pract. Exp.
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X
onlinedate: 04 March 2023
rawauthor: Noble Mushtak and Daniel Lemire
rawnote: See original work \cite{Lemire:2021:NPG}.
rawtitle: Fast number parsing without fallback
abstract:
In recent work, Lemire (2021) presented a fast algorithm to convert number strings into binary floating-point numbers. The algorithm has been adopted by several important systems: for example, it is part of the runtime libraries of GCC 12, Rust 1.55, and Go 1.16. The algorithm parses any number string with a significand containing no more than 19 digits into an IEEE floating-point number. However, there is a check leading to a fallback function to ensure correctness. This fallback function is never called in practice. We prove that the fallback is unnecessary. Thus we can slightly simplify the algorithm and its implementation.

rawabstract:
In recent work, Lemire (2021) presented a fast algorithm to convert number strings into binary floating-point numbers. The algorithm has been adopted by several important systems: for example, it is part of the runtime libraries of GCC 12, Rust 1.55, and Go 1.16. The algorithm parses any number string with a significand containing no more than 19 digits into an IEEE floating-point number. However, there is a check leading to a fallback function to ensure correctness. This fallback function is never called in practice. We prove that the fallback is unnecessary. Thus we can slightly simplify the algorithm and its implementation.

entry:
@Article{Mushtak:2023:FNP,
  author =       "Noble Mushtak and Daniel Lemire",
  title =        "Fast number parsing without fallback",
  journal =      j-SPE,
  volume =       "53",
  number =       "7",
  pages =        "1467--1471",
  month =        jul,
  year =         "2023",
  CODEN =        "SPEXBL",
  DOI =          "https://doi.org/10.1002/spe.3198",
  ISSN =         "0038-0644 (print), 1097-024X (electronic)",
  ISSN-L =       "0038-0644",
  bibdate =      "Thu Jun 29 14:46:14 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/spe.bib",
  note =         "See original work \cite{Lemire:2021:NPG}.",
  abstract =     "In recent work, Lemire (2021) presented a fast
                 algorithm to convert number strings into binary
                 floating-point numbers. The algorithm has been adopted
                 by several important systems: for example, it is part
                 of the runtime libraries of GCC 12, Rust 1.55, and Go
                 1.16. The algorithm parses any number string with a
                 significand containing no more than 19 digits into an
                 IEEE floating-point number. However, there is a check
                 leading to a fallback function to ensure correctness.
                 This fallback function is never called in practice. We
                 prove that the fallback is unnecessary. Thus we can
                 slightly simplify the algorithm and its
                 implementation.",
  acknowledgement = ack-nhfb,
  ajournal =     "Softw. Pract. Exp.",
  fjournal =     "Software --- Practice and Experience",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X",
  onlinedate =   "04 March 2023",
}


bibtype: article
filename: fparith.bib
label: Nadalini:2023:RPF
author: Davide Nadalini and Manuele Rusci and Luca Benini and Francesco Conti
journal: j-FUT-GEN-COMP-SYS
volume: 149
pages: 212--226
month: dec
monthnumber: 12
year: 2023
CODEN: FGSEVI
DOI: https://doi.org/10.1016/j.future.2023.07.020
ISSN: 0167-739X (print), 1872-7115 (electronic) OR 0167739X (print), 18727115 (electronic)
ISSNL: 0167-739X OR 0167739X
bibdate: Thu Sep 21 08:18:51 MDT 2023
bibtimestamp: 2023.09.21 08:18:51 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0167739X23002728
fjournal: Future Generation Computer Systems
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/0167739X
rawauthor: Davide Nadalini and Manuele Rusci and Luca Benini and Francesco Conti
title:
Reduced precision floating-point optimization for Deep Neural Network On-Device Learning on microcontrollers

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/futgencompsys2020.bib

rawtitle:
Reduced precision floating-point optimization for {Deep Neural Network On-Device Learning} on microcontrollers

entry:
@Article{Nadalini:2023:RPF,
  author =       "Davide Nadalini and Manuele Rusci and Luca Benini and
                 Francesco Conti",
  title =        "Reduced precision floating-point optimization for
                 {Deep Neural Network On-Device Learning} on
                 microcontrollers",
  journal =      j-FUT-GEN-COMP-SYS,
  volume =       "149",
  number =       "??",
  pages =        "212--226",
  month =        dec,
  year =         "2023",
  CODEN =        "FGSEVI",
  DOI =          "https://doi.org/10.1016/j.future.2023.07.020",
  ISSN =         "0167-739X (print), 1872-7115 (electronic)",
  ISSN-L =       "0167-739X",
  bibdate =      "Thu Sep 21 08:18:51 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/futgencompsys2020.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0167739X23002728",
  acknowledgement = ack-nhfb,
  fjournal =     "Future Generation Computer Systems",
  journal-URL =  "http://www.sciencedirect.com/science/journal/0167739X",
}


bibtype: inproceedings
filename: fparith.bib
label: Nadalini:2023:TWR
editor: IEEE
booktitle: 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2023
DOI: https://doi.org/10.1109/ISVLSI59464.2023.10238679
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawbooktitle: {2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}
raweditor: {IEEE}
author:
Alessandro Nadalini and Georg Rutishauser and Alessio Burrello and Nazareno Bruschi and Angelo Garofalo and Luca Benini and Francesco Conti and Davide Rossi

title:
A 3 TOPS / W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks

rawauthor:
Alessandro Nadalini and Georg Rutishauser and Alessio Burrello and Nazareno Bruschi and Angelo Garofalo and Luca Benini and Francesco Conti and Davide Rossi

rawtitle:
A 3 {TOPS\slash W RISC-V} Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks

entry:
@InProceedings{Nadalini:2023:TWR,
  author =       "Alessandro Nadalini and Georg Rutishauser and Alessio
                 Burrello and Nazareno Bruschi and Angelo Garofalo and
                 Luca Benini and Francesco Conti and Davide Rossi",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Computer Society Annual Symposium on VLSI
                 (ISVLSI)}",
  title =        "A 3 {TOPS\slash W RISC-V} Parallel Cluster for
                 Inference of Fine-Grain Mixed-Precision Quantized
                 Neural Networks",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISVLSI59464.2023.10238679",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: Nazareth:2023:CGN
author: John Lawrence Nazareth
title: Concise Guide to Numerical Algorithmics: The Foundations and Spirit of Scientific Computing
publisher: pub-SV
address: pub-SV:adr
pages: 1--6
year: 2023
DOI: https://doi.org/10.1007/978-3-031-21762-3
ISBN: 3-031-21762-4 OR 3031217624
ISBN13: 978-3-031-21762-3 OR 9783031217623
ISSN: 2191-5776 OR 21915776
ISSNL: 2191-5768 OR 21915768
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
series: SpringerBriefs in Computer Science
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: John Lawrence Nazareth
rawtitle: Concise Guide to Numerical Algorithmics: The Foundations and Spirit of Scientific Computing
entry:
@Book{Nazareth:2023:CGN,
  author =       "John Lawrence Nazareth",
  title =        "Concise Guide to Numerical Algorithmics: The
                 Foundations and Spirit of Scientific Computing",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-21762-3",
  ISBN =         "3-031-21762-4",
  ISBN-13 =      "978-3-031-21762-3",
  ISSN =         "2191-5776",
  ISSN-L =       "2191-5768",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "SpringerBriefs in Computer Science",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Noh:2023:FFD
author: Seock-Hwan Noh and Jahyun Koo and Seunghyun Lee and Jongse Park and Jaeha Kung
title: FlexBlock: a Flexible DNN Training Accelerator With Multi-Mode Block Floating Point Support
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 9
pages: 2522--2535
month: sep
monthnumber: 9
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2023.3253050
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Aug 10 06:30:56 2023
bibtimestamp: 2023.08.10 06:30:56 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Seock-Hwan Noh and Jahyun Koo and Seunghyun Lee and Jongse Park and Jaeha Kung
rawtitle: {FlexBlock}: a Flexible {DNN} Training Accelerator With Multi-Mode Block Floating Point Support
entry:
@Article{Noh:2023:FFD,
  author =       "Seock-Hwan Noh and Jahyun Koo and Seunghyun Lee and
                 Jongse Park and Jaeha Kung",
  title =        "{FlexBlock}: a Flexible {DNN} Training Accelerator
                 With Multi-Mode Block Floating Point Support",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "9",
  pages =        "2522--2535",
  month =        sep,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3253050",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Aug 10 06:30:56 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: misc
filename: fparith.bib
label: NVIDIA:2023:FPI
author: NVIDIA Corporation
title: Floating Point and IEEE 754 Compliance for NVIDIA GPUs
pages: 2522--2535
month: oct
monthnumber: 10
year: 2023
bibdate: Fri Dec 01 12:26:53 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.01 12:26:53 ???
URL: https://docs.nvidia.com/cuda/floating-point/
acknowledgement: ack-nhfb
howpublished: NVIDIA Web site.
rawauthor: {NVIDIA Corporation}
rawtitle: Floating Point and {IEEE 754} Compliance for {NVIDIA GPUs}
remark:
The document discusses IEEE 754 conformance, CUDA, fused multiply-add, dot products, and GPU issues. It also says: ``NVIDIA GPUs differ from the x86 architecture in that rounding modes are encoded within each floating point instruction instead of dynamically using a floating point control word. Trap handlers for floating point exceptions are not supported. On the GPU there is no status flag to indicate when calculations have overflowed, underflowed, or have involved inexact arithmetic.''

entry:
@Misc{NVIDIA:2023:FPI,
  author =       "{NVIDIA Corporation}",
  title =        "Floating Point and {IEEE 754} Compliance for {NVIDIA
                 GPUs}",
  howpublished = "NVIDIA Web site.",
  month =        oct,
  year =         "2023",
  bibdate =      "Fri Dec 01 12:26:53 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://docs.nvidia.com/cuda/floating-point/",
  acknowledgement = ack-nhfb,
  remark =       "The document discusses IEEE 754 conformance, CUDA,
                 fused multiply-add, dot products, and GPU issues. It
                 also says: ``NVIDIA GPUs differ from the x86
                 architecture in that rounding modes are encoded within
                 each floating point instruction instead of dynamically
                 using a floating point control word. Trap handlers for
                 floating point exceptions are not supported. On the GPU
                 there is no status flag to indicate when calculations
                 have overflowed, underflowed, or have involved inexact
                 arithmetic.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Oh:2023:RLR
author: Hyun Woo Oh and Seongmo An and Won Sik Jeong and Seung Eun Lee
editor: IEEE
booktitle: 2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
title: RF2P: a Lightweight RISC Processor Optimized for Rapid Migration from IEEE-754 to Posit
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2023
DOI: https://doi.org/10.1109/ISLPED58423.2023.10244582
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Hyun Woo Oh and Seongmo An and Won Sik Jeong and Seung Eun Lee
rawbooktitle: {2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)}
raweditor: {IEEE}
rawtitle: {RF2P}: a Lightweight {RISC} Processor Optimized for Rapid Migration from {IEEE-754} to Posit
entry:
@InProceedings{Oh:2023:RLR,
  author =       "Hyun Woo Oh and Seongmo An and Won Sik Jeong and Seung
                 Eun Lee",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE/ACM International Symposium on Low Power
                 Electronics and Design (ISLPED)}",
  title =        "{RF2P}: a Lightweight {RISC} Processor Optimized for
                 Rapid Migration from {IEEE-754} to Posit",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISLPED58423.2023.10244582",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: P:2023:AOF
author: Gayathri G P and Jaya S and Krishnakumar Rao S
editor: IEEE
booktitle: 2023 International Conference on Control, Communication and Computing (ICCC)
title: An Area Optimized Floating-Point Coprocessor for RISC-V Processor
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2023
DOI: https://doi.org/10.1109/ICCC57789.2023.10165397
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawauthor: Gayathri G P and Jaya S and Krishnakumar Rao S
rawbooktitle: {2023 International Conference on Control, Communication and Computing (ICCC)}
raweditor: {IEEE}
rawtitle: An Area Optimized Floating-Point Coprocessor for {RISC-V} Processor
entry:
@InProceedings{P:2023:AOF,
  author =       "Gayathri G P and Jaya S and Krishnakumar Rao S",
  editor =       "{IEEE}",
  booktitle =    "{2023 International Conference on Control,
                 Communication and Computing (ICCC)}",
  title =        "An Area Optimized Floating-Point Coprocessor for
                 {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICCC57789.2023.10165397",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: P:2023:ITO
author: Ponsuganth Ilangovan P. and Rohan Rayan and Vinay Shankar Saxena
title: Improving the Stability of Kalman Filters with Posit Arithmetic
crossref: Gustafson:2023:NGA
pages: 134--154
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_9
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Ponsuganth Ilangovan P. and Rohan Rayan and Vinay Shankar Saxena
rawtitle: Improving the Stability of {Kalman} Filters with Posit Arithmetic
entry:
@InProceedings{P:2023:ITO,
  author =       "Ponsuganth Ilangovan P. and Rohan Rayan and Vinay
                 Shankar Saxena",
  title =        "Improving the Stability of {Kalman} Filters with Posit
                 Arithmetic",
  crossref =     "Gustafson:2023:NGA",
  pages =        "134--154",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_9",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Park:2023:FDL
editor: IEEE
booktitle: 2023 IEEE / ACM International Symposium on Low Power Electronics and Design (ISLPED)
title: Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2023
DOI: https://doi.org/10.1109/ISLPED58423.2023.10244431
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawbooktitle: {2023 {IEEE\slash ACM} International Symposium on Low Power Electronics and Design (ISLPED)}
raweditor: {IEEE}
rawtitle: {Florian}: Developing a Low-Power {RISC-V} Multicore Processor with a Shared Lightweight {FPU}
author:
Jina Park and Kyuseung Han and Eunjin Choi and Sukho Lee and Jae-Jin Lee and Woojoo Lee and Massoud Pedram

rawauthor:
Jina Park and Kyuseung Han and Eunjin Choi and Sukho Lee and Jae-Jin Lee and Woojoo Lee and Massoud Pedram

entry:
@InProceedings{Park:2023:FDL,
  author =       "Jina Park and Kyuseung Han and Eunjin Choi and Sukho
                 Lee and Jae-Jin Lee and Woojoo Lee and Massoud Pedram",
  editor =       "{IEEE}",
  booktitle =    "{2023 {IEEE\slash ACM} International Symposium on Low
                 Power Electronics and Design (ISLPED)}",
  title =        "{Florian}: Developing a Low-Power {RISC-V} Multicore
                 Processor with a Shared Lightweight {FPU}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISLPED58423.2023.10244431",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Pasca:2023:ELP
author: Bogdan Pasca and Martin Langhammer
title: Extracting low-precision floating-point adders from embedded hard FP DSP Blocks on FPGAs
crossref: IEEE:2023:PIS
pages: 139--142
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00017
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Bogdan Pasca and Martin Langhammer
rawtitle: Extracting low-precision floating-point adders from embedded hard {FP DSP} Blocks on {FPGAs}
keywords:
adder; Adders; ARITH-30; bfloat16; Computer architecture; Costs; Digital arithmetic; DSP; extraction; Field programmable gate arrays; floating-point; FP-DSP; FPGA; half-precision; mapping

entry:
@InProceedings{Pasca:2023:ELP,
  author =       "Bogdan Pasca and Martin Langhammer",
  title =        "Extracting low-precision floating-point adders from
                 embedded hard {FP DSP} Blocks on {FPGAs}",
  crossref =     "IEEE:2023:PIS",
  pages =        "139--142",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00017",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "adder; Adders; ARITH-30; bfloat16; Computer
                 architecture; Costs; Digital arithmetic; DSP;
                 extraction; Field programmable gate arrays;
                 floating-point; FP-DSP; FPGA; half-precision; mapping",
}


bibtype: article
filename: fparith.bib
label: Perez:2023:TIL
title: Training and inference of large language models using 8-bit floating point
journal: arXiv.org
pages: 1--22
day: 29
month: sep
monthnumber: 9
year: 2023
DOI: https://doi.org/10.48550/arXiv.2309.17224
bibdate: Wed Aug 07 16:34:17 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.07 16:34:17 ???
URL: https://arxiv.org/abs/2309.17224
acknowledgement: ack-nhfb
rawtitle: Training and inference of large language models using 8-bit floating point
author:
Sergio P. Perez and Yan Zhang and James Briggs and Charlie Blake and Josh Levy-Kramer and Paul Balanca and Carlo Luschi and Stephen Barlow and Andrew William Fitzgibbon

abstract:
FP8 formats are gaining popularity to boost the computational efficiency for training and inference of large deep learning models. Their main challenge is that a careful choice of scaling is needed to prevent degradation due to the reduced dynamic range compared to higher-precision formats. Although there exists ample literature about selecting such scalings for INT formats, this critical aspect has yet to be addressed for FP8. This paper presents a methodology to select the scalings for FP8 linear layers, based on dynamically updating per-tensor scales for the weights, gradients and activations. We apply this methodology to train and validate large language models of the type of GPT and Llama 2 using FP8, for model sizes ranging from 111M to 70B. To facilitate the understanding of the FP8 dynamics, our results are accompanied by plots of the per-tensor scale distribution for weights, activations and gradients during both training and inference.

rawabstract:
FP8 formats are gaining popularity to boost the computational efficiency for training and inference of large deep learning models. Their main challenge is that a careful choice of scaling is needed to prevent degradation due to the reduced dynamic range compared to higher-precision formats. Although there exists ample literature about selecting such scalings for INT formats, this critical aspect has yet to be addressed for FP8. This paper presents a methodology to select the scalings for FP8 linear layers, based on dynamically updating per-tensor scales for the weights, gradients and activations. We apply this methodology to train and validate large language models of the type of GPT and Llama 2 using FP8, for model sizes ranging from 111M to 70B. To facilitate the understanding of the FP8 dynamics, our results are accompanied by plots of the per-tensor scale distribution for weights, activations and gradients during both training and inference.

rawauthor:
Sergio P. Perez and Yan Zhang and James Briggs and Charlie Blake and Josh Levy-Kramer and Paul Balanca and Carlo Luschi and Stephen Barlow and Andrew William Fitzgibbon

entry:
@Article{Perez:2023:TIL,
  author =       "Sergio P. Perez and Yan Zhang and James Briggs and
                 Charlie Blake and Josh Levy-Kramer and Paul Balanca and
                 Carlo Luschi and Stephen Barlow and Andrew William
                 Fitzgibbon",
  title =        "Training and inference of large language models using
                 8-bit floating point",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--22",
  day =          "29",
  month =        sep,
  year =         "2023",
  DOI =          "https://doi.org/10.48550/arXiv.2309.17224",
  bibdate =      "Wed Aug 07 16:34:17 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/2309.17224",
  abstract =     "FP8 formats are gaining popularity to boost the
                 computational efficiency for training and inference of
                 large deep learning models. Their main challenge is
                 that a careful choice of scaling is needed to prevent
                 degradation due to the reduced dynamic range compared
                 to higher-precision formats. Although there exists
                 ample literature about selecting such scalings for INT
                 formats, this critical aspect has yet to be addressed
                 for FP8. This paper presents a methodology to select
                 the scalings for FP8 linear layers, based on
                 dynamically updating per-tensor scales for the weights,
                 gradients and activations. We apply this methodology to
                 train and validate large language models of the type of
                 GPT and Llama 2 using FP8, for model sizes ranging from
                 111M to 70B. To facilitate the understanding of the FP8
                 dynamics, our results are accompanied by plots of the
                 per-tensor scale distribution for weights, activations
                 and gradients during both training and inference.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Perotti:2023:YOS
author: Matteo Perotti and Matheus Cavalcante and Alessandro Ottaviano and Jiantao Liu and Luca Benini
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 70
number: 10
pages: 3732--3736
year: 2023
DOI: https://doi.org/10.1109/TCSII.2023.3292579
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Matteo Perotti and Matheus Cavalcante and Alessandro Ottaviano and Jiantao Liu and Luca Benini
title:
Yun: an Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS

rawtitle:
{Yun}: an Open-Source, 64-Bit {RISC-V}-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm {CMOS}

entry:
@Article{Perotti:2023:YOS,
  author =       "Matteo Perotti and Matheus Cavalcante and Alessandro
                 Ottaviano and Jiantao Liu and Luca Benini",
  title =        "{Yun}: an Open-Source, 64-Bit {RISC-V}-Based Vector
                 Processor With Multi-Precision Integer and
                 Floating-Point Support in 65-nm {CMOS}",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "70",
  number =       "10",
  pages =        "3732--3736",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSII.2023.3292579",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
}


bibtype: misc
filename: fparith.bib
label: Pilipovic:2023:EEN
author: Ratko Pilipovic and Patricio Bulic and Uros Lotric
title: Energy-efficient neural network learning with accuracy-adjustable floating-point multiplier
pages: 3732--3736
day: 19
month: feb
monthnumber: 2
year: 2023
DOI: https://doi.org/10.36227/techrxiv.22123127.v1
bibdate: Fri Sep 29 14:34:35 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 14:34:35 ???
acknowledgement: ack-nhfb
howpublished: TechRxiv preprint.
rawauthor: Ratko Pilipovi{\'c} and Patricio Buli{\'c} and Uro{\v{s}} Lotri{\v{c}}
rawtitle: Energy-efficient neural network learning with accuracy-adjustable floating-point multiplier
URL:
https://www.techrxiv.org/articles/preprint/Energy-efficient_neural_network_learning_with_accuracy-adjustable_floating-point_multiplier/22123127

abstract:
This paper proposes a novel approximate bfloat16 multiplier with on-the-fly adjustable accuracy for energy-efficient learning in deep neural networks. The size of the proposed multiplier is only 62% of the size of the exact bfloat16 multiplier. Furthermore, its energy footprint is up to five times smaller than the footprint of the exact bfloat multiplier. We demonstrate the advantages of the proposed multiplier in deep neural network learning, where we successfully train the ResNet-20 network on the CIFAR-10 dataset from scratch.

rawabstract:
This paper proposes a novel approximate bfloat16 multiplier with on-the-fly adjustable accuracy for energy-efficient learning in deep neural networks. The size of the proposed multiplier is only 62\% of the size of the exact bfloat16 multiplier. Furthermore, its energy footprint is up to five times smaller than the footprint of the exact bfloat multiplier. We demonstrate the advantages of the proposed multiplier in deep neural network learning, where we successfully train the ResNet-20 network on the CIFAR-10 dataset from scratch.

entry:
@Misc{Pilipovic:2023:EEN,
  author =       "Ratko Pilipovi{\'c} and Patricio Buli{\'c} and
                 Uro{\v{s}} Lotri{\v{c}}",
  title =        "Energy-efficient neural network learning with
                 accuracy-adjustable floating-point multiplier",
  howpublished = "TechRxiv preprint.",
  day =          "19",
  month =        feb,
  year =         "2023",
  DOI =          "https://doi.org/10.36227/techrxiv.22123127.v1",
  bibdate =      "Fri Sep 29 14:34:35 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.techrxiv.org/articles/preprint/Energy-efficient_neural_network_learning_with_accuracy-adjustable_floating-point_multiplier/22123127",
  abstract =     "This paper proposes a novel approximate bfloat16
                 multiplier with on-the-fly adjustable accuracy for
                 energy-efficient learning in deep neural networks. The
                 size of the proposed multiplier is only 62\% of the
                 size of the exact bfloat16 multiplier. Furthermore, its
                 energy footprint is up to five times smaller than the
                 footprint of the exact bfloat multiplier. We
                 demonstrate the advantages of the proposed multiplier
                 in deep neural network learning, where we successfully
                 train the ResNet-20 network on the CIFAR-10 dataset
                 from scratch.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Postpischil:2023:WDI
author: Eric Postpischil
pages: 3732--3736
year: 2023
bibdate: Wed Dec 20 06:59:51 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 06:59:51 ???
remark: Discusses Jim Blinn's approximate logarithm for the IEEE 32-bit binary format cite Blinn:1997:JBC.
acknowledgement: ack-nhfb
howpublished: Stack Overflow Web site.
rawauthor: Eric Postpischil
title:
Why does the integer representation of a floating point number offer a piecewise linear approximation to the logarithm?

URL:
https://stackoverflow.com/questions/75772363/why-does-the-integer-representation-of-a-floating-point-number-offer-a-piecewise

rawtitle:
Why does the integer representation of a floating point number offer a piecewise linear approximation to the logarithm?

entry:
@Misc{Postpischil:2023:WDI,
  author =       "Eric Postpischil",
  title =        "Why does the integer representation of a floating
                 point number offer a piecewise linear approximation to
                 the logarithm?",
  howpublished = "Stack Overflow Web site.",
  year =         "2023",
  bibdate =      "Wed Dec 20 06:59:51 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://stackoverflow.com/questions/75772363/why-does-the-integer-representation-of-a-floating-point-number-offer-a-piecewise",
  acknowledgement = ack-nhfb,
  remark =       "Discusses Jim Blinn's approximate logarithm for the
                 IEEE 32-bit binary format \cite{Blinn:1997:JBC}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Ren:2023:EAM
author: Pengchang Ren and Reiji Suda and Vorapong Suppakitpaisarn
title: Efficient Additions and Montgomery Reductions of Large Integers for SIMD
crossref: IEEE:2023:PIS
pages: 48--59
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00034
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Pengchang Ren and Reiji Suda and Vorapong Suppakitpaisarn
rawtitle: Efficient Additions and {Montgomery} Reductions of Large Integers for {SIMD}
keywords:
additions; ARITH-30; arithmetic for cryptography; AVX-512; Cryptography; Digital arithmetic; Montgomery reduction; Pipelines; Program processors; SIMD; Standards; SVE

entry:
@InProceedings{Ren:2023:EAM,
  author =       "Pengchang Ren and Reiji Suda and Vorapong
                 Suppakitpaisarn",
  title =        "Efficient Additions and {Montgomery} Reductions of
                 Large Integers for {SIMD}",
  crossref =     "IEEE:2023:PIS",
  pages =        "48--59",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00034",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "additions; ARITH-30; arithmetic for cryptography;
                 AVX-512; Cryptography; Digital arithmetic; Montgomery
                 reduction; Pipelines; Program processors; SIMD;
                 Standards; SVE",
}


bibtype: article
filename: fparith.bib
label: Robert:2023:FMM
author: Jean-Marc Robert and Pascal Veron
journal: j-J-CRYPTO-ENG
volume: 13
number: 1
pages: 37--55
month: apr
monthnumber: 4
year: 2023
DOI: https://doi.org/10.1007/s13389-021-00278-3
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Fri Jun 2 12:32:10 MDT 2023
bibtimestamp: 2023.06.02 12:32:10 MDT
URL: https://link.springer.com/article/10.1007/s13389-021-00278-3
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
ajournal: J. Crypto. Eng.
journalURL: http://link.springer.com/journal/13389
rawauthor: Jean-Marc Robert and Pascal V{\'e}ron
title:
Faster multiplication over $ mathbb F_2 [X] $ using AVX512 instruction set and VPCLMULQDQ instruction

rawtitle:
Faster multiplication over {$ \mathbb {F}_2 [X] $} using {AVX512} instruction set and {VPCLMULQDQ} instruction

entry:
@Article{Robert:2023:FMM,
  author =       "Jean-Marc Robert and Pascal V{\'e}ron",
  title =        "Faster multiplication over {$ \mathbb {F}_2 [X] $}
                 using {AVX512} instruction set and {VPCLMULQDQ}
                 instruction",
  journal =      j-J-CRYPTO-ENG,
  volume =       "13",
  number =       "1",
  pages =        "37--55",
  month =        apr,
  year =         "2023",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-021-00278-3",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Fri Jun 2 12:32:10 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "https://link.springer.com/article/10.1007/s13389-021-00278-3",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Crypto. Eng.",
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Rump:2023:IPP
author: Siegfried M. Rump
title: IEEE-754 Precision-$p$ base-$ beta $ Arithmetic Implemented in Binary
journal: j-TOMS
volume: 49
number: 4
pages: 32:1--32:??
month: dec
monthnumber: 12
year: 2023
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3596218
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Sat Dec 23 05:40:24 MST 2023
bibtimestamp: 2023.12.23 05:40:24 MST
URL: https://dl.acm.org/doi/10.1145/3596218; https://www.tuhh.de/ti3/paper/rump/Ru23b.pdf
fjournal: ACM Transactions on Mathematical Software (TOMS)
remark: Received 6 December 2021; revised 10 October 2022; accepted 30 March 2023.
acknowledgement: ack-nhfb
ajournal: ACM Trans. Math. Softw.
articleno: 32
journalURL: https://dl.acm.org/loi/toms
rawauthor: Siegfried M. Rump
rawtitle: {IEEE-754} Precision-$p$ base-$ \beta $ Arithmetic Implemented in Binary
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
We show how an IEEE-754 conformant precision-$p$ base-$ beta $ arithmetic can be implemented based on some binary floating-point and/or integer arithmetic. This includes the four basic operations and square root subject to the five IEEE-754 rounding modes, namely he nearest roundings with roundTiesToEven and roundTiesToAway, the directed roundings downwards and upwards, as well as rounding towards zero. Exceptional values like $ infty $ or NaN are covered according to the IEEE-754 arithmetic standard. The results of the precision-$p$ base-$ beta $ operations are computed using some underlying precision-$q$ binary arithmetic. We distinguish two cases. When using a precision-$q$ binary integer arithmetic, the base-$ beta $ precision $p$ is limited for all operations by $ beta ^2 p leq 2^q$, whereas using a precision-$q$ binary floating-point arithmetic imposes stronger limits on the base-$ beta $ precision, namely $ beta ^2p leq 2^q$ for addition and multiplication, $ beta ^2p leq 2^q - 1$ for division and $ beta ^2p leq 2^q - 3$ for the square root. Those limitations cannot be improved. The algorithms are implemented in a Matlab/Octave flbeta-toolbox with the choice of using uint64 or binary64 as underlying arithmetic. The former allows larger precisions, the latter is advantageous for the square root, whereas computing times are similar. The flbeta-toolbox offers precision-$p$ base-$ beta $ scalar, vector and matrix operations including sparse matrices as well as corresponding interval operations. The base $ beta $ can be chosen in the range $ beta $ [2,64]. The flbeta-toolbox will be part of Version 13 of INTLAB [18], the Matlab/Octave toolbox for reliable computing.

rawabstract:
We show how an IEEE-754 conformant precision-$p$ base-$ \beta $ arithmetic can be implemented based on some binary floating-point and/or integer arithmetic. This includes the four basic operations and square root subject to the five IEEE-754 rounding modes, namely he nearest roundings with roundTiesToEven and roundTiesToAway, the directed roundings downwards and upwards, as well as rounding towards zero. Exceptional values like $ \infty $ or NaN are covered according to the IEEE-754 arithmetic standard. The results of the precision-$p$ base-$ \beta $ operations are computed using some underlying precision-$q$ binary arithmetic. We distinguish two cases. When using a precision-$q$ binary integer arithmetic, the base-$ \beta $ precision $p$ is limited for all operations by $ \beta^{2 p} \leq 2^q$, whereas using a precision-$q$ binary floating-point arithmetic imposes stronger limits on the base-$ \beta $ precision, namely $ \beta^{2p} \leq 2^q$ for addition and multiplication, $ \beta^{2p} \leq 2^{q - 1}$ for division and $ \beta^{2p} \leq 2^{q - 3}$ for the square root. Those limitations cannot be improved. The algorithms are implemented in a Matlab/Octave flbeta-toolbox with the choice of using uint64 or binary64 as underlying arithmetic. The former allows larger precisions, the latter is advantageous for the square root, whereas computing times are similar. The flbeta-toolbox offers precision-$p$ base-$ \beta $ scalar, vector and matrix operations including sparse matrices as well as corresponding interval operations. The base $ \beta $ can be chosen in the range $ \beta $ [2,64]. The flbeta-toolbox will be part of Version 13 of INTLAB [18], the Matlab/Octave toolbox for reliable computing.

entry:
@Article{Rump:2023:IPP,
  author =       "Siegfried M. Rump",
  title =        "{IEEE-754} Precision-$p$ base-$ \beta $ Arithmetic
                 Implemented in Binary",
  journal =      j-TOMS,
  volume =       "49",
  number =       "4",
  pages =        "32:1--32:??",
  month =        dec,
  year =         "2023",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3596218",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Sat Dec 23 05:40:24 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3596218;
                 https://www.tuhh.de/ti3/paper/rump/Ru23b.pdf",
  abstract =     "We show how an IEEE-754 conformant precision-$p$
                 base-$ \beta $ arithmetic can be implemented based on
                 some binary floating-point and/or integer arithmetic.
                 This includes the four basic operations and square root
                 subject to the five IEEE-754 rounding modes, namely he
                 nearest roundings with roundTiesToEven and
                 roundTiesToAway, the directed roundings downwards and
                 upwards, as well as rounding towards zero. Exceptional
                 values like $ \infty $ or NaN are covered according to
                 the IEEE-754 arithmetic standard.

                 The results of the precision-$p$ base-$ \beta $
                 operations are computed using some underlying
                 precision-$q$ binary arithmetic. We distinguish two
                 cases. When using a precision-$q$ binary integer
                 arithmetic, the base-$ \beta $ precision $p$ is limited
                 for all operations by $ \beta^{2 p} \leq 2^q$, whereas
                 using a precision-$q$ binary floating-point arithmetic
                 imposes stronger limits on the base-$ \beta $
                 precision, namely $ \beta^{2p} \leq 2^q$ for addition
                 and multiplication, $ \beta^{2p} \leq 2^{q - 1}$ for
                 division and $ \beta^{2p} \leq 2^{q - 3}$ for the
                 square root. Those limitations cannot be improved.

                 The algorithms are implemented in a Matlab/Octave
                 flbeta-toolbox with the choice of using uint64 or
                 binary64 as underlying arithmetic. The former allows
                 larger precisions, the latter is advantageous for the
                 square root, whereas computing times are similar. The
                 flbeta-toolbox offers precision-$p$ base-$ \beta $
                 scalar, vector and matrix operations including sparse
                 matrices as well as corresponding interval operations.
                 The base $ \beta $ can be chosen in the range $ \beta $
                 [2,64]. The flbeta-toolbox will be part of Version 13
                 of INTLAB [18], the Matlab/Octave toolbox for reliable
                 computing.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Math. Softw.",
  articleno =    "32",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  remark =       "Received 6 December 2021; revised 10 October 2022;
                 accepted 30 March 2023.",
}


bibtype: inproceedings
filename: fparith.bib
label: Rydahl:2023:PPA
author: Anton Rydahl and Joseph Huber and Ethan Luis Mcdonough and Johannes Doerfert
title: Precision and Performance Analysis of C Standard Math Library Functions on GPUs
publisher: pub-ACM
address: pub-ACM:adr
pages: 32:1--32:??
month: nov
monthnumber: 11
year: 2023
DOI: https://doi.org/10.1145/3624062.3624166
bibdate: Fri Dec 8 12:56:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 12:56:08 ???
acknowledgement: ack-nhfb
rawauthor: Anton Rydahl and Joseph Huber and Ethan Luis Mcdonough and Johannes Doerfert
rawtitle: Precision and Performance Analysis of {C} Standard Math Library Functions on {GPUs}
booktitle:
Proceedings of the SC 23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis

abstract:
With the advent of GPU computing, executing large program sections on accelerators has become increasingly important. Efforts are being made to support the C standard library, LIBC, on GPUs via LLVM machinery. Therefore, the C standard math library, LIBM, must be supported on GPUs. So far, LLVM frontends, such as Clang, have relied on GPU vendor implementations of LIBM functionality wrapped into (mostly) LIBM-compatible forwarding functions.par We propose a novel LIBM for GPUs reusing a collection of LLVM target-agnostic implementations and built-ins alongside vendor implementations of most single and double-precision floating point math functions. Our approach allows selecting between individual implementations based on the GPU target as opposed to the current approach, which serves only the single third-party library implementation. Our extensive numerical analysis highlights the various implementations differences in performance and precision. Our solution allows users to choose the implementation that maximizes speed while meeting their specific precision requirements.

rawabstract:
With the advent of GPU computing, executing large program sections on accelerators has become increasingly important. Efforts are being made to support the C standard library, LIBC, on GPUs via LLVM machinery. Therefore, the C standard math library, LIBM, must be supported on GPUs. So far, LLVM frontends, such as Clang, have relied on GPU vendor implementations of LIBM functionality wrapped into (mostly) LIBM-compatible forwarding functions.\par We propose a novel LIBM for GPUs reusing a collection of LLVM target-agnostic implementations and built-ins alongside vendor implementations of most single and double-precision floating point math functions. Our approach allows selecting between individual implementations based on the GPU target as opposed to the current approach, which serves only the single third-party library implementation. Our extensive numerical analysis highlights the various implementations differences in performance and precision. Our solution allows users to choose the implementation that maximizes speed while meeting their specific precision requirements.

rawbooktitle:
Proceedings of the {SC 23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis}

entry:
@InProceedings{Rydahl:2023:PPA,
  author =       "Anton Rydahl and Joseph Huber and Ethan Luis Mcdonough
                 and Johannes Doerfert",
  booktitle =    "Proceedings of the {SC 23 Workshops of The
                 International Conference on High Performance Computing,
                 Network, Storage, and Analysis}",
  title =        "Precision and Performance Analysis of {C} Standard
                 Math Library Functions on {GPUs}",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  month =        nov,
  year =         "2023",
  DOI =          "https://doi.org/10.1145/3624062.3624166",
  bibdate =      "Fri Dec 8 12:56:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "With the advent of GPU computing, executing large
                 program sections on accelerators has become
                 increasingly important. Efforts are being made to
                 support the C standard library, LIBC, on GPUs via LLVM
                 machinery. Therefore, the C standard math library,
                 LIBM, must be supported on GPUs. So far, LLVM
                 frontends, such as Clang, have relied on GPU vendor
                 implementations of LIBM functionality wrapped into
                 (mostly) LIBM-compatible forwarding functions.\par

                 We propose a novel LIBM for GPUs reusing a collection
                 of LLVM target-agnostic implementations and built-ins
                 alongside vendor implementations of most single and
                 double-precision floating point math functions. Our
                 approach allows selecting between individual
                 implementations based on the GPU target as opposed to
                 the current approach, which serves only the single
                 third-party library implementation. Our extensive
                 numerical analysis highlights the various
                 implementations differences in performance and
                 precision. Our solution allows users to choose the
                 implementation that maximizes speed while meeting their
                 specific precision requirements.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Safieh:2023:EBR
author: Malek Safieh and Andreas Furch and Fabrizio De Santis
title: An Efficient Barrett Reduction Algorithm for Gaussian Integer Moduli
crossref: IEEE:2023:PIS
pages: 76--83
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00011
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Malek Safieh and Andreas Furch and Fabrizio {De Santis}
rawtitle: An Efficient {Barrett} Reduction Algorithm for {Gaussian} Integer Moduli
keywords:
ARITH-30; Barrett Reduction; Computational complexity; Computational efficiency; Costs; Digital arithmetic; Gaussian Integers; Modular Arithmetic; Modulo Reduction

entry:
@InProceedings{Safieh:2023:EBR,
  author =       "Malek Safieh and Andreas Furch and Fabrizio {De
                 Santis}",
  title =        "An Efficient {Barrett} Reduction Algorithm for
                 {Gaussian} Integer Moduli",
  crossref =     "IEEE:2023:PIS",
  pages =        "76--83",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00011",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-30; Barrett Reduction; Computational complexity;
                 Computational efficiency; Costs; Digital arithmetic;
                 Gaussian Integers; Modular Arithmetic; Modulo
                 Reduction",
}


bibtype: inproceedings
filename: fparith.bib
label: Sakellariou:2023:MFR
title: A multiplier-Free RNS-Based CNN accelerator exploiting bit-Level sparsity
crossref: IEEE:2023:PIS
pages: 101--101
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00037
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawtitle: A multiplier-Free {RNS}-Based {CNN} accelerator exploiting bit-Level sparsity
author:
Vasilis Sakellariou and Vassilis Paliouras and Ioannis Kouretas and Hani Saleh and Thanos Stouraitis

keywords:
Analytical models; ARITH-30; Benchmark testing; Digital arithmetic; Encoding; Energy efficiency; Throughput; Vectors

rawauthor:
Vasilis Sakellariou and Vassilis Paliouras and Ioannis Kouretas and Hani Saleh and Thanos Stouraitis

entry:
@InProceedings{Sakellariou:2023:MFR,
  author =       "Vasilis Sakellariou and Vassilis Paliouras and Ioannis
                 Kouretas and Hani Saleh and Thanos Stouraitis",
  title =        "A multiplier-Free {RNS}-Based {CNN} accelerator
                 exploiting bit-Level sparsity",
  crossref =     "IEEE:2023:PIS",
  pages =        "101--101",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00037",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Analytical models; ARITH-30; Benchmark testing;
                 Digital arithmetic; Encoding; Energy efficiency;
                 Throughput; Vectors",
}


bibtype: article
filename: fparith.bib
label: Schilling:2023:BSR
author: Jonathan Schilling and Jakob Svensson and Udo Hofel and Joachim Geiger and Henning Thomsen
title: Biot--Savart routines with minimal floating point error
journal: j-COMP-PHYS-COMM
volume: 287
pages: Article 108692
month: jun
monthnumber: 6
year: 2023
CODEN: CPHCBZ
DOI: https://doi.org/10.1016/j.cpc.2023.108692
ISSN: 0010-4655 (print), 1879-2944 (electronic) OR 00104655 (print), 18792944 (electronic)
ISSNL: 0010-4655 OR 00104655
bibdate: Fri Mar 17 07:49:53 MDT 2023
bibtimestamp: 2023.03.17 07:49:53 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0010465523000371
fjournal: Computer Physics Communications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00104655
rawauthor: Jonathan Schilling and Jakob Svensson and Udo H{\"o}fel and Joachim Geiger and Henning Thomsen
rawtitle: {Biot--Savart} routines with minimal floating point error
bibsource:
https://www.math.utah.edu/pub/tex/bib/compphyscomm2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Schilling:2023:BSR,
  author =       "Jonathan Schilling and Jakob Svensson and Udo
                 H{\"o}fel and Joachim Geiger and Henning Thomsen",
  title =        "{Biot--Savart} routines with minimal floating point
                 error",
  journal =      j-COMP-PHYS-COMM,
  volume =       "287",
  number =       "??",
  pages =        "Article 108692",
  month =        jun,
  year =         "2023",
  CODEN =        "CPHCBZ",
  DOI =          "https://doi.org/10.1016/j.cpc.2023.108692",
  ISSN =         "0010-4655 (print), 1879-2944 (electronic)",
  ISSN-L =       "0010-4655",
  bibdate =      "Fri Mar 17 07:49:53 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compphyscomm2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0010465523000371",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Physics Communications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00104655",
}


bibtype: inproceedings
filename: fparith.bib
label: Seo:2023:DPHa
author: Jihee Seo and Dae Hyun Kim
title: Dual-Purpose Hardware Algorithms and Architectures. Part 1: Floating-Point Division
crossref: IEEE:2023:PIS
pages: 24--31
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00013
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Jihee Seo and Dae Hyun Kim
rawtitle: Dual-Purpose Hardware Algorithms and Architectures. {Part 1}: Floating-Point Division
keywords:
ARITH-30; Computer architecture; Costs; Digital arithmetic; Divider; Energy consumption; Floating-Point Arithmetic; Hardware; Online Division; Simulation; Throughput

entry:
@InProceedings{Seo:2023:DPHa,
  author =       "Jihee Seo and Dae Hyun Kim",
  title =        "Dual-Purpose Hardware Algorithms and Architectures.
                 {Part 1}: Floating-Point Division",
  crossref =     "IEEE:2023:PIS",
  pages =        "24--31",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00013",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-30; Computer architecture; Costs; Digital
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                 Throughput",
}


bibtype: inproceedings
filename: fparith.bib
label: Seo:2023:DPHb
author: Jihee Seo and Dae Hyun Kim
title: Dual-Purpose Hardware Algorithms and Architectures. Part 2: Integer Division
crossref: IEEE:2023:PIS
pages: 1--8
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00014
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Jihee Seo and Dae Hyun Kim
rawtitle: Dual-Purpose Hardware Algorithms and Architectures. {Part 2}: Integer Division
keywords:
ARITH-30; Computer architecture; Costs; Digital arithmetic; Divider; Energy consumption; Hardware; Integer Arithmetic; Online Division; Simulation

entry:
@InProceedings{Seo:2023:DPHb,
  author =       "Jihee Seo and Dae Hyun Kim",
  title =        "Dual-Purpose Hardware Algorithms and Architectures.
                 {Part 2}: Integer Division",
  crossref =     "IEEE:2023:PIS",
  pages =        "1--8",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00014",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-30; Computer architecture; Costs; Digital
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                 Integer Arithmetic; Online Division; Simulation",
}


bibtype: inproceedings
filename: fparith.bib
label: Shah:2023:DPU
author: Nimish Shah and Wannes Meert and Marian Verhelst
booktitle: Efficient Execution of Irregular Dataflow Graphs
publisher: pub-SV
address: pub-SV:adr
pages: 69--88
year: 2023
DOI: https://doi.org/10.1007/978-3-031-33136-7_4
ISBN: 3-031-33136-2 OR 3031331362
ISBN13: 978-3-031-33136-7 OR 9783031331367
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Nimish Shah and Wannes Meert and Marian Verhelst
rawbooktitle: Efficient Execution of Irregular Dataflow Graphs
title:
DAG Processing Unit Version 1 (DPU): Efficient Execution of Irregular Workloads on a Multicore Processor

rawtitle:
{DAG} Processing Unit Version 1 {(DPU)}: Efficient Execution of Irregular Workloads on a Multicore Processor

entry:
@InProceedings{Shah:2023:DPU,
  author =       "Nimish Shah and Wannes Meert and Marian Verhelst",
  booktitle =    "Efficient Execution of Irregular Dataflow Graphs",
  title =        "{DAG} Processing Unit Version 1 {(DPU)}: Efficient
                 Execution of Irregular Workloads on a Multicore
                 Processor",
  publisher =    pub-SV,
  address =      pub-SV:adr,
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  DOI =          "https://doi.org/10.1007/978-3-031-33136-7_4",
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  acknowledgement = ack-nhfb,
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bibtype: book
filename: fparith.bib
label: Shah:2023:EEI
author: Nimish Shah and Wannes Meert and Marian Verhelst
publisher: pub-SV
address: pub-SV:adr
pages: 69--88
year: 2023
DOI: https://doi.org/10.1007/978-3-031-33136-7
ISBN: 3-031-33136-2 OR 3031331362
ISBN13: 978-3-031-33136-7 OR 9783031331367
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Nimish Shah and Wannes Meert and Marian Verhelst
title:
Efficient Execution of Irregular Dataflow Graphs: Hardware / Software Co-optimization for Probabilistic AI and Sparse Linear Algebra

rawtitle:
Efficient Execution of Irregular Dataflow Graphs: Hardware\slash Software Co-optimization for Probabilistic {AI} and Sparse Linear Algebra

entry:
@Book{Shah:2023:EEI,
  author =       "Nimish Shah and Wannes Meert and Marian Verhelst",
  title =        "Efficient Execution of Irregular Dataflow Graphs:
                 Hardware\slash Software Co-optimization for
                 Probabilistic {AI} and Sparse Linear Algebra",
  publisher =    pub-SV,
  address =      pub-SV:adr,
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  DOI =          "https://doi.org/10.1007/978-3-031-33136-7",
  ISBN =         "3-031-33136-2",
  ISBN-13 =      "978-3-031-33136-7",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Shah:2023:IWR
author: Nimish Shah and Wannes Meert and Marian Verhelst
booktitle: Efficient Execution of Irregular Dataflow Graphs
title: Irregular Workloads at Risk of Losing the Hardware Lottery
publisher: pub-SV
address: pub-SV:adr
pages: 1--21
year: 2023
DOI: https://doi.org/10.1007/978-3-031-33136-7_1
ISBN: 3-031-33136-2 OR 3031331362
ISBN13: 978-3-031-33136-7 OR 9783031331367
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Nimish Shah and Wannes Meert and Marian Verhelst
rawbooktitle: Efficient Execution of Irregular Dataflow Graphs
rawtitle: Irregular Workloads at Risk of Losing the Hardware Lottery
entry:
@InProceedings{Shah:2023:IWR,
  author =       "Nimish Shah and Wannes Meert and Marian Verhelst",
  booktitle =    "Efficient Execution of Irregular Dataflow Graphs",
  title =        "Irregular Workloads at Risk of Losing the Hardware
                 Lottery",
  publisher =    pub-SV,
  address =      pub-SV:adr,
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  DOI =          "https://doi.org/10.1007/978-3-031-33136-7_1",
  ISBN =         "3-031-33136-2",
  ISBN-13 =      "978-3-031-33136-7",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
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bibtype: inproceedings
filename: fparith.bib
label: Shah:2023:SDR
author: Nimish Shah and Wannes Meert and Marian Verhelst
booktitle: Efficient Execution of Irregular Dataflow Graphs
publisher: pub-SV
address: pub-SV:adr
pages: 23--41
year: 2023
DOI: https://doi.org/10.1007/978-3-031-33136-7_2
ISBN: 3-031-33136-2 OR 3031331362
ISBN13: 978-3-031-33136-7 OR 9783031331367
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Nimish Shah and Wannes Meert and Marian Verhelst
rawbooktitle: Efficient Execution of Irregular Dataflow Graphs
title:
Suitable Data Representation: A Study of Fixed-Point, Floating-Point, and PositTM Formats for Probabilistic AI

rawtitle:
Suitable Data Representation: A Study of Fixed-Point, Floating-Point, and {PositTM} Formats for Probabilistic {AI}

entry:
@InProceedings{Shah:2023:SDR,
  author =       "Nimish Shah and Wannes Meert and Marian Verhelst",
  booktitle =    "Efficient Execution of Irregular Dataflow Graphs",
  title =        "Suitable Data Representation: A Study of Fixed-Point,
                 Floating-Point, and {PositTM} Formats for Probabilistic
                 {AI}",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "23--41",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-33136-7_2",
  ISBN =         "3-031-33136-2",
  ISBN-13 =      "978-3-031-33136-7",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Shahbazi:2023:OHI
author: Karim Shahbazi and Seok-Bum Ko
title: An Optimized Hardware Implementation of Modular Multiplication of Binary Ring LWE
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 11
number: 3
pages: 817--821
month: jul
monthnumber: 7
year: 2023
DOI: https://doi.org/10.1109/TETC.2023.3280470
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Karim Shahbazi and Seok-Bum Ko
rawtitle: An Optimized Hardware Implementation of Modular Multiplication of Binary Ring {LWE}
entry:
@Article{Shahbazi:2023:OHI,
  author =       "Karim Shahbazi and Seok-Bum Ko",
  title =        "An Optimized Hardware Implementation of Modular
                 Multiplication of Binary Ring {LWE}",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "11",
  number =       "3",
  pages =        "817--821",
  month =        jul # "\slash " # sep,
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TETC.2023.3280470",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
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bibtype: article
filename: fparith.bib
label: Sharma:2023:CQE
title: CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism
journal: j-J-SYST-ARCH
volume: 135
pages: 102801
year: 2023
CODEN: JSARFB
DOI: https://doi.org/10.1016/j.sysarc.2022.102801
ISSN: 1383-7621 (print), 1873-6165 (electronic) OR 13837621 (print), 18736165 (electronic)
ISSNL: 1383-7621 OR 13837621
bibdate: Wed May 22 14:56:32 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2024.05.22 14:56:32 ???
URL: https://www.sciencedirect.com/science/article/pii/S1383762122002867
fjournal: Journal of Systems Architecture
keywords: Posit-arithmetic, RISC-V, Open-source hardware, Custom-instructions
acknowledgement: ack-nhfb
ajournal: J. Syst. Arch.
journalURL: https://www.sciencedirect.com/journal/journal-of-systems-architecture
rawtitle: {CLARINET}: A quire-enabled {RISC-V}-based framework for posit arithmetic empiricism
author:
Niraj N. Sharma and Riya Jain and Mohana Madhumita Pokkuluri and Sachin B. Patkar and Rainer Leupers and Rishiyur S. Nikhil and Farhad Merchant

rawauthor:
Niraj N. Sharma and Riya Jain and Mohana Madhumita Pokkuluri and Sachin B. Patkar and Rainer Leupers and Rishiyur S. Nikhil and Farhad Merchant

entry:
@Article{Sharma:2023:CQE,
  author =       "Niraj N. Sharma and Riya Jain and Mohana Madhumita
                 Pokkuluri and Sachin B. Patkar and Rainer Leupers and
                 Rishiyur S. Nikhil and Farhad Merchant",
  title =        "{CLARINET}: A quire-enabled {RISC-V}-based framework
                 for posit arithmetic empiricism",
  journal =      j-J-SYST-ARCH,
  volume =       "135",
  pages =        "102801",
  year =         "2023",
  CODEN =        "JSARFB",
  DOI =          "https://doi.org/10.1016/j.sysarc.2022.102801",
  ISSN =         "1383-7621 (print), 1873-6165 (electronic)",
  ISSN-L =       "1383-7621",
  bibdate =      "Wed May 22 14:56:32 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
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  URL =          "https://www.sciencedirect.com/science/article/pii/S1383762122002867",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Syst. Arch.",
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  journal-URL =  "https://www.sciencedirect.com/journal/journal-of-systems-architecture",
  keywords =     "Posit-arithmetic, RISC-V, Open-source hardware,
                 Custom-instructions",
}


bibtype: inproceedings
filename: fparith.bib
label: Shekhawat:2023:PPH
author: Diksha Shekhawat and Jugal Gandhi and M. Santosh and Jai Gopal Pandey
title: PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations
crossref: Gustafson:2023:NGA
pages: 88--100
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_6
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Diksha Shekhawat and Jugal Gandhi and M. Santosh and Jai Gopal Pandey
rawtitle: {PHAc}: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations
entry:
@InProceedings{Shekhawat:2023:PPH,
  author =       "Diksha Shekhawat and Jugal Gandhi and M. Santosh and
                 Jai Gopal Pandey",
  title =        "{PHAc}: Posit Hardware Accelerator for Efficient
                 Arithmetic Logic Operations",
  crossref =     "Gustafson:2023:NGA",
  pages =        "88--100",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_6",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Shen:2023:CCA
author: Shiyu Shen and Hao Yang and Yu Liu and Zhe Liu and Yunlei Zhao
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 7
pages: 1999--2010
month: jul
monthnumber: 7
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2022.3227874
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 1 10:59:22 2023
bibtimestamp: 2023.07.01 10:59:22 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
rawauthor: Shiyu Shen and Hao Yang and Yu Liu and Zhe Liu and Yunlei Zhao
title:
CARM: CUDA-Accelerated RNS Multiplication in Word-Wise Homomorphic Encryption Schemes for Internet of Things

journalURL:
https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib; http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12

rawtitle:
{CARM}: {CUDA-Accelerated RNS Multiplication} in Word-Wise Homomorphic Encryption Schemes for {Internet of Things}

entry:
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  author =       "Shiyu Shen and Hao Yang and Yu Liu and Zhe Liu and
                 Yunlei Zhao",
  title =        "{CARM}: {CUDA-Accelerated RNS Multiplication} in
                 Word-Wise Homomorphic Encryption Schemes for {Internet
                 of Things}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "7",
  pages =        "1999--2010",
  month =        jul,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2022.3227874",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 1 10:59:22 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
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  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
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bibtype: inproceedings
filename: fparith.bib
label: Silva:2023:TAB
author: Himeshi De Silva and Hongshi Tan and Nhut-Minh Ho and John L. Gustafson and Weng-Fai Wong
title: Towards a Better 16-Bit Number Representation for Training Neural Networks
crossref: Gustafson:2023:NGA
pages: 114--133
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_8
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
acknowledgement: ack-nhfb
rawauthor: Himeshi De Silva and Hongshi Tan and Nhut-Minh Ho and John L. Gustafson and Weng-Fai Wong
rawtitle: Towards a Better 16-Bit Number Representation for Training Neural Networks
entry:
@InProceedings{Silva:2023:TAB,
  author =       "Himeshi De Silva and Hongshi Tan and Nhut-Minh Ho and
                 John L. Gustafson and Weng-Fai Wong",
  title =        "Towards a Better 16-Bit Number Representation for
                 Training Neural Networks",
  crossref =     "Gustafson:2023:NGA",
  pages =        "114--133",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_8",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Sohn:2023:EFP
author: Jongwook Sohn and David K. Dean and Eric Quintana and Wing Shek Wong
title: Enhanced Floating-Point Multiply-Add with Full Denormal Support
crossref: IEEE:2023:PIS
pages: 143--150
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00015
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Jongwook Sohn and David K. Dean and Eric Quintana and Wing Shek Wong
rawtitle: Enhanced Floating-Point Multiply-Add with Full Denormal Support
keywords:
ARITH-30; Delays; Digital arithmetic; Encoding; floating-point arithmetic; floating-point denormal numbers; Floating-point multiply-add; high-speed computer arithmetic; Logic arrays; Next generation networking; Optimization

entry:
@InProceedings{Sohn:2023:EFP,
  author =       "Jongwook Sohn and David K. Dean and Eric Quintana and
                 Wing Shek Wong",
  title =        "Enhanced Floating-Point Multiply-Add with Full
                 Denormal Support",
  crossref =     "IEEE:2023:PIS",
  pages =        "143--150",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00015",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-30; Delays; Digital arithmetic; Encoding;
                 floating-point arithmetic; floating-point denormal
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                 computer arithmetic; Logic arrays; Next generation
                 networking; Optimization",
}


bibtype: misc
filename: fparith.bib
label: Sukop:2023:HDB
author: Juraj Sukop and Niels Moller
title: On HGCD-D bounds
type: Report
pages: 143--150
day: 7
month: feb
monthnumber: 2
year: 2023
bibdate: Thu Feb 09 11:15:45 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.02.09 11:15:45 ???
URL: https://hal.science/hal-03976898
acknowledgement: ack-nhfb
rawauthor: Juraj Sukop and Niels M{\"o}ller
rawtitle: On {HGCD-D} bounds
abstract:
An improved bound for one of the founding relations of HGCD-D algorithm is presented. This allows to put a lower limit on the iteration count of the first sdiv loop, to impose a particular structure on the accumulated quotients and to bound the size of the largest matrix element. The matrix product M.M' is proved to have its upper and lower size bound differ by at most two bits

rawabstract:
An improved bound for one of the founding relations of HGCD-D algorithm is presented. This allows to put a lower limit on the iteration count of the first sdiv loop, to impose a particular structure on the accumulated quotients and to bound the size of the largest matrix element. The matrix product M.M' is proved to have its upper and lower size bound differ by at most two bits

entry:
@Misc{Sukop:2023:HDB,
  author =       "Juraj Sukop and Niels M{\"o}ller",
  title =        "On {HGCD-D} bounds",
  type =         "Report",
  day =          "7",
  month =        feb,
  year =         "2023",
  bibdate =      "Thu Feb 09 11:15:45 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.science/hal-03976898",
  abstract =     "An improved bound for one of the founding relations of
                 HGCD-D algorithm is presented. This allows to put a
                 lower limit on the iteration count of the first sdiv
                 loop, to impose a particular structure on the
                 accumulated quotients and to bound the size of the
                 largest matrix element. The matrix product M.M' is
                 proved to have its upper and lower size bound differ by
                 at most two bits",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Talpes:2023:MDT
title: The Microarchitecture of DOJO, Tesla's Exa-Scale Computer
journal: j-IEEE-MICRO
volume: 43
number: 3
pages: 31--39
month: may
monthnumber: 5
year: 2023
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/MM.2023.3258906
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Thu May 18 07:38:12 2023
bibtimestamp: 2023.05.18 07:38:12 ???
fjournal: IEEE Micro
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40
rawtitle: The Microarchitecture of {DOJO}, {Tesla}'s Exa-Scale Computer
author:
Emil Talpes and Debjit Das Sarma and Doug Williams and Sahil Arora and Thomas Kunjan and Benjamin Floering and Ankit Jalote and Christopher Hsiong and Chandrasekhar Poorna and Vaidehi Samant and John Sicilia and Anantha Kumar Nivarti and Raghuvir Ramachandran and Tim Fischer and Ben Herzberg and Bill McGee and Ganesh Venkataramanan and Pete Banon

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/hot-chips.bib; https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib

remark:
DOJO is based on RISC-V64 with instruction set extensions. Its arithmetic supports 8-, 16-, 32-, and 64-bit integers, and IEEE 754 FP32 (1/8/23), plus FP16 (1/5/10), BFP16 (1/8/7), CFP8 (1/4/3), CFP8 (1/5/2), and CFP16 (1/5/10) floating-point formats. The latter is unusual having an external register that records the exponent bias (0, 31, or 63), so that it supports three different ranges of numbers. There is no support for FP64 or longer formats. There is support for stochastic rounding.

rawauthor:
Emil Talpes and Debjit Das Sarma and Doug Williams and Sahil Arora and Thomas Kunjan and Benjamin Floering and Ankit Jalote and Christopher Hsiong and Chandrasekhar Poorna and Vaidehi Samant and John Sicilia and Anantha Kumar Nivarti and Raghuvir Ramachandran and Tim Fischer and Ben Herzberg and Bill McGee and Ganesh Venkataramanan and Pete Banon

entry:
@Article{Talpes:2023:MDT,
  author =       "Emil Talpes and Debjit Das Sarma and Doug Williams and
                 Sahil Arora and Thomas Kunjan and Benjamin Floering and
                 Ankit Jalote and Christopher Hsiong and Chandrasekhar
                 Poorna and Vaidehi Samant and John Sicilia and Anantha
                 Kumar Nivarti and Raghuvir Ramachandran and Tim Fischer
                 and Ben Herzberg and Bill McGee and Ganesh
                 Venkataramanan and Pete Banon",
  title =        "The Microarchitecture of {DOJO}, {Tesla}'s Exa-Scale
                 Computer",
  journal =      j-IEEE-MICRO,
  volume =       "43",
  number =       "3",
  pages =        "31--39",
  month =        may # "\slash " # jun,
  year =         "2023",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2023.3258906",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu May 18 07:38:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
  remark =       "DOJO is based on RISC-V64 with instruction set
                 extensions. Its arithmetic supports 8-, 16-, 32-, and
                 64-bit integers, and IEEE 754 FP32 (1/8/23), plus FP16
                 (1/5/10), BFP16 (1/8/7), CFP8 (1/4/3), CFP8 (1/5/2),
                 and CFP16 (1/5/10) floating-point formats. The latter
                 is unusual having an external register that records the
                 exponent bias (0, 31, or 63), so that it supports three
                 different ranges of numbers. There is no support for
                 FP64 or longer formats. There is support for stochastic
                 rounding.",
}


bibtype: inproceedings
filename: fparith.bib
label: Tompazi:2023:ABT
author: Styliani Tompazi and Georgios Karakonstantis
title: AI-based Timing Error Modelling: a Case Study on a Pipelined Floating-point Core
crossref: IEEE:2023:PIS
pages: 110--110
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00035
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Styliani Tompazi and Georgios Karakonstantis
rawtitle: {AI}-based Timing Error Modelling: a Case Study on a Pipelined Floating-point Core
keywords:
ARITH-30; Computational modeling; Digital arithmetic; Machine learning; Nanoscale devices; Timing; Training

entry:
@InProceedings{Tompazi:2023:ABT,
  author =       "Styliani Tompazi and Georgios Karakonstantis",
  title =        "{AI}-based Timing Error Modelling: a Case Study on a
                 Pipelined Floating-point Core",
  crossref =     "IEEE:2023:PIS",
  pages =        "110--110",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00035",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-30; Computational modeling; Digital arithmetic;
                 Machine learning; Nanoscale devices; Timing; Training",
}


bibtype: article
filename: fparith.bib
label: Towhidy:2023:DIA
author: Ahmad Towhidy and Reza Omidi and Karim Mohammadi
title: On the Design of Iterative Approximate Floating-Point Multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 6
pages: 1623--1635
month: jun
monthnumber: 6
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2022.3216465
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed May 17 10:34:15 2023
bibtimestamp: 2023.05.17 10:34:15 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Ahmad Towhidy and Reza Omidi and Karim Mohammadi
rawtitle: On the Design of Iterative Approximate Floating-Point Multipliers
abstract:
Approximate multipliers provide power and area-saving for error-resilient applications. In this paper, we first propose two approximate floating-point multipliers based on two-dimensional pseudo-Booth encoding: floating-point pseudo-Booth (PB), and floating-point iterative pseudo-Booth (IPB). The accuracy of proposed multipliers can be tuned by three parameters: iteration, encoder's radix (R), and word length after truncation (W). Next, we developed the conventional iterative multipliers with a simplified steering circuit for their correction part to eliminate the power consumption of multipliers. The proposed iterative multipliers are compared with conventional iterative integer multipliers implemented by a simplified steering circuit for the floating-point area. The results reveal that the proposed PB-R4-W4 and IPB-R16-W19, compared to the exact floating-point multiplier, provide up to 98.9% and 67.5% reductions in power consumption, respectively, in TSMC 180nm CMOS technology. Also, their MRED values are, respectively, 2.9% and ($ 7.4 times 10 -4$)%. Finally, we evaluated the functionality of the proposed multipliers for real-life applications, including a hyper-plane classifier and two image processing applications of smoothing and sharpening.

rawabstract:
Approximate multipliers provide power and area-saving for error-resilient applications. In this paper, we first propose two approximate floating-point multipliers based on two-dimensional pseudo-Booth encoding: floating-point pseudo-Booth (PB), and floating-point iterative pseudo-Booth (IPB). The accuracy of proposed multipliers can be tuned by three parameters: iteration, encoder's radix (R), and word length after truncation (W). Next, we developed the conventional iterative multipliers with a simplified steering circuit for their correction part to eliminate the power consumption of multipliers. The proposed iterative multipliers are compared with conventional iterative integer multipliers implemented by a simplified steering circuit for the floating-point area. The results reveal that the proposed PB-R4-W4 and IPB-R16-W19, compared to the exact floating-point multiplier, provide up to 98.9\% and 67.5\% reductions in power consumption, respectively, in TSMC 180nm CMOS technology. Also, their MRED values are, respectively, 2.9\% and ($ 7.4 \times 10 {-4}$)\%. Finally, we evaluated the functionality of the proposed multipliers for real-life applications, including a hyper-plane classifier and two image processing applications of smoothing and sharpening.

entry:
@Article{Towhidy:2023:DIA,
  author =       "Ahmad Towhidy and Reza Omidi and Karim Mohammadi",
  title =        "On the Design of Iterative Approximate Floating-Point
                 Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "6",
  pages =        "1623--1635",
  month =        jun,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2022.3216465",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed May 17 10:34:15 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  abstract =     "Approximate multipliers provide power and area-saving
                 for error-resilient applications. In this paper, we
                 first propose two approximate floating-point
                 multipliers based on two-dimensional pseudo-Booth
                 encoding: floating-point pseudo-Booth (PB), and
                 floating-point iterative pseudo-Booth (IPB). The
                 accuracy of proposed multipliers can be tuned by three
                 parameters: iteration, encoder's radix (R), and word
                 length after truncation (W). Next, we developed the
                 conventional iterative multipliers with a simplified
                 steering circuit for their correction part to eliminate
                 the power consumption of multipliers. The proposed
                 iterative multipliers are compared with conventional
                 iterative integer multipliers implemented by a
                 simplified steering circuit for the floating-point
                 area. The results reveal that the proposed PB-R4-W4 and
                 IPB-R16-W19, compared to the exact floating-point
                 multiplier, provide up to 98.9\% and 67.5\% reductions
                 in power consumption, respectively, in TSMC 180nm CMOS
                 technology. Also, their MRED values are, respectively,
                 2.9\% and ($ 7.4 \times 10 {-4}$)\%. Finally, we
                 evaluated the functionality of the proposed multipliers
                 for real-life applications, including a hyper-plane
                 classifier and two image processing applications of
                 smoothing and sharpening.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Ullah:2023:DRE
author: Salim Ullah and Siva Satyendra Sahoo and Akash Kumar
booktitle: Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing
publisher: pub-SV
address: pub-SV:adr
pages: 89--119
month: oct
monthnumber: 10
year: 2023
DOI: https://doi.org/10.1007/978-3-031-19568-6_4
ISBN: 3-031-19568-X OR 303119568X
ISBN13: 978-3-031-19568-6 OR 9783031195686
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Salim Ullah and Siva Satyendra Sahoo and Akash Kumar
rawbooktitle: Embedded Machine Learning for Cyber-Physical, {IoT}, and Edge Computing
title:
Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations

rawtitle:
Designing Resource-Efficient Hardware Arithmetic for {FPGA}-Based Accelerators Leveraging Approximations and Mixed Quantizations

entry:
@InProceedings{Ullah:2023:DRE,
  author =       "Salim Ullah and Siva Satyendra Sahoo and Akash Kumar",
  booktitle =    "Embedded Machine Learning for Cyber-Physical, {IoT},
                 and Edge Computing",
  title =        "Designing Resource-Efficient Hardware Arithmetic for
                 {FPGA}-Based Accelerators Leveraging Approximations and
                 Mixed Quantizations",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "89--119",
  month =        oct,
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-19568-6_4",
  ISBN =         "3-031-19568-X",
  ISBN-13 =      "978-3-031-19568-6",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Vollmer:2023:UHA
author: Morgane Vollmer and Karim Bigou and Arnaud Tisserand
title: Using Hierarchical Approach to Speed-up RNS Base Extensions in Homomorphic Encryption Context
crossref: IEEE:2023:PIS
pages: 84--87
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00030
bibdate: Wed May 8 09:17:31 2024
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Morgane Vollmer and Karim Bigou and Arnaud Tisserand
rawtitle: Using Hierarchical Approach to Speed-up {RNS} Base Extensions in Homomorphic Encryption Context
keywords:
ARITH-30; base extension; Costs; Digital arithmetic; homomorphic encryption; Homomorphic encryption; Multicore processing; Parallel processing; residue number system; Software; Software algorithms

entry:
@InProceedings{Vollmer:2023:UHA,
  author =       "Morgane Vollmer and Karim Bigou and Arnaud Tisserand",
  title =        "Using Hierarchical Approach to Speed-up {RNS} Base
                 Extensions in Homomorphic Encryption Context",
  crossref =     "IEEE:2023:PIS",
  pages =        "84--87",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00030",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-30; base extension; Costs; Digital arithmetic;
                 homomorphic encryption; Homomorphic encryption;
                 Multicore processing; Parallel processing; residue
                 number system; Software; Software algorithms",
}


bibtype: manual
filename: fparith.bib
label: Whitehead:2023:FPI
author: Nathan Whitehead and Alex Fit-florea
title: Floating Point and IEEE 754 Compliance for NVIDIA GPUs
organization: NVIDIA
pages: 28
day: 24
month: aug
monthnumber: 8
year: 2023
bibdate: Mon Sep 11 07:26:37 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 07:26:37 ???
acknowledgement: ack-nhfb
rawauthor: Nathan Whitehead and Alex Fit-florea
rawtitle: Floating Point and {IEEE 754} Compliance for {NVIDIA GPUs}
URL:
https://docs.nvidia.com/cuda/floating-point/; https://docs.nvidia.com/cuda/pdf/Floating_Point_on_NVIDIA_GPU.pdf

abstract:
A number of issues related to floating point accuracy and compliance are a frequent source of confusion on both CPUs and GPUs. The purpose of this white paper is to discuss the most common issues related to NVIDIA GPUs and to supplement the documentation in the CUDA C++ Programming Guide

TOC:
1 Floating Point / 3 1.1 Formats / 3 1.2 Operations and Accuracy / 4 1.3 The Fused Multiply-Add (FMA) / 5 2 Dot Product: An Accuracy Example / 7 2.1 Example Algorithms / 7 2.2 Comparison / 8 3 CUDA and Floating Point / 9 3.1 Compute Capability 2.0 and Above / 9 3.2 Rounding Modes / 9 3.3 Controlling Fused Multiply-add / 10 3.4 Compiler Flags / 11 3.5 Differences from x86 / 11 4 Considerations for a Heterogeneous World / 13 4.1 Mathematical Function Accuracy / 13 4.2 x87 and SSE / 14 4.3 Core Counts / 14 4.4 Verifying GPU Results / 14 5 Concrete Recommendations / 17 6 Acknowledgements / 19 7 References / 21 8 Notices / 23 8.1 Notice / 23 8.2 OpenCL / 24 8.3 Trademarks / 24

rawabstract:
A number of issues related to floating point accuracy and compliance are a frequent source of confusion on both CPUs and GPUs. The purpose of this white paper is to discuss the most common issues related to NVIDIA GPUs and to supplement the documentation in the CUDA C++ Programming Guide

rawTOC:
1 Floating Point / 3 \\ 1.1 Formats / 3 \\ 1.2 Operations and Accuracy / 4 \\ 1.3 The Fused Multiply-Add (FMA) / 5 \\ 2 Dot Product: An Accuracy Example / 7 \\ 2.1 Example Algorithms / 7 \\ 2.2 Comparison / 8 \\ 3 CUDA and Floating Point / 9 \\ 3.1 Compute Capability 2.0 and Above / 9 \\ 3.2 Rounding Modes / 9 \\ 3.3 Controlling Fused Multiply-add / 10 \\ 3.4 Compiler Flags / 11 \\ 3.5 Differences from x86 / 11 \\ 4 Considerations for a Heterogeneous World / 13 \\ 4.1 Mathematical Function Accuracy / 13 \\ 4.2 x87 and SSE / 14 \\ 4.3 Core Counts / 14 \\ 4.4 Verifying GPU Results / 14 \\ 5 Concrete Recommendations / 17 \\ 6 Acknowledgements / 19 \\ 7 References / 21 \\ 8 Notices / 23 \\ 8.1 Notice / 23 \\ 8.2 OpenCL / 24 \\ 8.3 Trademarks / 24

entry:
@Manual{Whitehead:2023:FPI,
  author =       "Nathan Whitehead and Alex Fit-florea",
  title =        "Floating Point and {IEEE 754} Compliance for {NVIDIA
                 GPUs}",
  organization = "NVIDIA",
  address =      "????",
  pages =        "28",
  day =          "24",
  month =        aug,
  year =         "2023",
  bibdate =      "Mon Sep 11 07:26:37 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://docs.nvidia.com/cuda/floating-point/;
                 https://docs.nvidia.com/cuda/pdf/Floating_Point_on_NVIDIA_GPU.pdf",
  abstract =     "A number of issues related to floating point accuracy
                 and compliance are a frequent source of confusion on
                 both CPUs and GPUs. The purpose of this white paper is
                 to discuss the most common issues related to NVIDIA
                 GPUs and to supplement the documentation in the CUDA
                 C++ Programming Guide",
  acknowledgement = ack-nhfb,
  tableofcontents = "1 Floating Point / 3 \\
                 1.1 Formats / 3 \\
                 1.2 Operations and Accuracy / 4 \\
                 1.3 The Fused Multiply-Add (FMA) / 5 \\
                 2 Dot Product: An Accuracy Example / 7 \\
                 2.1 Example Algorithms / 7 \\
                 2.2 Comparison / 8 \\
                 3 CUDA and Floating Point / 9 \\
                 3.1 Compute Capability 2.0 and Above / 9 \\
                 3.2 Rounding Modes / 9 \\
                 3.3 Controlling Fused Multiply-add / 10 \\
                 3.4 Compiler Flags / 11 \\
                 3.5 Differences from x86 / 11 \\
                 4 Considerations for a Heterogeneous World / 13 \\
                 4.1 Mathematical Function Accuracy / 13 \\
                 4.2 x87 and SSE / 14 \\
                 4.3 Core Counts / 14 \\
                 4.4 Verifying GPU Results / 14 \\
                 5 Concrete Recommendations / 17 \\
                 6 Acknowledgements / 19 \\
                 7 References / 21 \\
                 8 Notices / 23 \\
                 8.1 Notice / 23 \\
                 8.2 OpenCL / 24 \\
                 8.3 Trademarks / 24",
}


bibtype: book
filename: fparith.bib
label: Wilkinson:2023:REA
author: J. H. (James Hardy) Wilkinson
title: Rounding Errors in Algebraic Processes
volume: 89
publisher: pub-SIAM
address: pub-SIAM:adr
pages: xiii + 161
year: 2023
ISBN: 1-61197-751-7 OR 1611977517
ISBN13: 978-1-61197-751-6 OR 9781611977516
LCCN: QA275 .W64 2023
bibdate: Wed Aug 7 17:00:33 MDT 2024
bibtimestamp: 2024.08.07 17:00:33 MDT
note: New foreword by N. J. Higham.
series: Classics in applied mathematics
subject: Roundoff errors; Erreurs d'arrondi; Roundoff errors
TOC: The fundamental arithmetic operations Computations involving polynomials Matrix computations
acknowledgement: ack-nhfb
authordates: James H. Wilkinson (27 September 1919--5 October 1986)
rawauthor: J. H. (James Hardy) Wilkinson
rawnote: New foreword by N. J. Higham.
rawtitle: Rounding Errors in Algebraic Processes
rawTOC: The fundamental arithmetic operations \\ Computations involving polynomials \\ Matrix computations
bibsource:
fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/bibnet/authors/w/wilkinson-james-hardy.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
booktitle Rounding Errors in Algebraic Processes was the first book to give systematic analyses of the effects of rounding errors on a variety of key computations involving polynomials and matrices. A detailed analysis is given of the rounding errors made in the elementary arithmetic operations and inner products, for both floating-point arithmetic and fixed-point arithmetic. The results are then applied in the error analyses of a variety of computations involving polynomials as well as the solution of linear systems, matrix inversion, and eigenvalue computations. The conditioning of these problems is investigated. The aim was to provide a unified method of treatment, and emphasis is placed on the underlying concepts.

remark:
``ldots a republication originally published by Her Majesty's Stationery Office under British Crown copyright in 1963''-- title page verso.

rawabstract:
\booktitle{Rounding Errors in Algebraic Processes} was the first book to give systematic analyses of the effects of rounding errors on a variety of key computations involving polynomials and matrices. A detailed analysis is given of the rounding errors made in the elementary arithmetic operations and inner products, for both floating-point arithmetic and fixed-point arithmetic. The results are then applied in the error analyses of a variety of computations involving polynomials as well as the solution of linear systems, matrix inversion, and eigenvalue computations. The conditioning of these problems is investigated. The aim was to provide a unified method of treatment, and emphasis is placed on the underlying concepts.

entry:
@Book{Wilkinson:2023:REA,
  author =       "J. H. (James Hardy) Wilkinson",
  title =        "Rounding Errors in Algebraic Processes",
  volume =       "89",
  publisher =    pub-SIAM,
  address =      pub-SIAM:adr,
  pages =        "xiii + 161",
  year =         "2023",
  ISBN =         "1-61197-751-7",
  ISBN-13 =      "978-1-61197-751-6",
  LCCN =         "QA275 .W64 2023",
  bibdate =      "Wed Aug 7 17:00:33 MDT 2024",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/bibnet/authors/w/wilkinson-james-hardy.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "New foreword by N. J. Higham.",
  series =       "Classics in applied mathematics",
  abstract =     "\booktitle{Rounding Errors in Algebraic Processes} was
                 the first book to give systematic analyses of the
                 effects of rounding errors on a variety of key
                 computations involving polynomials and matrices. A
                 detailed analysis is given of the rounding errors made
                 in the elementary arithmetic operations and inner
                 products, for both floating-point arithmetic and
                 fixed-point arithmetic. The results are then applied in
                 the error analyses of a variety of computations
                 involving polynomials as well as the solution of linear
                 systems, matrix inversion, and eigenvalue computations.
                 The conditioning of these problems is investigated. The
                 aim was to provide a unified method of treatment, and
                 emphasis is placed on the underlying concepts.",
  acknowledgement = ack-nhfb,
  author-dates = "James H. Wilkinson (27 September 1919--5 October
                 1986)",
  remark =       "``\ldots{}a republication originally published by Her
                 Majesty's Stationery Office under British Crown
                 copyright in 1963''-- title page verso.",
  subject =      "Roundoff errors; Erreurs d'arrondi; Roundoff errors",
  tableofcontents = "The fundamental arithmetic operations \\
                 Computations involving polynomials \\
                 Matrix computations",
}


bibtype: article
filename: fparith.bib
label: Wong:2023:KNS
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 7
pages: 1830--1842
month: jul
monthnumber: 7
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2023.3238129
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 1 10:59:22 2023
bibtimestamp: 2023.07.01 10:59:22 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
author:
Zheng-Yan Wong and Denis C.-K. Wong and Wai-Kong Lee and Kai-Ming Mok and Wun-She Yap and Ayesha Khalid

title:
KaratSaber: New Speed Records for Saber Polynomial Multiplication Using Efficient Karatsuba FPGA Architecture

bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib

rawauthor:
Zheng-Yan Wong and Denis C.-K. Wong and Wai-Kong Lee and Kai-Ming Mok and Wun-She Yap and Ayesha Khalid

rawtitle:
{KaratSaber}: New Speed Records for {Saber} Polynomial Multiplication Using Efficient {Karatsuba} {FPGA} Architecture

entry:
@Article{Wong:2023:KNS,
  author =       "Zheng-Yan Wong and Denis C.-K. Wong and Wai-Kong Lee
                 and Kai-Ming Mok and Wun-She Yap and Ayesha Khalid",
  title =        "{KaratSaber}: New Speed Records for {Saber} Polynomial
                 Multiplication Using Efficient {Karatsuba} {FPGA}
                 Architecture",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "7",
  pages =        "1830--1842",
  month =        jul,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3238129",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 1 10:59:22 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Yang:2023:ATF
author: Chun-Chieh Yang and Yi-Ru Chen and Hui-Hsin Liao and Yuan-Ming Chang and Jenq-Kuen Lee
title: Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension
journal: j-TODAES
volume: 28
number: 3
pages: 33:1--33:??
month: may
monthnumber: 5
year: 2023
CODEN: ATASFO
DOI: https://doi.org/10.1145/3569939
ISSN: 1084-4309 (print), 1557-7309 (electronic) OR 10844309 (print), 15577309 (electronic)
ISSNL: 1084-4309 OR 10844309
bibdate: Wed May 17 08:06:20 MDT 2023
bibtimestamp: 2023.05.17 08:06:20 MDT
URL: https://dl.acm.org/doi/10.1145/3569939
fjournal: ACM Transactions on Design Automation of Electronic Systems
acknowledgement: ack-nhfb
articleno: 33
journalURL: https://dl.acm.org/loi/todaes
rawauthor: Chun-Chieh Yang and Yi-Ru Chen and Hui-Hsin Liao and Yuan-Ming Chang and Jenq-Kuen Lee
rawtitle: Auto-tuning Fixed-point Precision with {TVM} on {RISC-V} Packed {SIMD} Extension
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib; https://www.math.utah.edu/pub/tex/bib/todaes.bib

abstract:
Today, as deep learning (DL) is applied more often in daily life, dedicated processors such as CPUs and GPUs have become very important for accelerating model executions. With the growth of technology, people are becoming accustomed to using edge devices, such as mobile phones, smart watches, and VR devices in their daily lives. A variety of technologies using DL are gradually being applied to these edge devices. However, there is a large number of computations in DL. It faces a challenging problem how to provide solutions in the edge devices. In this article, the proposed method enables a flow with the RISC-V Packed extension (P extension) in TVM. TVM, an open deep learning compiler for neural network models, is growing as a key infrastructure for DL computing. RISC-V is an open instruction set architecture (ISA) with customized and flexible features. The Packed-SIMD extension is a RISC-V extension that enables subword single-instruction multiple-data (SIMD) computations in RISC-V architectures to support fallback engines in AI computing. In the proposed flow, a fixed-point type that is supported by an integer of 16-bit type and saturation instructions is added to replace the original 32-bit float type. In addition, an auto-tuning method is proposed to use a uniform selector mechanism (USM) to find the binary point position for fixed-point type use. The tensorization feature of TVM can be used to optimize specific hardware such as subword SIMD instructions with RISC-V P extension. With our experiment on the Spike simulator, the proposed method with the USM can improve performance by approximately 2.54 to 6.15$ times $ in terms of instruction counts with little accuracy loss.

rawabstract:
Today, as deep learning (DL) is applied more often in daily life, dedicated processors such as CPUs and GPUs have become very important for accelerating model executions. With the growth of technology, people are becoming accustomed to using edge devices, such as mobile phones, smart watches, and VR devices in their daily lives. A variety of technologies using DL are gradually being applied to these edge devices. However, there is a large number of computations in DL. It faces a challenging problem how to provide solutions in the edge devices. In this article, the proposed method enables a flow with the RISC-V Packed extension (P extension) in TVM. TVM, an open deep learning compiler for neural network models, is growing as a key infrastructure for DL computing. RISC-V is an open instruction set architecture (ISA) with customized and flexible features. The Packed-SIMD extension is a RISC-V extension that enables subword single-instruction multiple-data (SIMD) computations in RISC-V architectures to support fallback engines in AI computing. In the proposed flow, a fixed-point type that is supported by an integer of 16-bit type and saturation instructions is added to replace the original 32-bit float type. In addition, an auto-tuning method is proposed to use a uniform selector mechanism (USM) to find the binary point position for fixed-point type use. The tensorization feature of TVM can be used to optimize specific hardware such as subword SIMD instructions with RISC-V P extension. With our experiment on the Spike simulator, the proposed method with the USM can improve performance by approximately 2.54 to 6.15$ \times $ in terms of instruction counts with little accuracy loss.

entry:
@Article{Yang:2023:ATF,
  author =       "Chun-Chieh Yang and Yi-Ru Chen and Hui-Hsin Liao and
                 Yuan-Ming Chang and Jenq-Kuen Lee",
  title =        "Auto-tuning Fixed-point Precision with {TVM} on
                 {RISC-V} Packed {SIMD} Extension",
  journal =      j-TODAES,
  volume =       "28",
  number =       "3",
  pages =        "33:1--33:??",
  month =        may,
  year =         "2023",
  CODEN =        "ATASFO",
  DOI =          "https://doi.org/10.1145/3569939",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Wed May 17 08:06:20 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/todaes.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3569939",
  abstract =     "Today, as deep learning (DL) is applied more often in
                 daily life, dedicated processors such as CPUs and GPUs
                 have become very important for accelerating model
                 executions. With the growth of technology, people are
                 becoming accustomed to using edge devices, such as
                 mobile phones, smart watches, and VR devices in their
                 daily lives. A variety of technologies using DL are
                 gradually being applied to these edge devices. However,
                 there is a large number of computations in DL. It faces
                 a challenging problem how to provide solutions in the
                 edge devices. In this article, the proposed method
                 enables a flow with the RISC-V Packed extension (P
                 extension) in TVM. TVM, an open deep learning compiler
                 for neural network models, is growing as a key
                 infrastructure for DL computing. RISC-V is an open
                 instruction set architecture (ISA) with customized and
                 flexible features. The Packed-SIMD extension is a
                 RISC-V extension that enables subword
                 single-instruction multiple-data (SIMD) computations in
                 RISC-V architectures to support fallback engines in AI
                 computing. In the proposed flow, a fixed-point type
                 that is supported by an integer of 16-bit type and
                 saturation instructions is added to replace the
                 original 32-bit float type. In addition, an auto-tuning
                 method is proposed to use a uniform selector mechanism
                 (USM) to find the binary point position for fixed-point
                 type use. The tensorization feature of TVM can be used
                 to optimize specific hardware such as subword SIMD
                 instructions with RISC-V P extension. With our
                 experiment on the Spike simulator, the proposed method
                 with the USM can improve performance by approximately
                 2.54 to 6.15$ \times $ in terms of instruction counts
                 with little accuracy loss.",
  acknowledgement = ack-nhfb,
  articleno =    "33",
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems",
  journal-URL =  "https://dl.acm.org/loi/todaes",
}


bibtype: article
filename: fparith.bib
label: Zhang:2023:EAP
author: Hao Zhang and Seok-Bum Ko
title: Efficient Approximate Posit Multipliers for Deep Learning Computation
journal: j-IEEE-J-EMERG-SEL-TOP-CIRCUITS-SYST
volume: 13
number: 1
pages: 201--211
year: 2023
DOI: https://doi.org/10.1109/JETCAS.2022.3231642
ISSN: 2156-3357 (print), 2156-3365 (electronic) OR 21563357 (print), 21563365 (electronic)
ISSNL: 2156-3357 OR 21563357
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
fjournal: IEEE Journal on Emerging and Selected Topics in Circuits and Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5503868
rawauthor: Hao Zhang and Seok-Bum Ko
rawtitle: Efficient Approximate Posit Multipliers for Deep Learning Computation
entry:
@Article{Zhang:2023:EAP,
  author =       "Hao Zhang and Seok-Bum Ko",
  title =        "Efficient Approximate Posit Multipliers for Deep
                 Learning Computation",
  journal =      j-IEEE-J-EMERG-SEL-TOP-CIRCUITS-SYST,
  volume =       "13",
  number =       "1",
  pages =        "201--211",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/JETCAS.2022.3231642",
  ISSN =         "2156-3357 (print), 2156-3365 (electronic)",
  ISSN-L =       "2156-3357",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal on Emerging and Selected Topics in
                 Circuits and Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5503868",
}


bibtype: article
filename: fparith.bib
label: Zlatopolski:2023:PAV
author: Dmitry Zlatopolski
title: ``Perfect Arithmetic'' by Vaclav Josef Pelikan
journal: j-HIST-MATH
volume: 62
pages: 40--50
month: feb
monthnumber: 2
year: 2023
CODEN: HIMADS
DOI: https://doi.org/10.1016/j.hm.2022.09.002
ISSN: 0315-0860 (print), 1090-249X (electronic) OR 03150860 (print), 1090249X (electronic)
ISSNL: 0315-0860 OR 03150860
bibdate: Wed Mar 15 09:40:56 MDT 2023
bibtimestamp: 2023.03.15 09:40:56 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0315086022000659
fjournal: Historia Mathematica
keywords: base conversion; binary arithmetic
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03150860
rawauthor: Dmitry Zlatopolski
rawtitle: {``Perfect Arithmetic'' by Vaclav Josef Pelikan}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/histmath.bib

abstract:
The present article describes for the first time the book of Vaclav Josef Pelikan titled booktitle Arithmeticus Perfectus Qui tria numerare nescit. Seu Arithmetica dualis, In qua Numerando non proceditur, nisi ad duo, & tamen omnes quaestiones Arithmeticae negotio facili enodari possunt, published in Prague in 1712. The book is written in Latin on 86 pages and consists of a dedication, a message to the reader and four chapters. Operations in the binary system, including the extraction of square and cube roots, methods of converting numbers from the decimal system to the binary system and vice versa, etc., are given. In general, we may say that the book by Vaclav Josef Pelikan is the first fully fledged and methodologically sound textbook of arithmetic using the binary number system as well as containing original methods of solution.

rawabstract:
The present article describes for the first time the book of Vaclav Josef Pelikan titled \booktitle{Arithmeticus Perfectus Qui tria numerare nescit. Seu Arithmetica dualis, In qua Numerando non proceditur, nisi ad duo, \& tamen omnes quaestiones Arithmeticae negotio facili enodari possunt}, published in Prague in 1712. The book is written in Latin on 86 pages and consists of a dedication, a message to the reader and four chapters. Operations in the binary system, including the extraction of square and cube roots, methods of converting numbers from the decimal system to the binary system and vice versa, etc., are given. In general, we may say that the book by Vaclav Josef Pelikan is the first fully fledged and methodologically sound textbook of arithmetic using the binary number system as well as containing original methods of solution.

entry:
@Article{Zlatopolski:2023:PAV,
  author =       "Dmitry Zlatopolski",
  title =        "{``Perfect Arithmetic'' by Vaclav Josef Pelikan}",
  journal =      j-HIST-MATH,
  volume =       "62",
  number =       "??",
  pages =        "40--50",
  month =        feb,
  year =         "2023",
  CODEN =        "HIMADS",
  DOI =          "https://doi.org/10.1016/j.hm.2022.09.002",
  ISSN =         "0315-0860 (print), 1090-249X (electronic)",
  ISSN-L =       "0315-0860",
  bibdate =      "Wed Mar 15 09:40:56 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/histmath.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0315086022000659",
  abstract =     "The present article describes for the first time the
                 book of Vaclav Josef Pelikan titled
                 \booktitle{Arithmeticus Perfectus Qui tria numerare
                 nescit. Seu Arithmetica dualis, In qua Numerando non
                 proceditur, nisi ad duo, \& tamen omnes quaestiones
                 Arithmeticae negotio facili enodari possunt}, published
                 in Prague in 1712. The book is written in Latin on 86
                 pages and consists of a dedication, a message to the
                 reader and four chapters. Operations in the binary
                 system, including the extraction of square and cube
                 roots, methods of converting numbers from the decimal
                 system to the binary system and vice versa, etc., are
                 given. In general, we may say that the book by Vaclav
                 Josef Pelikan is the first fully fledged and
                 methodologically sound textbook of arithmetic using the
                 binary number system as well as containing original
                 methods of solution.",
  acknowledgement = ack-nhfb,
  fjournal =     "Historia Mathematica",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03150860",
  keywords =     "base conversion; binary arithmetic",
}


bibtype: book
filename: fparith.bib
label: Alsuhli:2024:NSD
title: Number Systems for Deep Neural Network Architectures
publisher: pub-SV
address: pub-SV:adr
pages: 40--50
year: 2024
DOI: https://doi.org/10.1007/978-3-031-38133-1
ISBN: 3-031-38133-5 OR 3031381335
ISBN13: 978-3-031-38133-1 OR 9783031381331
ISSN: 2690-0327 OR 26900327
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
series: Synthesis Lectures on Engineering, Science, and Technology
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawtitle: Number Systems for Deep Neural Network Architectures
author:
Ghada Alsuhli and Vasilis Sakellariou and Hani Saleh and Mahmoud Al-Qutayri and Baker Mohammad and Thanos Stouraitis

rawauthor:
Ghada Alsuhli and Vasilis Sakellariou and Hani Saleh and Mahmoud Al-Qutayri and Baker Mohammad and Thanos Stouraitis

entry:
@Book{Alsuhli:2024:NSD,
  author =       "Ghada Alsuhli and Vasilis Sakellariou and Hani Saleh
                 and Mahmoud Al-Qutayri and Baker Mohammad and Thanos
                 Stouraitis",
  title =        "Number Systems for Deep Neural Network Architectures",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  year =         "2024",
  DOI =          "https://doi.org/10.1007/978-3-031-38133-1",
  ISBN =         "3-031-38133-5",
  ISBN-13 =      "978-3-031-38133-1",
  ISSN =         "2690-0327",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "Synthesis Lectures on Engineering, Science, and
                 Technology",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Angioli:2024:DIE
title: Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme
journal: j-IEEE-TRANS-COMPUT
volume: 73
number: 7
pages: 1767--1779
month: jul
monthnumber: 7
year: 2024
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2024.3386060
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jun 12 15:57:24 2024
bibtimestamp: 2024.06.12 15:57:24 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme
author:
Marco Angioli and Marcello Barbirotta and Abdallah Cheikh and Antonio Mastrandrea and Francesco Menichelli and Saeid Jamili and Mauro Olivieri

keywords:
Benchmark testing; Clocks; computer arithmetic; Field programmable gate arrays; Frequency conversion; Hardware; high-speed arithmetic; integer division; low-power design; real-time and embedded systems; Registers; Signal processing algorithms; Variable-latency divider

rawauthor:
Marco Angioli and Marcello Barbirotta and Abdallah Cheikh and Antonio Mastrandrea and Francesco Menichelli and Saeid Jamili and Mauro Olivieri

entry:
@Article{Angioli:2024:DIE,
  author =       "Marco Angioli and Marcello Barbirotta and Abdallah
                 Cheikh and Antonio Mastrandrea and Francesco Menichelli
                 and Saeid Jamili and Mauro Olivieri",
  title =        "Design, Implementation and Evaluation of a New
                 Variable Latency Integer Division Scheme",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "73",
  number =       "7",
  pages =        "1767--1779",
  month =        jul,
  year =         "2024",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2024.3386060",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jun 12 15:57:24 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Benchmark testing; Clocks; computer arithmetic; Field
                 programmable gate arrays; Frequency conversion;
                 Hardware; high-speed arithmetic; integer division;
                 low-power design; real-time and embedded systems;
                 Registers; Signal processing algorithms;
                 Variable-latency divider",
}


bibtype: article
filename: fparith.bib
label: Bandil:2024:HIU
author: Lalit Bandil and Bal Chand Nagar
journal: j-IEEE-TRANS-COMPUT
volume: 73
number: 12
pages: 2734--2746
year: 2024
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2024.3457731
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Nov 20 07:36:48 2024
bibtimestamp: 2024.11.20 07:36:48 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Lalit Bandil and Bal Chand Nagar
title:
Hardware Implementation of Unsigned Approximate Hybrid Square Rooters for Error-Resilient Applications

keywords:
Accuracy; accuracy metrics; Approximate computing; Arithmetic; Computers; Hardware; hardware implementation; image processing; Image restoration; low power; Measurement; Multiplexing; square rooter

rawtitle:
Hardware Implementation of Unsigned Approximate Hybrid Square Rooters for Error-Resilient Applications

entry:
@Article{Bandil:2024:HIU,
  author =       "Lalit Bandil and Bal Chand Nagar",
  title =        "Hardware Implementation of Unsigned Approximate Hybrid
                 Square Rooters for Error-Resilient Applications",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "73",
  number =       "12",
  pages =        "2734--2746",
  year =         "2024",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2024.3457731",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Nov 20 07:36:48 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Accuracy; accuracy metrics; Approximate computing;
                 Arithmetic; Computers; Hardware; hardware
                 implementation; image processing; Image restoration;
                 low power; Measurement; Multiplexing; square rooter",
}


bibtype: article
filename: fparith.bib
label: Benmaghnia:2024:CGN
author: Hanane Benmaghnia and Matthieu Martel and Yassamine Seladji
title: Code Generation for Neural Networks Based on Fixed-point Arithmetic
journal: j-TECS
volume: 23
number: 5
pages: 68:1--68:??
month: sep
monthnumber: 9
year: 2024
DOI: https://doi.org/10.1145/3563945
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Wed Sep 25 11:16:16 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tecs.bib
bibtimestamp: 2024.09.25 11:16:16 MDT
URL: https://dl.acm.org/doi/10.1145/3563945
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
ajournal: ACM Trans. Embed. Comput. Syst.
articleno: 68
journalURL: https://dl.acm.org/loi/tecs
rawauthor: Hanane Benmaghnia and Matthieu Martel and Yassamine Seladji
rawtitle: Code Generation for Neural Networks Based on Fixed-point Arithmetic
abstract:
Over the past few years, neural networks have started penetrating safety critical systems to make decisions as, for example, in robots, rockets, and autonomous driving cars. Neural networks based on floating-point arithmetic are very time and memory consuming, which are not compatible with embedded systems known to have limited resources. They are also very sensitive to the precision in which they have been trained, so changing this precision generally degrades the quality of their answers. To deal with that, we introduce a new technique to generate a fixed-point code for a trained neural network. This technique is based on fixed-point arithmetic with mixed-precision. This arithmetic is based on integer operations only, which are compatible with small memory devices. The obtained neural network has the same behavior as the initial one (based on the floating-point arithmetic) up to an error threshold defined by the user. The experimental results show the efficiency of our tool SyFix in terms of memory saved and the accuracy of the computations.

rawabstract:
Over the past few years, neural networks have started penetrating safety critical systems to make decisions as, for example, in robots, rockets, and autonomous driving cars. Neural networks based on floating-point arithmetic are very time and memory consuming, which are not compatible with embedded systems known to have limited resources. They are also very sensitive to the precision in which they have been trained, so changing this precision generally degrades the quality of their answers. To deal with that, we introduce a new technique to generate a fixed-point code for a trained neural network. This technique is based on fixed-point arithmetic with mixed-precision. This arithmetic is based on integer operations only, which are compatible with small memory devices. The obtained neural network has the same behavior as the initial one (based on the floating-point arithmetic) up to an error threshold defined by the user. The experimental results show the efficiency of our tool SyFix in terms of memory saved and the accuracy of the computations.

entry:
@Article{Benmaghnia:2024:CGN,
  author =       "Hanane Benmaghnia and Matthieu Martel and Yassamine
                 Seladji",
  title =        "Code Generation for Neural Networks Based on
                 Fixed-point Arithmetic",
  journal =      j-TECS,
  volume =       "23",
  number =       "5",
  pages =        "68:1--68:??",
  month =        sep,
  year =         "2024",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3563945",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Wed Sep 25 11:16:16 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3563945",
  abstract =     "Over the past few years, neural networks have started
                 penetrating safety critical systems to make decisions
                 as, for example, in robots, rockets, and autonomous
                 driving cars. Neural networks based on floating-point
                 arithmetic are very time and memory consuming, which
                 are not compatible with embedded systems known to have
                 limited resources. They are also very sensitive to the
                 precision in which they have been trained, so changing
                 this precision generally degrades the quality of their
                 answers. To deal with that, we introduce a new
                 technique to generate a fixed-point code for a trained
                 neural network. This technique is based on fixed-point
                 arithmetic with mixed-precision. This arithmetic is
                 based on integer operations only, which are compatible
                 with small memory devices. The obtained neural network
                 has the same behavior as the initial one (based on the
                 floating-point arithmetic) up to an error threshold
                 defined by the user. The experimental results show the
                 efficiency of our tool SyFix in terms of memory saved
                 and the accuracy of the computations.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Embed. Comput. Syst.",
  articleno =    "68",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "https://dl.acm.org/loi/tecs",
}


bibtype: techreport
filename: fparith.bib
label: Brisebarre:2024:CRE
author: Nicolas Brisebarre and Guillaume Hanrot and Jean-Michel Muller and Paul Zimmermann
title: Correctly-rounded evaluation of a function: why, how, and at what cost?
type: Report
number: hal-04474530
institution: CNRS --- Centre National de la Recherche Scientifique and others
address: Paris, France
pages: 29
day: 23
month: feb
monthnumber: 2
year: 2024
bibdate: Fri Feb 23 16:11:08 2024
bibtimestamp: 2024.02.23 16:11:08 ???
URL: https://hal.science/hal-04474530
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Guillaume Hanrot and Jean-Michel Muller and Paul Zimmermann
rawtitle: Correctly-rounded evaluation of a function: why, how, and at what cost?
abstract:
The goal of this paper is to convince the reader that a future standard for floating-point arithmetic should require the availability of a correctly-rounded version of a well-chosen core set of elementary functions. We discuss the interest and feasibility of this requirement. We also give answers to common objections we have received over the last 10 years.

keywords:
algorithmic number theory; approximation theory; Computer arithmetic; elementary functions; floating-point arithmetic; lattice basis reduction; LLL algorithm; standardization

rawabstract:
The goal of this paper is to convince the reader that a future standard for floating-point arithmetic should require the availability of a correctly-rounded version of a well-chosen core set of elementary functions. We discuss the interest and feasibility of this requirement. We also give answers to common objections we have received over the last 10 years.

entry:
@TechReport{Brisebarre:2024:CRE,
  author =       "Nicolas Brisebarre and Guillaume Hanrot and
                 Jean-Michel Muller and Paul Zimmermann",
  title =        "Correctly-rounded evaluation of a function: why, how,
                 and at what cost?",
  type =         "Report",
  number =       "hal-04474530",
  institution =  "CNRS --- Centre National de la Recherche Scientifique
                 and others",
  address =      "Paris, France",
  pages =        "29",
  day =          "23",
  month =        feb,
  year =         "2024",
  bibdate =      "Fri Feb 23 16:11:08 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.science/hal-04474530",
  abstract =     "The goal of this paper is to convince the reader that
                 a future standard for floating-point arithmetic should
                 require the availability of a correctly-rounded version
                 of a well-chosen core set of elementary functions. We
                 discuss the interest and feasibility of this
                 requirement. We also give answers to common objections
                 we have received over the last 10 years.",
  acknowledgement = ack-nhfb,
  keywords =     "algorithmic number theory; approximation theory;
                 Computer arithmetic; elementary functions;
                 floating-point arithmetic; lattice basis reduction; LLL
                 algorithm; standardization",
}


bibtype: article
filename: fparith.bib
label: Brogi:2024:FPP
author: F. Brogi and S. Bna and G. Boga and G. Amati and T. Esposti Ongaro and M. Cerminara
title: On floating point precision in computational fluid dynamics using OpenFOAM
journal: j-FUT-GEN-COMP-SYS
volume: 152
pages: 1--16
month: mar
monthnumber: 3
year: 2024
CODEN: FGSEVI
DOI: https://doi.org/10.1016/j.future.2023.10.006
ISSN: 0167-739X (print), 1872-7115 (electronic) OR 0167739X (print), 18727115 (electronic)
ISSNL: 0167-739X OR 0167739X
bibdate: Sat Dec 16 07:26:57 MST 2023
bibtimestamp: 2023.12.16 07:26:57 MST
URL: http://www.sciencedirect.com/science/article/pii/S0167739X23003813
fjournal: Future Generation Computer Systems
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/0167739X
rawauthor: F. Brogi and S. Bn{\`a} and G. Boga and G. Amati and T. Esposti Ongaro and M. Cerminara
rawtitle: On floating point precision in computational fluid dynamics using {OpenFOAM}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/futgencompsys2020.bib

entry:
@Article{Brogi:2024:FPP,
  author =       "F. Brogi and S. Bn{\`a} and G. Boga and G. Amati and
                 T. Esposti Ongaro and M. Cerminara",
  title =        "On floating point precision in computational fluid
                 dynamics using {OpenFOAM}",
  journal =      j-FUT-GEN-COMP-SYS,
  volume =       "152",
  number =       "??",
  pages =        "1--16",
  month =        mar,
  year =         "2024",
  CODEN =        "FGSEVI",
  DOI =          "https://doi.org/10.1016/j.future.2023.10.006",
  ISSN =         "0167-739X (print), 1872-7115 (electronic)",
  ISSN-L =       "0167-739X",
  bibdate =      "Sat Dec 16 07:26:57 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/futgencompsys2020.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0167739X23003813",
  acknowledgement = ack-nhfb,
  fjournal =     "Future Generation Computer Systems",
  journal-URL =  "http://www.sciencedirect.com/science/journal/0167739X",
}


bibtype: article
filename: fparith.bib
label: Cai:2024:TEV
author: Luwei Cai and Fu Song and Taolue Chen
title: Towards Efficient Verification of Constant-Time Cryptographic Implementations
journal: Proceedings of the ACM on Software Engineering
volume: 1
number: FSE
pages: 1019--1042
month: jul
monthnumber: 7
year: 2024
DOI: https://doi.org/10.1145/3643772
ISSN: 2994-970X OR 2994970X
bibdate: Tue Aug 27 07:37:07 2024
bibtimestamp: 2024.08.27 07:37:07 ???
acknowledgement: ack-nhfb
rawauthor: Luwei Cai and Fu Song and Taolue Chen
rawtitle: Towards Efficient Verification of Constant-Time Cryptographic Implementations
abstract:
Timing side-channel attacks exploit secret-dependent execution time to fully or partially recover secrets of cryptographic implementations, posing a severe threat to software security. Constant-time programming discipline is an effective software-based countermeasure against timing side-channel attacks, but developing constant-time implementations turns out to be challenging and error-prone. Current verification approaches/tools suffer from scalability and precision issues when applied to production software in practice. In this paper, we put forward practical verification approaches based on a novel synergy of taint analysis and safety verification of self-composed programs. Specifically, we first use an IFDS-based lightweight taint analysis to prove that a large number of potential (timing) side-channel sources do not actually leak secrets. We then resort to a precise taint analysis and a safety verification approach to determine whether the remaining potential side-channel sources can actually leak secrets. These include novel constructions of taint-directed semi-cross-product of the original program and its Boolean abstraction, and a taint-directed self-composition of the program. Our approach is implemented as a cross-platform and fully automated tool CT-Prover. The experiments confirm its efficiency and effectiveness in verifying real-world benchmarks from modern cryptographic and SSL/TLS libraries. In particular, CT-Prover identify new, confirmed vulnerabilities of open-source SSL libraries (e.g., Mbed SSL, BearSSL) and significantly outperforms the state-of-the-art tool

keywords:
constant-time cryptographic implementation; Formal security models; Formal software verification; formal verification; Logic and verification; Program analysis; Security and privacy; Software and its engineering; taint analysis; Theory of computation; Timing side-channel

rawabstract:
Timing side-channel attacks exploit secret-dependent execution time to fully or partially recover secrets of cryptographic implementations, posing a severe threat to software security. Constant-time programming discipline is an effective software-based countermeasure against timing side-channel attacks, but developing constant-time implementations turns out to be challenging and error-prone. Current verification approaches/tools suffer from scalability and precision issues when applied to production software in practice. In this paper, we put forward practical verification approaches based on a novel synergy of taint analysis and safety verification of self-composed programs. Specifically, we first use an IFDS-based lightweight taint analysis to prove that a large number of potential (timing) side-channel sources do not actually leak secrets. We then resort to a precise taint analysis and a safety verification approach to determine whether the remaining potential side-channel sources can actually leak secrets. These include novel constructions of taint-directed semi-cross-product of the original program and its Boolean abstraction, and a taint-directed self-composition of the program. Our approach is implemented as a cross-platform and fully automated tool CT-Prover. The experiments confirm its efficiency and effectiveness in verifying real-world benchmarks from modern cryptographic and SSL/TLS libraries. In particular, CT-Prover identify new, confirmed vulnerabilities of open-source SSL libraries (e.g., Mbed SSL, BearSSL) and significantly outperforms the state-of-the-art tool

entry:
@Article{Cai:2024:TEV,
  author =       "Luwei Cai and Fu Song and Taolue Chen",
  title =        "Towards Efficient Verification of Constant-Time
                 Cryptographic Implementations",
  journal =      "Proceedings of the ACM on Software Engineering",
  volume =       "1",
  number =       "FSE",
  pages =        "1019--1042",
  month =        jul,
  year =         "2024",
  DOI =          "https://doi.org/10.1145/3643772",
  ISSN =         "2994-970X",
  bibdate =      "Tue Aug 27 07:37:07 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Timing side-channel attacks exploit secret-dependent
                 execution time to fully or partially recover secrets of
                 cryptographic implementations, posing a severe threat
                 to software security. Constant-time programming
                 discipline is an effective software-based
                 countermeasure against timing side-channel attacks, but
                 developing constant-time implementations turns out to
                 be challenging and error-prone. Current verification
                 approaches/tools suffer from scalability and precision
                 issues when applied to production software in practice.
                 In this paper, we put forward practical verification
                 approaches based on a novel synergy of taint analysis
                 and safety verification of self-composed programs.
                 Specifically, we first use an IFDS-based lightweight
                 taint analysis to prove that a large number of
                 potential (timing) side-channel sources do not actually
                 leak secrets. We then resort to a precise taint
                 analysis and a safety verification approach to
                 determine whether the remaining potential side-channel
                 sources can actually leak secrets. These include novel
                 constructions of taint-directed semi-cross-product of
                 the original program and its Boolean abstraction, and a
                 taint-directed self-composition of the program. Our
                 approach is implemented as a cross-platform and fully
                 automated tool CT-Prover. The experiments confirm its
                 efficiency and effectiveness in verifying real-world
                 benchmarks from modern cryptographic and SSL/TLS
                 libraries. In particular, CT-Prover identify new,
                 confirmed vulnerabilities of open-source SSL libraries
                 (e.g., Mbed SSL, BearSSL) and significantly outperforms
                 the state-of-the-art tool",
  acknowledgement = ack-nhfb,
  keywords =     "constant-time cryptographic implementation; Formal
                 security models; Formal software verification; formal
                 verification; Logic and verification; Program analysis;
                 Security and privacy; Software and its engineering;
                 taint analysis; Theory of computation; Timing
                 side-channel",
}


bibtype: article
filename: fparith.bib
label: Cameron:2024:AHM
author: Thomas R. Cameron and Stef Graillat
title: Accurate Horner methods in real and complex floating-point arithmetic
journal: j-BIT-NUM-MATH
volume: 64
number: 2
pages: ??--??
month: jun
monthnumber: 6
year: 2024
CODEN: BITTEL, NBITAB
DOI: https://doi.org/10.1007/s10543-024-01017-w
ISSN: 0006-3835 (print), 1572-9125 (electronic) OR 00063835 (print), 15729125 (electronic)
ISSNL: 0006-3835 OR 00063835
bibdate: Tue May 28 15:02:24 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/bit.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.28 15:02:24 MDT
URL: https://link.springer.com/article/10.1007/s10543-024-01017-w
fjournal: BIT Numerical Mathematics
acknowledgement: ack-nhfb
ajournal: Bit Num. Math.
articleno: 17
journalURL: http://link.springer.com/journal/10543
rawauthor: Thomas R. Cameron and Stef Graillat
rawtitle: Accurate {Horner} methods in real and complex floating-point arithmetic
entry:
@Article{Cameron:2024:AHM,
  author =       "Thomas R. Cameron and Stef Graillat",
  title =        "Accurate {Horner} methods in real and complex
                 floating-point arithmetic",
  journal =      j-BIT-NUM-MATH,
  volume =       "64",
  number =       "2",
  pages =        "??--??",
  month =        jun,
  year =         "2024",
  CODEN =        "BITTEL, NBITAB",
  DOI =          "https://doi.org/10.1007/s10543-024-01017-w",
  ISSN =         "0006-3835 (print), 1572-9125 (electronic)",
  ISSN-L =       "0006-3835",
  bibdate =      "Tue May 28 15:02:24 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/bit.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://link.springer.com/article/10.1007/s10543-024-01017-w",
  acknowledgement = ack-nhfb,
  ajournal =     "Bit Num. Math.",
  articleno =    "17",
  fjournal =     "BIT Numerical Mathematics",
  journal-URL =  "http://link.springer.com/journal/10543",
}


bibtype: techreport
filename: fparith.bib
label: Caprioli:2024:ACM
author: Paul Caprioli and Vincenzo Innocente and Paul Zimmermann
title: Accuracy of Complex Mathematical Operations and Functions in Single and Double Precision
type: Report
number: hal-04714173
institution: High Performance Kernels LLC
pages: 8
day: 30
month: sep
monthnumber: 9
year: 2024
bibdate: Mon Sep 30 06:08:35 2024
bibtimestamp: 2024.09.30 06:08:35 ???
URL: https://inria.hal.science/hal-04714173v1
acknowledgement: ack-nhfb
rawauthor: Paul Caprioli and Vincenzo Innocente and Paul Zimmermann
rawtitle: Accuracy of Complex Mathematical Operations and Functions in Single and Double Precision
entry:
@TechReport{Caprioli:2024:ACM,
  author =       "Paul Caprioli and Vincenzo Innocente and Paul
                 Zimmermann",
  title =        "Accuracy of Complex Mathematical Operations and
                 Functions in Single and Double Precision",
  type =         "Report",
  number =       "hal-04714173",
  institution =  "High Performance Kernels LLC",
  address =      "????",
  pages =        "8",
  day =          "30",
  month =        sep,
  year =         "2024",
  bibdate =      "Mon Sep 30 06:08:35 2024",
  URL =          "https://inria.hal.science/hal-04714173v1",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Demmel:2024:EDS
author: Jim Demmel
title: Exploring the Design Space of Exception Handling
pages: 42
day: 22
month: aug
monthnumber: 8
year: 2024
bibdate: Tue Aug 27 08:09:27 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.27 08:09:27 ???
URL: ExceptionHandling_22Aug2024.pdf
acknowledgement: ack-nhfb
howpublished: Posting to STDS-754 mailing list.
rawauthor: Jim Demmel
rawtitle: Exploring the Design Space of Exception Handling
note:
Lecture slides on progress in research on floating-point exception handling, notably in LAPACK and the BLAS (Basic Linear Algebra Subroutines).

rawnote:
Lecture slides on progress in research on floating-point exception handling, notably in LAPACK and the BLAS (Basic Linear Algebra Subroutines).

entry:
@Misc{Demmel:2024:EDS,
  author =       "Jim Demmel",
  title =        "Exploring the Design Space of Exception Handling",
  howpublished = "Posting to STDS-754 mailing list.",
  pages =        "42",
  day =          "22",
  month =        aug,
  year =         "2024",
  bibdate =      "Tue Aug 27 08:09:27 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Lecture slides on progress in research on
                 floating-point exception handling, notably in LAPACK
                 and the BLAS (Basic Linear Algebra Subroutines).",
  URL =          "ExceptionHandling_22Aug2024.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Deng:2024:FPE
author: Bobin Deng and Bhargava Nadendla and Kun Suo and Yixin Xie and Dan Chia-Tien Lo
title: Fixed-point Encoding and Architecture Exploration for Residue Number Systems
journal: j-TACO
volume: 21
number: 3
pages: 53:1--53:??
month: sep
monthnumber: 9
year: 2024
DOI: https://doi.org/10.1145/3664923
ISSN: 1544-3566 (print), 1544-3973 (electronic) OR 15443566 (print), 15443973 (electronic)
ISSNL: 1544-3566 OR 15443566
bibdate: Sat Sep 21 06:05:41 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/taco.bib
bibtimestamp: 2024.09.21 06:05:41 MDT
URL: https://dl.acm.org/doi/10.1145/3664923
fjournal: ACM Transactions on Architecture and Code Optimization (TACO)
acknowledgement: ack-nhfb
ajournal: ACM Trans. Archit. Code Optim.
articleno: 53
journalURL: https://dl.acm.org/loi/taco
rawauthor: Bobin Deng and Bhargava Nadendla and Kun Suo and Yixin Xie and Dan Chia-Tien Lo
rawtitle: Fixed-point Encoding and Architecture Exploration for Residue Number Systems
abstract:
Residue Number Systems (RNS) demonstrate the fascinating potential to serve integer addition / multiplication-intensive applications. The complexity of Artificial Intelligence (AI) models has grown enormously in recent years. From a computer system's perspective, ensuring the training of these large-scale AI models within an adequate time and energy consumption has become a big concern. Matrix multiplication is a dominant subroutine in many prevailing AI models, with an addition / multiplication-intensive attribute. However, the data type of matrix multiplication within machine learning training typically requires real numbers, which indicates that RNS benefits for integer applications cannot be directly gained by AI training. The state-of-the-art RNS real-number encodings, including floating-point and fixed-point, have defects and can be further enhanced. To transform default RNS benefits to the efficiency of large-scale AI training, we propose a low-cost and high-accuracy RNS fixed-point representation: Single RNS Logical Partition (S-RNS-Logic-P) representation with Scaling-down Postprocessing Multiplication (SD-Post-Mul). Moreover, we extend the implementation details of the other two RNS fixed-point methods: Double RNS Concatenation and S-RNS-Logic-P representation with Scaling-down Preprocessing Multiplication. We also design the architectures of these three fixed-point multipliers. In empirical experiments, our S-RNS-Logic-P representation with SD-Post-Mul method achieves less latency and energy overhead while maintaining good accuracy. Furthermore, this method can easily extend to the Redundant Residue Number System to raise the efficiency of error-tolerant domains, such as improving the error correction efficiency of quantum computing.

rawabstract:
Residue Number Systems (RNS) demonstrate the fascinating potential to serve integer addition\slash multiplication-intensive applications. The complexity of Artificial Intelligence (AI) models has grown enormously in recent years. From a computer system's perspective, ensuring the training of these large-scale AI models within an adequate time and energy consumption has become a big concern. Matrix multiplication is a dominant subroutine in many prevailing AI models, with an addition\slash multiplication-intensive attribute. However, the data type of matrix multiplication within machine learning training typically requires real numbers, which indicates that RNS benefits for integer applications cannot be directly gained by AI training. The state-of-the-art RNS real-number encodings, including floating-point and fixed-point, have defects and can be further enhanced. To transform default RNS benefits to the efficiency of large-scale AI training, we propose a low-cost and high-accuracy RNS fixed-point representation: Single RNS Logical Partition (S-RNS-Logic-P) representation with Scaling-down Postprocessing Multiplication (SD-Post-Mul). Moreover, we extend the implementation details of the other two RNS fixed-point methods: Double RNS Concatenation and S-RNS-Logic-P representation with Scaling-down Preprocessing Multiplication. We also design the architectures of these three fixed-point multipliers. In empirical experiments, our S-RNS-Logic-P representation with SD-Post-Mul method achieves less latency and energy overhead while maintaining good accuracy. Furthermore, this method can easily extend to the Redundant Residue Number System to raise the efficiency of error-tolerant domains, such as improving the error correction efficiency of quantum computing.

entry:
@Article{Deng:2024:FPE,
  author =       "Bobin Deng and Bhargava Nadendla and Kun Suo and Yixin
                 Xie and Dan Chia-Tien Lo",
  title =        "Fixed-point Encoding and Architecture Exploration for
                 Residue Number Systems",
  journal =      j-TACO,
  volume =       "21",
  number =       "3",
  pages =        "53:1--53:??",
  month =        sep,
  year =         "2024",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3664923",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Sat Sep 21 06:05:41 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3664923",
  abstract =     "Residue Number Systems (RNS) demonstrate the
                 fascinating potential to serve integer addition\slash
                 multiplication-intensive applications. The complexity
                 of Artificial Intelligence (AI) models has grown
                 enormously in recent years. From a computer system's
                 perspective, ensuring the training of these large-scale
                 AI models within an adequate time and energy
                 consumption has become a big concern. Matrix
                 multiplication is a dominant subroutine in many
                 prevailing AI models, with an addition\slash
                 multiplication-intensive attribute. However, the data
                 type of matrix multiplication within machine learning
                 training typically requires real numbers, which
                 indicates that RNS benefits for integer applications
                 cannot be directly gained by AI training. The
                 state-of-the-art RNS real-number encodings, including
                 floating-point and fixed-point, have defects and can be
                 further enhanced. To transform default RNS benefits to
                 the efficiency of large-scale AI training, we propose a
                 low-cost and high-accuracy RNS fixed-point
                 representation: Single RNS Logical Partition
                 (S-RNS-Logic-P) representation with Scaling-down
                 Postprocessing Multiplication (SD-Post-Mul). Moreover,
                 we extend the implementation details of the other two
                 RNS fixed-point methods: Double RNS Concatenation and
                 S-RNS-Logic-P representation with Scaling-down
                 Preprocessing Multiplication. We also design the
                 architectures of these three fixed-point multipliers.
                 In empirical experiments, our S-RNS-Logic-P
                 representation with SD-Post-Mul method achieves less
                 latency and energy overhead while maintaining good
                 accuracy. Furthermore, this method can easily extend to
                 the Redundant Residue Number System to raise the
                 efficiency of error-tolerant domains, such as improving
                 the error correction efficiency of quantum computing.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Archit. Code Optim.",
  articleno =    "53",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "https://dl.acm.org/loi/taco",
}


bibtype: article
filename: fparith.bib
label: ElArar:2024:BNE
author: E-M. El Arar and D. Sohier and P. de Oliveira Castro and E. Petit
title: Bounds on Nonlinear Errors for Variance Computation with Stochastic Rounding
journal: j-SIAM-J-SCI-COMP
volume: 46
number: 5
pages: B579--B599
year: 2024
CODEN: SJOCE3
DOI: https://doi.org/10.1137/23M1563001
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Mon Sep 30 10:38:50 MDT 2024
bibtimestamp: 2024.09.30 10:38:50 MDT
URL: https://epubs.siam.org/doi/10.1137/23M1563001
fjournal: SIAM Journal on Scientific Computing
keywords: accurate floating-point summation; stochastic rounding
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: E-M. {El Arar} and D. Sohier and P. {de Oliveira Castro} and E. Petit
rawtitle: Bounds on Nonlinear Errors for Variance Computation with Stochastic Rounding
bibsource:
http://epubs.siam.org/toc/sjoce3/46/5; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

entry:
@Article{ElArar:2024:BNE,
  author =       "E-M. {El Arar} and D. Sohier and P. {de Oliveira
                 Castro} and E. Petit",
  title =        "Bounds on Nonlinear Errors for Variance Computation
                 with Stochastic Rounding",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "46",
  number =       "5",
  pages =        "B579--B599",
  month =        "????",
  year =         "2024",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/23M1563001",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Mon Sep 30 10:38:50 MDT 2024",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/46/5;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  URL =          "https://epubs.siam.org/doi/10.1137/23M1563001",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "accurate floating-point summation; stochastic
                 rounding",
}


bibtype: article
filename: fparith.bib
label: Faissole:2024:FVR
author: Florian Faissole
title: Formally-Verified Round-Off Error Analysis of Runge--Kutta Methods
journal: j-J-AUTOM-REASON
volume: 68
number: 1
pages: ??--??
month: mar
monthnumber: 3
year: 2024
CODEN: JAREEW
DOI: https://doi.org/10.1007/s10817-023-09686-y
ISSN: 0168-7433 (print), 1573-0670 (electronic) OR 01687433 (print), 15730670 (electronic)
ISSNL: 0168-7433 OR 01687433
bibdate: Fri May 24 08:31:25 MDT 2024
bibtimestamp: 2024.05.24 08:31:25 MDT
URL: https://link.springer.com/article/10.1007/s10817-023-09686-y
fjournal: Journal of Automated Reasoning
acknowledgement: ack-nhfb
ajournal: J. Autom. Reason.
articleno: 1
journalURL: http://link.springer.com/journal/10817
rawauthor: Florian Faissole
rawtitle: Formally-Verified Round-Off Error Analysis of {Runge--Kutta} Methods
entry:
@Article{Faissole:2024:FVR,
  author =       "Florian Faissole",
  title =        "Formally-Verified Round-Off Error Analysis of
                 {Runge--Kutta} Methods",
  journal =      j-J-AUTOM-REASON,
  volume =       "68",
  number =       "1",
  pages =        "??--??",
  month =        mar,
  year =         "2024",
  CODEN =        "JAREEW",
  DOI =          "https://doi.org/10.1007/s10817-023-09686-y",
  ISSN =         "0168-7433 (print), 1573-0670 (electronic)",
  ISSN-L =       "0168-7433",
  bibdate =      "Fri May 24 08:31:25 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jautomreason.bib",
  URL =          "https://link.springer.com/article/10.1007/s10817-023-09686-y",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Autom. Reason.",
  articleno =    "1",
  fjournal =     "Journal of Automated Reasoning",
  journal-URL =  "http://link.springer.com/journal/10817",
}


bibtype: techreport
filename: fparith.bib
label: Fog:2024:FPE
author: Agner Fog
title: Floating point exception tracking and NAN propagation
type: Report
institution: Technical University of Denmark
address: Lyngby, Denmark
pages: 11
day: 15
month: aug
monthnumber: 8
year: 2024
bibdate: Wed Jan 15 10:06:11 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.01.15 10:06:11 ???
URL: https://www.agner.org/optimize/nan_propagation.pdf
remark: Revision of cite Fog:2020:FPE and cite Fog:2023:FPE.
acknowledgement: ack-nhfb
rawauthor: Agner Fog
rawtitle: Floating point exception tracking and {NAN} propagation
entry:
@TechReport{Fog:2024:FPE,
  author =       "Agner Fog",
  title =        "Floating point exception tracking and {NAN}
                 propagation",
  type =         "Report",
  institution =  "Technical University of Denmark",
  address =      "Lyngby, Denmark",
  pages =        "11",
  day =          "15",
  month =        aug,
  year =         "2024",
  bibdate =      "Wed Jan 15 10:06:11 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.agner.org/optimize/nan_propagation.pdf",
  abstract =     "The most common methods for detecting floating point
                 errors are based on exception trapping or a global
                 status register. These methods are inefficient in
                 modern systems that use out-of-order parallelism and
                 single-instruction-multiple-data (SIMD) parallelism for
                 improving performance. It is argued that a method based
                 on NAN propagation is more efficient and deterministic.
                 Problems with NAN propagation in current systems are
                 discussed. Examples of implementation in the C++ vector
                 class library and in an experimental instruction set
                 named ForwardCom are presented. The IEEE-754 standard
                 for floating point arithmetic may need adjustment to
                 accommodate the needs of modern forms of parallelism.",
  acknowledgement = ack-nhfb,
  remark =       "Revision of \cite{Fog:2020:FPE} and
                 \cite{Fog:2023:FPE}.",
}


bibtype: techreport
filename: fparith.bib
label: Gladman:2024:AMFa
author: Brian Gladman and Vincenzo Innocente and John Mather and Paul Zimmermann
title: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
pages: 25
day: 15
month: feb
monthnumber: 2
year: 2024
bibdate: Thu Feb 15 13:17:22 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.02.15 13:17:22 ???
URL: https://hal.inria.fr/hal-03141101; https://members.loria.fr/PZimmermann/papers/accuracy.pdf
acknowledgement: ack-nhfb
rawauthor: Brian Gladman and Vincenzo Innocente and John Mather and Paul Zimmermann
rawtitle: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
remark:
Tabular comparison of AMD, Apple, ARM, CUDA, FreeBSD, GNU, Intel, LLVM, Microsoft Musl, Newlib, OpenLibm, RadeonOpenCompute (ROCm), and RedHat -lm libraries for correct rounding, versus results from MPFR.

entry:
@TechReport{Gladman:2024:AMFa,
  author =       "Brian Gladman and Vincenzo Innocente and John Mather
                 and Paul Zimmermann",
  title =        "Accuracy of Mathematical Functions in Single, Double,
                 Double Extended, and Quadruple Precision",
  institution =  "????",
  pages =        "25",
  day =          "15",
  month =        feb,
  year =         "2024",
  bibdate =      "Thu Feb 15 13:17:22 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.inria.fr/hal-03141101;
                 https://members.loria.fr/PZimmermann/papers/accuracy.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Tabular comparison of AMD, Apple, ARM, CUDA, FreeBSD,
                 GNU, Intel, LLVM, Microsoft Musl, Newlib, OpenLibm,
                 RadeonOpenCompute (ROCm), and RedHat -lm libraries for
                 correct rounding, versus results from MPFR.",
}


bibtype: techreport
filename: fparith.bib
label: Gladman:2024:AMFb
author: Brian Gladman and Vincenzo Innocente and John Mather and Paul Zimmermann
title: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
pages: 25
day: 26
month: aug
monthnumber: 8
year: 2024
bibdate: Thu Sep 19 14:49:38 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.09.19 14:49:38 ???
URL: https://members.loria.fr/PZimmermann/papers/accuracy.pdf
acknowledgement: ack-nhfb
rawauthor: Brian Gladman and Vincenzo Innocente and John Mather and Paul Zimmermann
rawtitle: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
remark:
Tabular comparison of AMD, Apple, ARM, CUDA, FreeBSD, GNU, Intel, LLVM, Microsoft Musl, Newlib, OpenLibm, RadeonOpenCompute (ROCm), and RedHat -lm libraries for correct rounding, versus results from MPFR.

entry:
@TechReport{Gladman:2024:AMFb,
  author =       "Brian Gladman and Vincenzo Innocente and John Mather
                 and Paul Zimmermann",
  title =        "Accuracy of Mathematical Functions in Single, Double,
                 Double Extended, and Quadruple Precision",
  institution =  "????",
  pages =        "25",
  day =          "26",
  month =        aug,
  year =         "2024",
  bibdate =      "Thu Sep 19 14:49:38 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://members.loria.fr/PZimmermann/papers/accuracy.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Tabular comparison of AMD, Apple, ARM, CUDA, FreeBSD,
                 GNU, Intel, LLVM, Microsoft Musl, Newlib, OpenLibm,
                 RadeonOpenCompute (ROCm), and RedHat -lm libraries for
                 correct rounding, versus results from MPFR.",
}


bibtype: article
filename: fparith.bib
label: Guthmuller:2024:XRV
title: Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation
journal: j-IEEE-TRANS-COMPUT
volume: 73
number: 7
pages: 1683--1697
month: jul
monthnumber: 7
year: 2024
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2024.3383964
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jun 12 15:57:24 2024
bibtimestamp: 2024.06.12 15:57:24 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: {Xvpfloat}: {RISC-V} {ISA} Extension for Variable Extended Precision Floating Point Computation
author:
Eric Guthmuller and Cesar Fuguet and Andrea Bocco and Jerome Fereyre and Riccardo Alidori and Ihsane Tahir and Yves Durand

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib

keywords:
application specific processor; Arithmetic; Computer architecture; Convergence; coprocessor; Field programmable gate arrays; floating point arithmetic; Hardware; high precision arithmetic; Instruction sets; linear algebra; Open area test sites; RISC-V; scientific computing; Software

rawauthor:
Eric Guthmuller and C{\'e}sar Fuguet and Andrea Bocco and J{\'e}r{\^o}me Fereyre and Riccardo Alidori and Ihsane Tahir and Yves Durand

entry:
@Article{Guthmuller:2024:XRV,
  author =       "Eric Guthmuller and C{\'e}sar Fuguet and Andrea Bocco
                 and J{\'e}r{\^o}me Fereyre and Riccardo Alidori and
                 Ihsane Tahir and Yves Durand",
  title =        "{Xvpfloat}: {RISC-V} {ISA} Extension for Variable
                 Extended Precision Floating Point Computation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "73",
  number =       "7",
  pages =        "1683--1697",
  month =        jul,
  year =         "2024",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2024.3383964",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jun 12 15:57:24 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "application specific processor; Arithmetic; Computer
                 architecture; Convergence; coprocessor; Field
                 programmable gate arrays; floating point arithmetic;
                 Hardware; high precision arithmetic; Instruction sets;
                 linear algebra; Open area test sites; RISC-V;
                 scientific computing; Software",
}


bibtype: article
filename: fparith.bib
label: Haider:2024:DRA
author: Muhammad Hamis Haider and Hao Zhang and Seok-Bum Ko
title: Decoder Reduction Approximation Scheme for Booth Multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 73
number: 3
pages: 735--746
month: mar
monthnumber: 3
year: 2024
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2023.3343093
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Feb 16 07:37:44 2024
bibtimestamp: 2024.02.16 07:37:44 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Muhammad Hamis Haider and Hao Zhang and Seok-Bum Ko
rawtitle: Decoder Reduction Approximation Scheme for {Booth} Multipliers
keywords:
Adders; approximate computing; Booth multipliers; Complexity theory; Computer architecture; convolutional neural networks; Decoding; Error analysis; Filtration; Hardware; leading one detection; logarithmic multipliers

entry:
@Article{Haider:2024:DRA,
  author =       "Muhammad Hamis Haider and Hao Zhang and Seok-Bum Ko",
  title =        "Decoder Reduction Approximation Scheme for {Booth}
                 Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "73",
  number =       "3",
  pages =        "735--746",
  month =        mar,
  year =         "2024",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3343093",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Feb 16 07:37:44 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adders; approximate computing; Booth multipliers;
                 Complexity theory; Computer architecture; convolutional
                 neural networks; Decoding; Error analysis; Filtration;
                 Hardware; leading one detection; logarithmic
                 multipliers",
}


bibtype: article
filename: fparith.bib
label: Harris:2024:UDS
title: Unified Digit Selection for Radix-4 Recurrence Division and Square Root
journal: j-IEEE-TRANS-COMPUT
volume: 73
number: 1
pages: 292--300
month: jan
monthnumber: 1
year: 2024
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2023.3305760
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Dec 27 15:37:27 2023
bibtimestamp: 2023.12.27 15:37:27 ???
fjournal: IEEE Transactions on Computers
keywords: division; minimally-redundant radix-4; RISC-V; square root; SRT
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: Unified Digit Selection for Radix-4 Recurrence Division and Square Root
author:
David Harris and James Stine and Milo Ercegovac and Alberto Nannarelli and Katherine Parry and Cedar Turek

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib

rawauthor:
David Harris and James Stine and Milo Ercegovac and Alberto Nannarelli and Katherine Parry and Cedar Turek

entry:
@Article{Harris:2024:UDS,
  author =       "David Harris and James Stine and Milo Ercegovac and
                 Alberto Nannarelli and Katherine Parry and Cedar
                 Turek",
  title =        "Unified Digit Selection for Radix-4 Recurrence
                 Division and Square Root",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "73",
  number =       "1",
  pages =        "292--300",
  month =        jan,
  year =         "2024",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3305760",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Dec 27 15:37:27 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "division; minimally-redundant radix-4; RISC-V; square
                 root; SRT",
}


bibtype: article
filename: fparith.bib
label: Harvey:2024:FTI
author: David Harvey
title: Faster truncated integer multiplication
journal: j-MATH-COMPUT
volume: 93
number: 347
pages: 1265--1296
month: jul
monthnumber: 7
year: 2024
CODEN: MCMPAF
DOI: https://doi.org/10.1090/mcom/3939
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Mon May 27 15:56:44 MDT 2024
bibtimestamp: 2024.05.27 15:56:44 MDT
URL: https://www.ams.org/journals/mcom/2024-93-347/S0025-5718-2024-03939-X
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
journalURL: https://www.ams.org/mcom/
rawauthor: David Harvey
rawtitle: Faster truncated integer multiplication
bibsource:
https://www.ams.org/mcom/2024-93-347; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp2020.bib

entry:
@Article{Harvey:2024:FTI,
  author =       "David Harvey",
  title =        "Faster truncated integer multiplication",
  journal =      j-MATH-COMPUT,
  volume =       "93",
  number =       "347",
  pages =        "1265--1296",
  month =        jul,
  year =         "2024",
  CODEN =        "MCMPAF",
  DOI =          "https://doi.org/10.1090/mcom/3939",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Mon May 27 15:56:44 MDT 2024",
  bibsource =    "https://www.ams.org/mcom/2024-93-347;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp2020.bib",
  URL =          "https://www.ams.org/journals/mcom/2024-93-347/S0025-5718-2024-03939-X",
  acknowledgement = ack-nhfb,
  fjournal =     "Mathematics of Computation",
  journal-URL =  "https://www.ams.org/mcom/",
  pubdate =      "2 February 2024",
}


bibtype: techreport
filename: fparith.bib
label: Hubrecht:2024:TCR
author: Tom Hubrecht and Claude-Pierre Jeannerod and Paul Zimmermann and Laurence Rideau and Laurent Thery
title: Towards a correctly-rounded and fast power function in binary64 arithmetic
type: Report
institution: DI-ENS --- Departement d'informatique --- ENS Paris
address: Paris, France
pages: 1265--1296
day: 8
month: feb
monthnumber: 2
year: 2024
bibdate: Mon May 13 12:00:21 2024
bibtimestamp: 2024.05.13 12:00:21 ???
URL: https://inria.hal.science/hal-04159652v2/
acknowledgement: ack-nhfb
rawtitle: Towards a correctly-rounded and fast power function in binary64 arithmetic
abstract:
We design algorithms for the correct rounding of the power function $x^y$ in the binary64 IEEE 754 format, for all rounding modes, modulo the knowledge of hardest-to-round cases. Our implementation of these algorithms largely outperforms previous correctly-rounded implementations and is not far from the efficiency of current mathematical libraries, which are not correctly-rounded. Still, we expect our algorithms can be further improved for speed. The proofs of correctness are fully detailed and have been formally verified. We hope this work will motivate the next IEEE 754 revision committee to require correct rounding for mathematical functions.

remark:
This is a longer version of cite Hubrecht:2023:TCRb with proofs and remarks by the final two authors on the formal verification.

rawabstract:
We design algorithms for the correct rounding of the power function $x^y$ in the binary64 IEEE 754 format, for all rounding modes, modulo the knowledge of hardest-to-round cases. Our implementation of these algorithms largely outperforms previous correctly-rounded implementations and is not far from the efficiency of current mathematical libraries, which are not correctly-rounded. Still, we expect our algorithms can be further improved for speed. The proofs of correctness are fully detailed and have been formally verified. We hope this work will motivate the next IEEE 754 revision committee to require correct rounding for mathematical functions.

rawauthor:
Tom Hubrecht and Claude-Pierre Jeannerod and Paul Zimmermann and Laurence Rideau and Laurent Th{\'e}ry

entry:
@TechReport{Hubrecht:2024:TCR,
  author =       "Tom Hubrecht and Claude-Pierre Jeannerod and Paul
                 Zimmermann and Laurence Rideau and Laurent Th{\'e}ry",
  title =        "Towards a correctly-rounded and fast power function in
                 binary64 arithmetic",
  institution =  "DI-ENS --- D{\'e}partement d'informatique --- ENS
                 Paris",
  year =         "2024",
  type =         "Report",
  address =      "Paris, France",
  month =        feb,
  day =          "8",
  URL =          "https://inria.hal.science/hal-04159652v2/",
  acknowledgement = ack-nhfb,
  bibdate =      "Mon May 13 12:00:21 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We design algorithms for the correct rounding of the
                 power function $x^y$ in the binary64 IEEE 754 format,
                 for all rounding modes, modulo the knowledge of
                 hardest-to-round cases. Our implementation of these
                 algorithms largely outperforms previous
                 correctly-rounded implementations and is not far from
                 the efficiency of current mathematical libraries, which
                 are not correctly-rounded. Still, we expect our
                 algorithms can be further improved for speed. The
                 proofs of correctness are fully detailed and have been
                 formally verified. We hope this work will motivate the
                 next IEEE 754 revision committee to require correct
                 rounding for mathematical functions.",
  remark =       "This is a longer version of \cite{Hubrecht:2023:TCRb}
                 with proofs and remarks by the final two authors on the
                 formal verification.",
}


bibtype: techreport
filename: fparith.bib
label: Hubrecht:2024:UAC
author: Tom Hubrecht and Claude-Pierre Jeannerod and Jean-Michel Muller
title: Useful applications of correctly-rounded operators of the form $ a b + c d + e $
type: Report
number: hal-04461089
institution: DI-ENS (Department d'informatique --- ENS Paris) and Universite de Lyon
address: Paris, France and Lyon France
pages: 1265--1296
day: 16
month: feb
monthnumber: 2
year: 2024
bibdate: Thu Feb 22 05:37:30 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.02.22 05:37:30 ???
URL: https://inria.hal.science/hal-04461089
acknowledgement: ack-nhfb
rawauthor: Tom Hubrecht and Claude-Pierre Jeannerod and Jean-Michel Muller
rawtitle: Useful applications of correctly-rounded operators of the form $ a b + c d + e $
abstract:
We show that the availability of fused arithmetic operators that evaluate expressions of the form $ a b + c d $ (FD2 instruction) or $ a b + c d + e $ (FD2A instruction) in floating-point arithmetic with one final rounding only would significantly facilitate many calculations that are hard to perform with high accuracy at small cost using only the traditional operations $+$, $-$, $ div $, $ times $, $ sqrt $, and fused multiply-add (FMA).

rawabstract:
We show that the availability of fused arithmetic operators that evaluate expressions of the form $ a b + c d $ (FD2 instruction) or $ a b + c d + e $ (FD2A instruction) in floating-point arithmetic with one final rounding only would significantly facilitate many calculations that are hard to perform with high accuracy at small cost using only the traditional operations $+$, $-$, $ \div $, $ \times $, $ \sqrt {} $, and fused multiply-add (FMA).

entry:
@TechReport{Hubrecht:2024:UAC,
  author =       "Tom Hubrecht and Claude-Pierre Jeannerod and
                 Jean-Michel Muller",
  title =        "Useful applications of correctly-rounded operators of
                 the form $ a b + c d + e $",
  type =         "Report",
  number =       "hal-04461089",
  institution =  "DI-ENS (D{\'e}partment d'informatique --- ENS Paris)
                 and Universit{\'e} de Lyon",
  address =      "Paris, France and Lyon France",
  day =          "16",
  month =        feb,
  year =         "2024",
  bibdate =      "Thu Feb 22 05:37:30 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://inria.hal.science/hal-04461089",
  abstract =     "We show that the availability of fused arithmetic
                 operators that evaluate expressions of the form $ a b +
                 c d $ (FD2 instruction) or $ a b + c d + e $ (FD2A
                 instruction) in floating-point arithmetic with one
                 final rounding only would significantly facilitate many
                 calculations that are hard to perform with high
                 accuracy at small cost using only the traditional
                 operations $+$, $-$, $ \div $, $ \times $, $ \sqrt {}
                 $, and fused multiply-add (FMA).",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kim:2024:MCA
author: Kwang Ho Kim and Sihem Mesnager and Kyong Il Pak
title: Montgomery curve arithmetic revisited
journal: j-J-CRYPTO-ENG
volume: 14
number: 2
pages: 343--362
month: jun
monthnumber: 6
year: 2024
DOI: https://doi.org/10.1007/s13389-024-00353-5
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Thu Aug 8 07:34:12 MDT 2024
bibtimestamp: 2024.08.08 07:34:12 MDT
note: See cite Montgomery:1987:SPE.
URL: https://link.springer.com/article/10.1007/s13389-024-00353-5
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
ajournal: J. Crypto. Eng.
journalURL: http://link.springer.com/journal/13389
rawauthor: Kwang Ho Kim and Sihem Mesnager and Kyong Il Pak
rawnote: See \cite{Montgomery:1987:SPE}.
rawtitle: {Montgomery} curve arithmetic revisited
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib

entry:
@Article{Kim:2024:MCA,
  author =       "Kwang Ho Kim and Sihem Mesnager and Kyong Il Pak",
  title =        "{Montgomery} curve arithmetic revisited",
  journal =      j-J-CRYPTO-ENG,
  volume =       "14",
  number =       "2",
  pages =        "343--362",
  month =        jun,
  year =         "2024",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-024-00353-5",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Thu Aug 8 07:34:12 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  note =         "See \cite{Montgomery:1987:SPE}.",
  URL =          "https://link.springer.com/article/10.1007/s13389-024-00353-5",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Crypto. Eng.",
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Laudadio:2024:CIE
author: Teresa Laudadio and Nicola Mastronardi and Donatella Occorsio
title: Computing integrals with an exponential weight on the real axis in floating point arithmetic
journal: j-APPL-NUM-MATH
volume: 200
pages: 309--317
month: jun
monthnumber: 6
year: 2024
CODEN: ANMAEL
DOI: https://doi.org/10.1016/j.apnum.2023.05.025
ISSN: 0168-9274 (print), 1873-5460 (electronic) OR 01689274 (print), 18735460 (electronic)
ISSNL: 0168-9274 OR 01689274
bibdate: Thu Apr 11 08:18:17 MDT 2024
bibtimestamp: 2024.04.11 08:18:17 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0168927423001551
fjournal: Applied Numerical Mathematics: Transactions of IMACS
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/01689274
rawauthor: Teresa Laudadio and Nicola Mastronardi and Donatella Occorsio
rawtitle: Computing integrals with an exponential weight on the real axis in floating point arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/applnummath.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Laudadio:2024:CIE,
  author =       "Teresa Laudadio and Nicola Mastronardi and Donatella
                 Occorsio",
  title =        "Computing integrals with an exponential weight on the
                 real axis in floating point arithmetic",
  journal =      j-APPL-NUM-MATH,
  volume =       "200",
  number =       "??",
  pages =        "309--317",
  month =        jun,
  year =         "2024",
  CODEN =        "ANMAEL",
  DOI =          "https://doi.org/10.1016/j.apnum.2023.05.025",
  ISSN =         "0168-9274 (print), 1873-5460 (electronic)",
  ISSN-L =       "0168-9274",
  bibdate =      "Thu Apr 11 08:18:17 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/applnummath.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0168927423001551",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Numerical Mathematics: Transactions of IMACS",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01689274",
}


bibtype: misc
filename: fparith.bib
label: Lefevre:2024:TMF
author: Vincent Lefevre
title: Test of Mathematical Functions of the Standard C Library
pages: 309--317
day: 27
month: sep
monthnumber: 9
year: 2024
bibdate: Mon Oct 21 11:32:37 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.10.21 11:32:37 ???
URL: https://www.vinc17.net/research/testlibm/; https://www.vinc17.net/research/testlibm/hrcases/
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Vincent Lef{\`e}vre
rawtitle: Test of Mathematical Functions of the {Standard C Library}
remark:
Contains link to collection of data files with worst-case (or hard-to-round) arguments for common elementary functions. See also cite Lefevre:2003:WCC.

entry:
@Misc{Lefevre:2024:TMF,
  author =       "Vincent Lef{\`e}vre",
  title =        "Test of Mathematical Functions of the {Standard C
                 Library}",
  howpublished = "Web site.",
  day =          "27",
  month =        sep,
  year =         "2024",
  bibdate =      "Mon Oct 21 11:32:37 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.vinc17.net/research/testlibm/;
                 https://www.vinc17.net/research/testlibm/hrcases/",
  acknowledgement = ack-nhfb,
  remark =       "Contains link to collection of data files with
                 worst-case (or hard-to-round) arguments for common
                 elementary functions. See also
                 \cite{Lefevre:2003:WCC}.",
}


bibtype: article
filename: fparith.bib
label: Lemire:2024:ESP
author: Daniel Lemire
title: Exact Short Products From Truncated Multipliers
journal: j-COMP-J
volume: 67
number: 4
pages: 1514--1520
month: apr
monthnumber: 4
year: 2024
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxad077
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Fri Apr 26 12:13:08 MDT 2024
bibtimestamp: 2024.04.26 12:13:08 MDT
URL: http://academic.oup.com/comjnl/article/67/4/1514/7306807; https://arxiv.org/abs/2303.14321v1
fjournal: Computer Journal
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: Daniel Lemire
rawtitle: Exact Short Products From Truncated Multipliers
bibsource:
https://www.math.utah.edu/pub/tex/bib/compj2020.bib; https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We sometimes need to compute the most significant digits of the product of small integers with a multiplier requiring much storage: e.g., a large integer (e.g., $ 5^100 $) or an irrational number ($ pi $). We only need to access the most significant digits of the multiplier --- as long as the integers are sufficiently small. We provide an efficient algorithm to compute the range of integers given a truncated multiplier and a desired number of digits.

rawabstract:
We sometimes need to compute the most significant digits of the product of small integers with a multiplier requiring much storage: e.g., a large integer (e.g., $ 5^{100} $) or an irrational number ($ \pi $). We only need to access the most significant digits of the multiplier --- as long as the integers are sufficiently small. We provide an efficient algorithm to compute the range of integers given a truncated multiplier and a desired number of digits.

entry:
@Article{Lemire:2024:ESP,
  author =       "Daniel Lemire",
  title =        "Exact Short Products From Truncated Multipliers",
  journal =      j-COMP-J,
  volume =       "67",
  number =       "4",
  pages =        "1514--1520",
  month =        apr,
  year =         "2024",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxad077",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Fri Apr 26 12:13:08 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compj2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://academic.oup.com/comjnl/article/67/4/1514/7306807;
                 https://arxiv.org/abs/2303.14321v1",
  abstract =     "We sometimes need to compute the most significant
                 digits of the product of small integers with a
                 multiplier requiring much storage: e.g., a large
                 integer (e.g., $ 5^{100} $) or an irrational number ($
                 \pi $). We only need to access the most significant
                 digits of the multiplier --- as long as the integers
                 are sufficiently small. We provide an efficient
                 algorithm to compute the range of integers given a
                 truncated multiplier and a desired number of digits.",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
}


bibtype: article
filename: fparith.bib
label: Mackie:2024:RFM
author: Maximilien Mackie
title: Recursion-free modular arithmetic in the lambda-calculus
journal: j-INFO-PROC-LETT
volume: 183
pages: Article 106408
month: jan
monthnumber: 1
year: 2024
CODEN: IFPLAT
DOI: https://doi.org/10.1016/j.ipl.2023.106408
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Tue Sep 19 07:09:51 MDT 2023
bibtimestamp: 2023.09.19 07:09:51 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0020019023000510
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: Maximilien Mackie
rawtitle: Recursion-free modular arithmetic in the lambda-calculus
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/infoproc2020.bib

entry:
@Article{Mackie:2024:RFM,
  author =       "Maximilien Mackie",
  title =        "Recursion-free modular arithmetic in the
                 lambda-calculus",
  journal =      j-INFO-PROC-LETT,
  volume =       "183",
  number =       "??",
  pages =        "Article 106408",
  month =        jan,
  year =         "2024",
  CODEN =        "IFPLAT",
  DOI =          "https://doi.org/10.1016/j.ipl.2023.106408",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Tue Sep 19 07:09:51 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/infoproc2020.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0020019023000510",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: article
filename: fparith.bib
label: Mikaitis:2024:MMT
author: Mantas Mikaitis
title: Monotonicity of Multi-Term Floating-Point Adders
journal: j-IEEE-TRANS-COMPUT
pages: 1--13
year: 2024
CODEN: ITCOB4
DOI: https://doi.org/10.1109/tc.2024.3371783
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Mar 11 11:33:29 2024
bibtimestamp: 2024.03.11 11:33:29 ???
fjournal: IEEE Transactions on Computers
keywords: accurate floating-point summation
remark: Online on 11 March 2024, but not yet assigned to an issue.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Mantas Mikaitis
rawtitle: Monotonicity of Multi-Term Floating-Point Adders
entry:
@Article{Mikaitis:2024:MMT,
  author =       "Mantas Mikaitis",
  title =        "Monotonicity of Multi-Term Floating-Point Adders",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "??",
  number =       "??",
  pages =        "1--13",
  month =        "????",
  year =         "2024",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/tc.2024.3371783",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Mar 11 11:33:29 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "accurate floating-point summation",
  remark =       "Online on 11 March 2024, but not yet assigned to an
                 issue.",
}


bibtype: misc
filename: fparith.bib
label: Muller:2024:SNC
author: Jean-Michel Muller
title: Some notes on correct rounding of functions
pages: 31
day: 18
month: sep
monthnumber: 9
year: 2024
bibdate: Thu Sep 19 15:27:07 2024
bibtimestamp: 2024.09.19 15:27:07 ???
acknowledgement: ack-nhfb
howpublished: Attachment to STDS-754 mailing list
rawauthor: Jean-Michel Muller
rawtitle: Some notes on correct rounding of functions
entry:
@Misc{Muller:2024:SNC,
  author =       "Jean-Michel Muller",
  title =        "Some notes on correct rounding of functions",
  howpublished = "Attachment to STDS-754 mailing list",
  pages =        "31",
  day =          "18",
  month =        sep,
  year =         "2024",
  bibdate =      "Thu Sep 19 15:27:07 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Navimipour:2024:NSA
author: Nima Jafari Navimipour and Seyed-Sajad Ahmadpour and Senay Yalcin
title: A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots
journal: j-J-SUPERCOMPUTING
volume: 80
number: 1
pages: 395--412
month: jan
monthnumber: 1
year: 2024
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-023-05491-x
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Thu Feb 15 10:23:12 MST 2024
bibtimestamp: 2024.02.15 10:23:12 MST
URL: https://link.springer.com/article/10.1007/s11227-023-05491-x
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
ajournal: J. Supercomputing
journalURL: http://link.springer.com/journal/11227
rawauthor: Nima Jafari Navimipour and Seyed-Sajad Ahmadpour and Senay Yalcin
rawtitle: A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots
entry:
@Article{Navimipour:2024:NSA,
  author =       "Nima Jafari Navimipour and Seyed-Sajad Ahmadpour and
                 Senay Yalcin",
  title =        "A nano-scale arithmetic and logic unit using a
                 reversible logic and quantum-dots",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "80",
  number =       "1",
  pages =        "395--412",
  month =        jan,
  year =         "2024",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-023-05491-x",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Thu Feb 15 10:23:12 MST 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib",
  URL =          "https://link.springer.com/article/10.1007/s11227-023-05491-x",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Supercomputing",
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: article
filename: fparith.bib
label: Noyez:2024:MMS
author: Louis Noyez and Nadia El Mrabet and Olivier Potin and Pascal Veron
title: Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2
journal: j-TRETS
volume: 17
number: 1
pages: 9:1--9:??
month: mar
monthnumber: 3
year: 2024
DOI: https://doi.org/10.1145/3624571
ISSN: 1936-7406 (print), 1936-7414 (electronic) OR 19367406 (print), 19367414 (electronic)
ISSNL: 1936-7406 OR 19367406
bibdate: Wed Mar 20 07:25:09 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/trets.bib
bibtimestamp: 2024.03.20 07:25:09 MDT
URL: https://dl.acm.org/doi/10.1145/3624571
fjournal: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
acknowledgement: ack-nhfb
ajournal: ACM Trans. Reconfigurable Technol. Syst.
articleno: 9
journalURL: https://dl.acm.org/loi/trets
rawauthor: Louis Noyez and Nadia {El Mrabet} and Olivier Potin and Pascal Veron
rawtitle: {Montgomery} Multiplication Scalable Systolic Designs Optimized for {DSP48E2}
abstract:
This article describes an extensive study of the use of DSP48E2 Slices in Ultrascale FPGAs to design hardware versions of the Montgomery Multiplication algorithm for the hardware acceleration of modular multiplications. Our fully scalable systolic ldots 

rawabstract:
This article describes an extensive study of the use of DSP48E2 Slices in Ultrascale FPGAs to design hardware versions of the Montgomery Multiplication algorithm for the hardware acceleration of modular multiplications. Our fully scalable systolic \ldots{}

entry:
@Article{Noyez:2024:MMS,
  author =       "Louis Noyez and Nadia {El Mrabet} and Olivier Potin
                 and Pascal Veron",
  title =        "{Montgomery} Multiplication Scalable Systolic Designs
                 Optimized for {DSP48E2}",
  journal =      j-TRETS,
  volume =       "17",
  number =       "1",
  pages =        "9:1--9:??",
  month =        mar,
  year =         "2024",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3624571",
  ISSN =         "1936-7406 (print), 1936-7414 (electronic)",
  ISSN-L =       "1936-7406",
  bibdate =      "Wed Mar 20 07:25:09 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/trets.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3624571",
  abstract =     "This article describes an extensive study of the use
                 of DSP48E2 Slices in Ultrascale FPGAs to design
                 hardware versions of the Montgomery Multiplication
                 algorithm for the hardware acceleration of modular
                 multiplications. Our fully scalable systolic \ldots{}",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Reconfigurable Technol. Syst.",
  articleno =    "9",
  fjournal =     "ACM Transactions on Reconfigurable Technology and
                 Systems (TRETS)",
  journal-URL =  "https://dl.acm.org/loi/trets",
}


bibtype: manual
filename: fparith.bib
label: Oracle:2024:SLR
title: SQL Language Reference
organization: Oracle Corporation
publisher: pub-ORACLE
address: pub-ORACLE:adr
edition: 19c (E96310-27)
pages: 9:1--9:??
month: jul
monthnumber: 7
year: 2024
bibdate: Tue Sep 10 15:24:10 2024
bibtimestamp: 2024.09.10 15:24:10 ???
acknowledgement: ack-nhfb
rawtitle: {SQL} Language Reference
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sqlbooks.bib

note:
The Data Types section describes the (non-IEEE 754) decimal number encoding. The precision is about 39 decimal digits, with a nonzero range of [1e-130, 1e126).

URL:
https://docs.oracle.com/en/database/oracle/oracle-database/19/sqlrf/Data-Types.html#GUID-A3C0D836-BADB-44E5-A5D4-265BA5968483

rawnote:
The Data Types section describes the (non-IEEE 754) decimal number encoding. The precision is about 39 decimal digits, with a nonzero range of [1e-130, 1e126).

entry:
@Manual{Oracle:2024:SLR,
  title =        "{SQL} Language Reference",
  organization = "{Oracle Corporation}",
  publisher =    pub-ORACLE,
  address =      pub-ORACLE:adr,
  edition =      "19c (E96310-27)",
  month =        jul,
  year =         "2024",
  bibdate =      "Tue Sep 10 15:24:10 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sqlbooks.bib",
  note =         "The Data Types section describes the (non-IEEE 754)
                 decimal number encoding. The precision is about 39
                 decimal digits, with a nonzero range of [1e-130,
                 1e126).",
  URL =          "https://docs.oracle.com/en/database/oracle/oracle-database/19/sqlrf/Data-Types.html#GUID-A3C0D836-BADB-44E5-A5D4-265BA5968483",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Perez:2024:HAF
author: J. Ayuso Perez
title: Hardware Addition Over Finite Fields Based On Booth--Karatsuba Algorithm
journal: j-COMP-J
volume: 67
number: 8
pages: 2643--2666
month: aug
monthnumber: 8
year: 2024
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxae034
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Mon Aug 19 11:43:29 MDT 2024
bibtimestamp: 2024.08.19 11:43:29 MDT
URL: http://academic.oup.com/comjnl/article/67/8/2643/7667243
fjournal: Computer Journal
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: J. Ayuso Perez
rawtitle: Hardware Addition Over Finite Fields Based On {Booth--Karatsuba} Algorithm
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/compj2020.bib

entry:
@Article{Perez:2024:HAF,
  author =       "J. Ayuso Perez",
  title =        "Hardware Addition Over Finite Fields Based On
                 {Booth--Karatsuba} Algorithm",
  journal =      j-COMP-J,
  volume =       "67",
  number =       "8",
  pages =        "2643--2666",
  month =        aug,
  year =         "2024",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxae034",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Mon Aug 19 11:43:29 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/compj2020.bib",
  URL =          "http://academic.oup.com/comjnl/article/67/8/2643/7667243",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
}


bibtype: article
filename: fparith.bib
label: Rashidi:2024:AFE
author: Bahram Rashidi
title: APPAs: fast and efficient approximate parallel prefix adders and multipliers
journal: j-J-SUPERCOMPUTING
volume: 80
number: 16
pages: 24269--24296
month: nov
monthnumber: 11
year: 2024
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-024-06356-7
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Thu Aug 22 13:34:29 MDT 2024
bibtimestamp: 2024.08.22 13:34:29 MDT
URL: https://link.springer.com/article/10.1007/s11227-024-06356-7
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
ajournal: J. Supercomputing
journalURL: http://link.springer.com/journal/11227
rawauthor: Bahram Rashidi
rawtitle: {APPAs}: fast and efficient approximate parallel prefix adders and multipliers
entry:
@Article{Rashidi:2024:AFE,
  author =       "Bahram Rashidi",
  title =        "{APPAs}: fast and efficient approximate parallel
                 prefix adders and multipliers",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "80",
  number =       "16",
  pages =        "24269--24296",
  month =        nov,
  year =         "2024",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-024-06356-7",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Thu Aug 22 13:34:29 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib",
  URL =          "https://link.springer.com/article/10.1007/s11227-024-06356-7",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Supercomputing",
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: article
filename: fparith.bib
label: Sahoo:2024:ADF
author: Siva Satyendra Sahoo and Salim Ullah and Akash Kumar
title: AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming
journal: j-TRETS
volume: 17
number: 2
pages: 31:1--31:??
month: jun
monthnumber: 6
year: 2024
DOI: https://doi.org/10.1145/3648694
ISSN: 1936-7406 (print), 1936-7414 (electronic) OR 19367406 (print), 19367414 (electronic)
ISSNL: 1936-7406 OR 19367406
bibdate: Tue Jun 4 06:09:07 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/trets.bib
bibtimestamp: 2024.06.04 06:09:07 MDT
URL: https://dl.acm.org/doi/10.1145/3648694
fjournal: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
acknowledgement: ack-nhfb
ajournal: ACM Trans. Reconfigurable Technol. Syst.
articleno: 31
journalURL: https://dl.acm.org/loi/trets
rawauthor: Siva Satyendra Sahoo and Salim Ullah and Akash Kumar
rawtitle: {AxOMaP}: Designing {FPGA}-based Approximate Arithmetic Operators using Mathematical Programming
abstract:
With the increasing application of machine learning (ML) algorithms in embedded systems, there is a rising necessity to design low-cost computer arithmetic for these resource-constrained systems. As a result, emerging models of computation, such as approximate and stochastic computing, that leverage the inherent error-resilience of such algorithms are being actively explored for implementing ML inference on resource-constrained systems. Approximate computing (AxC) aims to provide disproportionate gains in the power, performance, and area (PPA) of an application by allowing some level of reduction in its behavioral accuracy (BEHAV). Using approximate operators (AxOs) for computer arithmetic forms one of the more prevalent methods of implementing AxC. AxOs provide the additional scope for finer granularity of optimization, compared to only precision scaling of computer arithmetic. To this end, the design of platform-specific and cost-efficient approximate operators forms an important research goal. Recently, multiple works have reported the use of AI / ML-based approaches for synthesizing novel FPGA-based AxOs. However, most of such works limit the use of AI/ML to designing ML-based surrogate functions that are used during iterative optimization processes. To this end, we propose a novel data analysis-driven mathematical programming-based approach to synthesizing approximate operators for FPGAs. Specifically, we formulate mixed integer quadratically constrained programs based on the results of correlation analysis of the characterization data and use the solutions to enable a more directed search approach for evolutionary optimization algorithms. Compared to traditional evolutionary algorithms-based optimization, we report up to 21% improvement in the hypervolume, for joint optimization of PPA and BEHAV, in the design of signed 8-bit multipliers. Further, we report up to 27% better hypervolume than other state-of-the-art approaches to DSE for FPGA-based application-specific AxOs.

rawabstract:
With the increasing application of machine learning (ML) algorithms in embedded systems, there is a rising necessity to design low-cost computer arithmetic for these resource-constrained systems. As a result, emerging models of computation, such as approximate and stochastic computing, that leverage the inherent error-resilience of such algorithms are being actively explored for implementing ML inference on resource-constrained systems. Approximate computing (AxC) aims to provide disproportionate gains in the power, performance, and area (PPA) of an application by allowing some level of reduction in its behavioral accuracy (BEHAV). Using approximate operators (AxOs) for computer arithmetic forms one of the more prevalent methods of implementing AxC. AxOs provide the additional scope for finer granularity of optimization, compared to only precision scaling of computer arithmetic. To this end, the design of platform-specific and cost-efficient approximate operators forms an important research goal. Recently, multiple works have reported the use of AI\slash ML-based approaches for synthesizing novel FPGA-based AxOs. However, most of such works limit the use of AI/ML to designing ML-based surrogate functions that are used during iterative optimization processes. To this end, we propose a novel data analysis-driven mathematical programming-based approach to synthesizing approximate operators for FPGAs. Specifically, we formulate mixed integer quadratically constrained programs based on the results of correlation analysis of the characterization data and use the solutions to enable a more directed search approach for evolutionary optimization algorithms. Compared to traditional evolutionary algorithms-based optimization, we report up to 21\% improvement in the hypervolume, for joint optimization of PPA and BEHAV, in the design of signed 8-bit multipliers. Further, we report up to 27\% better hypervolume than other state-of-the-art approaches to DSE for FPGA-based application-specific AxOs.

entry:
@Article{Sahoo:2024:ADF,
  author =       "Siva Satyendra Sahoo and Salim Ullah and Akash Kumar",
  title =        "{AxOMaP}: Designing {FPGA}-based Approximate
                 Arithmetic Operators using Mathematical Programming",
  journal =      j-TRETS,
  volume =       "17",
  number =       "2",
  pages =        "31:1--31:??",
  month =        jun,
  year =         "2024",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3648694",
  ISSN =         "1936-7406 (print), 1936-7414 (electronic)",
  ISSN-L =       "1936-7406",
  bibdate =      "Tue Jun 4 06:09:07 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/trets.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3648694",
  abstract =     "With the increasing application of machine learning
                 (ML) algorithms in embedded systems, there is a rising
                 necessity to design low-cost computer arithmetic for
                 these resource-constrained systems. As a result,
                 emerging models of computation, such as approximate and
                 stochastic computing, that leverage the inherent
                 error-resilience of such algorithms are being actively
                 explored for implementing ML inference on
                 resource-constrained systems. Approximate computing
                 (AxC) aims to provide disproportionate gains in the
                 power, performance, and area (PPA) of an application by
                 allowing some level of reduction in its behavioral
                 accuracy (BEHAV). Using approximate operators (AxOs)
                 for computer arithmetic forms one of the more prevalent
                 methods of implementing AxC. AxOs provide the
                 additional scope for finer granularity of optimization,
                 compared to only precision scaling of computer
                 arithmetic. To this end, the design of
                 platform-specific and cost-efficient approximate
                 operators forms an important research goal. Recently,
                 multiple works have reported the use of AI\slash
                 ML-based approaches for synthesizing novel FPGA-based
                 AxOs.  However, most of such works limit the use of
                 AI/ML to designing ML-based surrogate functions that
                 are used during iterative optimization processes. To
                 this end, we propose a novel data analysis-driven
                 mathematical programming-based approach to synthesizing
                 approximate operators for FPGAs. Specifically, we
                 formulate mixed integer quadratically constrained
                 programs based on the results of correlation analysis
                 of the characterization data and use the solutions to
                 enable a more directed search approach for evolutionary
                 optimization algorithms. Compared to traditional
                 evolutionary algorithms-based optimization, we report
                 up to 21\% improvement in the hypervolume, for joint
                 optimization of PPA and BEHAV, in the design of signed
                 8-bit multipliers. Further, we report up to 27\% better
                 hypervolume than other state-of-the-art approaches to
                 DSE for FPGA-based application-specific AxOs.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Reconfigurable Technol. Syst.",
  articleno =    "31",
  fjournal =     "ACM Transactions on Reconfigurable Technology and
                 Systems (TRETS)",
  journal-URL =  "https://dl.acm.org/loi/trets",
}


bibtype: article
filename: fparith.bib
label: Scott:2024:ABI
author: Jennifer Scott and Miroslav Tuma
title: Avoiding Breakdown in Incomplete Factorizations in Low Precision Arithmetic
journal: j-TOMS
volume: 50
number: 2
pages: 9:1--9:25
month: jun
monthnumber: 6
year: 2024
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3651155
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Tue Jul 2 07:51:57 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2024.07.02 07:51:57 MDT
URL: https://dl.acm.org/doi/10.1145/3651155
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
ajournal: ACM Trans. Math. Softw.
articleno: 9
journalURL: https://dl.acm.org/loi/toms
rawauthor: Jennifer Scott and Miroslav Tuma
rawtitle: Avoiding Breakdown in Incomplete Factorizations in Low Precision Arithmetic
abstract:
The emergence of low precision floating-point arithmetic in computer hardware has led to a resurgence of interest in the use of mixed precision numerical linear algebra. For linear systems of equations, there has been renewed enthusiasm for mixed precision variants of iterative refinement. We consider the iterative solution of large sparse systems using incomplete factorization preconditioners. The focus is on the robust computation of such preconditioners in half precision arithmetic and employing them to solve symmetric positive definite systems to higher precision accuracy; however, the proposed ideas can be applied more generally. Even for well-conditioned problems, incomplete factorizations can break down when small entries occur on the diagonal during the factorization. When using half precision arithmetic, overflows are an additional possible source of breakdown. We examine how breakdowns can be avoided and implement our strategies within new half precision Fortran sparse incomplete Cholesky factorization software. Results are reported for a range of problems from practical applications. These demonstrate that, even for highly ill-conditioned problems, half precision preconditioners can potentially replace double precision preconditioners, although unsurprisingly this may be at the cost of additional iterations of a Krylov solver.

rawabstract:
The emergence of low precision floating-point arithmetic in computer hardware has led to a resurgence of interest in the use of mixed precision numerical linear algebra. For linear systems of equations, there has been renewed enthusiasm for mixed precision variants of iterative refinement. We consider the iterative solution of large sparse systems using incomplete factorization preconditioners. The focus is on the robust computation of such preconditioners in half precision arithmetic and employing them to solve symmetric positive definite systems to higher precision accuracy; however, the proposed ideas can be applied more generally. Even for well-conditioned problems, incomplete factorizations can break down when small entries occur on the diagonal during the factorization. When using half precision arithmetic, overflows are an additional possible source of breakdown. We examine how breakdowns can be avoided and implement our strategies within new half precision Fortran sparse incomplete Cholesky factorization software. Results are reported for a range of problems from practical applications. These demonstrate that, even for highly ill-conditioned problems, half precision preconditioners can potentially replace double precision preconditioners, although unsurprisingly this may be at the cost of additional iterations of a Krylov solver.

entry:
@Article{Scott:2024:ABI,
  author =       "Jennifer Scott and Miroslav Tuma",
  title =        "Avoiding Breakdown in Incomplete Factorizations in Low
                 Precision Arithmetic",
  journal =      j-TOMS,
  volume =       "50",
  number =       "2",
  pages =        "9:1--9:25",
  month =        jun,
  year =         "2024",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3651155",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Tue Jul 2 07:51:57 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3651155",
  abstract =     "The emergence of low precision floating-point
                 arithmetic in computer hardware has led to a resurgence
                 of interest in the use of mixed precision numerical
                 linear algebra. For linear systems of equations, there
                 has been renewed enthusiasm for mixed precision
                 variants of iterative refinement. We consider the
                 iterative solution of large sparse systems using
                 incomplete factorization preconditioners. The focus is
                 on the robust computation of such preconditioners in
                 half precision arithmetic and employing them to solve
                 symmetric positive definite systems to higher precision
                 accuracy; however, the proposed ideas can be applied
                 more generally. Even for well-conditioned problems,
                 incomplete factorizations can break down when small
                 entries occur on the diagonal during the factorization.
                 When using half precision arithmetic, overflows are an
                 additional possible source of breakdown. We examine how
                 breakdowns can be avoided and implement our strategies
                 within new half precision Fortran sparse incomplete
                 Cholesky factorization software. Results are reported
                 for a range of problems from practical applications.
                 These demonstrate that, even for highly ill-conditioned
                 problems, half precision preconditioners can
                 potentially replace double precision preconditioners,
                 although unsurprisingly this may be at the cost of
                 additional iterations of a Krylov solver.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Math. Softw.",
  articleno =    "9",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Tosini:2024:AEI
author: Marcelo Tosini and Martin Vazquez and Lucas Leiva
journal: j-J-SUPERCOMPUTING
volume: 80
number: 7
pages: 9298--9326
month: may
monthnumber: 5
year: 2024
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-023-05808-w
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Fri Apr 19 06:28:17 MDT 2024
bibtimestamp: 2024.04.19 06:28:17 MDT
URL: https://link.springer.com/article/10.1007/s11227-023-05808-w
fjournal: The Journal of Supercomputing
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
ajournal: J. Supercomputing
journalURL: http://link.springer.com/journal/11227
rawauthor: Marcelo Tosini and Mart{\'\i}n V{\'a}zquez and Lucas Leiva
title:
Analysis and efficient implementation of IEEE-754 decimal floating point adders / subtractors in FPGAs for DPD and BID encoding

rawtitle:
Analysis and efficient implementation of {IEEE-754} decimal floating point adders\slash subtractors in {FPGAs} for {DPD} and {BID} encoding

entry:
@Article{Tosini:2024:AEI,
  author =       "Marcelo Tosini and Mart{\'\i}n V{\'a}zquez and Lucas
                 Leiva",
  title =        "Analysis and efficient implementation of {IEEE-754}
                 decimal floating point adders\slash subtractors in
                 {FPGAs} for {DPD} and {BID} encoding",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "80",
  number =       "7",
  pages =        "9298--9326",
  month =        may,
  year =         "2024",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-023-05808-w",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Fri Apr 19 06:28:17 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib",
  URL =          "https://link.springer.com/article/10.1007/s11227-023-05808-w",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Supercomputing",
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Wu:2024:SAM
title: A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits
journal: j-TODAES
volume: 29
number: 1
pages: 23:1--23:??
month: jan
monthnumber: 1
year: 2024
CODEN: ATASFO
DOI: https://doi.org/10.1145/3610291
ISSN: 1084-4309 (print), 1557-7309 (electronic) OR 10844309 (print), 15577309 (electronic)
ISSNL: 1084-4309 OR 10844309
bibdate: Mon Jan 15 11:14:18 MST 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/todaes.bib
bibtimestamp: 2024.01.15 11:14:18 MST
URL: https://dl.acm.org/doi/10.1145/3610291
fjournal: ACM Transactions on Design Automation of Electronic Systems
acknowledgement: ack-nhfb
ajournal: ACM Transact. Des. Automat. Electron. Syst.
articleno: 23
journalURL: https://dl.acm.org/loi/todaes
rawtitle: A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits
author:
Ying Wu and Chuangtao Chen and Weihua Xiao and Xuan Wang and Chenyi Wen and Jie Han and Xunzhao Yin and Weikang Qian and Cheng Zhuo

abstract:
Given the stringent requirements of energy efficiency for Internet-of-Things edge devices, approximate multipliers, as a basic component of many processors and accelerators, have been constantly proposed and studied for decades, especially in error-resilient applications. The computation error and energy efficiency largely depend on how and where the approximation is introduced into a design. Thus, this article aims to provide a comprehensive review of the approximation techniques in multiplier designs ranging from algorithms and architectures to circuits. We have implemented representative approximate multiplier designs in each category to understand the impact of the design techniques on accuracy and efficiency. The designs can then be effectively deployed in high-level applications, such as machine learning, to gain energy efficiency at the cost of slight accuracy loss.

rawabstract:
Given the stringent requirements of energy efficiency for Internet-of-Things edge devices, approximate multipliers, as a basic component of many processors and accelerators, have been constantly proposed and studied for decades, especially in error-resilient applications. The computation error and energy efficiency largely depend on how and where the approximation is introduced into a design. Thus, this article aims to provide a comprehensive review of the approximation techniques in multiplier designs ranging from algorithms and architectures to circuits. We have implemented representative approximate multiplier designs in each category to understand the impact of the design techniques on accuracy and efficiency. The designs can then be effectively deployed in high-level applications, such as machine learning, to gain energy efficiency at the cost of slight accuracy loss.

rawauthor:
Ying Wu and Chuangtao Chen and Weihua Xiao and Xuan Wang and Chenyi Wen and Jie Han and Xunzhao Yin and Weikang Qian and Cheng Zhuo

entry:
@Article{Wu:2024:SAM,
  author =       "Ying Wu and Chuangtao Chen and Weihua Xiao and Xuan
                 Wang and Chenyi Wen and Jie Han and Xunzhao Yin and
                 Weikang Qian and Cheng Zhuo",
  title =        "A Survey on Approximate Multiplier Designs for Energy
                 Efficiency: From Algorithms to Circuits",
  journal =      j-TODAES,
  volume =       "29",
  number =       "1",
  pages =        "23:1--23:??",
  month =        jan,
  year =         "2024",
  CODEN =        "ATASFO",
  DOI =          "https://doi.org/10.1145/3610291",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Mon Jan 15 11:14:18 MST 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/todaes.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3610291",
  abstract =     "Given the stringent requirements of energy efficiency
                 for Internet-of-Things edge devices, approximate
                 multipliers, as a basic component of many processors
                 and accelerators, have been constantly proposed and
                 studied for decades, especially in error-resilient
                 applications. The computation error and energy
                 efficiency largely depend on how and where the
                 approximation is introduced into a design. Thus, this
                 article aims to provide a comprehensive review of the
                 approximation techniques in multiplier designs ranging
                 from algorithms and architectures to circuits. We have
                 implemented representative approximate multiplier
                 designs in each category to understand the impact of
                 the design techniques on accuracy and efficiency. The
                 designs can then be effectively deployed in high-level
                 applications, such as machine learning, to gain energy
                 efficiency at the cost of slight accuracy loss.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Transact. Des. Automat. Electron. Syst.",
  articleno =    "23",
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems",
  journal-URL =  "https://dl.acm.org/loi/todaes",
}


bibtype: article
filename: fparith.bib
label: Xie:2024:FRO
author: Peichen Xie and Yanjie Gao and Jilong Xue
title: FPRev: Revealing the Order of Floating-Point Summation by Numerical Testing
journal: arXiv.org
pages: 1--20
day: 1
month: nov
monthnumber: 11
year: 2024
bibdate: Tue Jan 28 06:36:44 2025
bibtimestamp: 2025.01.28 06:36:44 ???
URL: https://arxiv.org/abs/2411.00442v1
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
rawauthor: Peichen Xie and Yanjie Gao and Jilong Xue
rawtitle: {FPRev}: Revealing the Order of Floating-Point Summation by Numerical Testing
abstract:
The order of floating-point summation is a key factor in numerical reproducibility. However, this critical information is generally unspecified and unknown for most summation-based functions in numerical libraries, making it challenging to migrate them to new environments reproducibly. This paper presents novel, non-intrusive, testing-based algorithms that can reveal the order of floating-point summation by treating functions as callable black boxes. By constructing well-designed input that can cause the swamping phenomenon of floating-point addition, we can infer the order of summation from the output. We introduce FPRev, a tool that implements these algorithms, and validate its efficiency through extensive experiments with popular numerical libraries on various CPUs and GPUs (including those with Tensor Cores). FPRev reveals the varying summation orders across different libraries and devices, and outperforms other methods in terms of time complexity. The source code of FPRev is at this article's URL.

rawabstract:
The order of floating-point summation is a key factor in numerical reproducibility. However, this critical information is generally unspecified and unknown for most summation-based functions in numerical libraries, making it challenging to migrate them to new environments reproducibly. This paper presents novel, non-intrusive, testing-based algorithms that can reveal the order of floating-point summation by treating functions as callable black boxes. By constructing well-designed input that can cause the swamping phenomenon of floating-point addition, we can infer the order of summation from the output. We introduce FPRev, a tool that implements these algorithms, and validate its efficiency through extensive experiments with popular numerical libraries on various CPUs and GPUs (including those with Tensor Cores). FPRev reveals the varying summation orders across different libraries and devices, and outperforms other methods in terms of time complexity. The source code of FPRev is at this article's URL.

entry:
@Article{Xie:2024:FRO,
  author =       "Peichen Xie and Yanjie Gao and Jilong Xue",
  title =        "{FPRev}: Revealing the Order of Floating-Point
                 Summation by Numerical Testing",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--20",
  day =          "1",
  month =        nov,
  year =         "2024",
  bibdate =      "Tue Jan 28 06:36:44 2025",
  URL =          "https://arxiv.org/abs/2411.00442v1",
  abstract =     "The order of floating-point summation is a key factor
                 in numerical reproducibility. However, this critical
                 information is generally unspecified and unknown for
                 most summation-based functions in numerical libraries,
                 making it challenging to migrate them to new
                 environments reproducibly. This paper presents novel,
                 non-intrusive, testing-based algorithms that can reveal
                 the order of floating-point summation by treating
                 functions as callable black boxes. By constructing
                 well-designed input that can cause the swamping
                 phenomenon of floating-point addition, we can infer the
                 order of summation from the output. We introduce FPRev,
                 a tool that implements these algorithms, and validate
                 its efficiency through extensive experiments with
                 popular numerical libraries on various CPUs and GPUs
                 (including those with Tensor Cores). FPRev reveals the
                 varying summation orders across different libraries and
                 devices, and outperforms other methods in terms of time
                 complexity. The source code of FPRev is at this
                 article's URL.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation",
}


bibtype: article
filename: fparith.bib
label: Zhang:2024:HSA
author: Zuoyan Zhang and Jinchen Xu and Jiangwei Hao and Yang Qu and Haotian He and Bei Zhou
title: Hierarchical search algorithm for error detection in floating-point arithmetic expressions
journal: j-J-SUPERCOMPUTING
volume: 80
number: 1
pages: 1183--1205
month: jan
monthnumber: 1
year: 2024
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-023-05523-6
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Thu Feb 15 10:23:12 MST 2024
bibtimestamp: 2024.02.15 10:23:12 MST
URL: https://link.springer.com/article/10.1007/s11227-023-05523-6
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
ajournal: J. Supercomputing
journalURL: http://link.springer.com/journal/11227
rawauthor: Zuoyan Zhang and Jinchen Xu and Jiangwei Hao and Yang Qu and Haotian He and Bei Zhou
rawtitle: Hierarchical search algorithm for error detection in floating-point arithmetic expressions
entry:
@Article{Zhang:2024:HSA,
  author =       "Zuoyan Zhang and Jinchen Xu and Jiangwei Hao and Yang
                 Qu and Haotian He and Bei Zhou",
  title =        "Hierarchical search algorithm for error detection in
                 floating-point arithmetic expressions",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "80",
  number =       "1",
  pages =        "1183--1205",
  month =        jan,
  year =         "2024",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-023-05523-6",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Thu Feb 15 10:23:12 MST 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib",
  URL =          "https://link.springer.com/article/10.1007/s11227-023-05523-6",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Supercomputing",
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: techreport
filename: fparith.bib
label: Zimmermann:2024:NVD
author: Paul Zimmermann
title: Note on the Veltkamp / Dekker Algorithms with Directed Roundings
type: Report
number: hal-04480440
institution: Universite de Lorraine, CNRS, Inria, LORIA
address: Metz, France
pages: 1183--1205
day: 29
month: feb
monthnumber: 2
year: 2024
bibdate: Thu Aug 01 17:14:10 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.01 17:14:10 ???
URL: https://inria.hal.science/hal-04480440
keywords: CARAMBA --- Cryptology, arithmetic: algebraic methods for better algorithms
acknowledgement: ack-nhfb
rawauthor: Paul Zimmermann
rawtitle: Note on the {Veltkamp\slash Dekker} Algorithms with Directed Roundings
abstract:
The Veltkamp / Dekker algorithms are very useful for double-double arithmetic, when no fused multiply-add is available in hardware. Their analysis is well-known for rounding to nearest-even. We study how they behave with directed roundings in radix 2.

rawabstract:
The Veltkamp\slash Dekker algorithms are very useful for double-double arithmetic, when no fused multiply-add is available in hardware. Their analysis is well-known for rounding to nearest-even. We study how they behave with directed roundings in radix 2.

entry:
@TechReport{Zimmermann:2024:NVD,
  author =       "Paul Zimmermann",
  title =        "Note on the {Veltkamp\slash Dekker} Algorithms with
                 Directed Roundings",
  type =         "Report",
  number =       "hal-04480440",
  institution =  "Universit{\'e} de Lorraine, CNRS, Inria, LORIA",
  address =      "Metz, France",
  day =          "29",
  month =        feb,
  year =         "2024",
  bibdate =      "Thu Aug 01 17:14:10 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://inria.hal.science/hal-04480440",
  abstract =     "The Veltkamp\slash Dekker algorithms are very useful
                 for double-double arithmetic, when no fused
                 multiply-add is available in hardware. Their analysis
                 is well-known for rounding to nearest-even. We study
                 how they behave with directed roundings in radix 2.",
  acknowledgement = ack-nhfb,
  keywords =     "CARAMBA --- Cryptology, arithmetic: algebraic methods
                 for better algorithms",
}


bibtype: article
filename: fparith.bib
label: Zou:2024:PRE
author: Qinmeng Zou
title: Probabilistic Rounding Error Analysis of Modified Gram--Schmidt
journal: j-SIAM-J-MAT-ANA-APPL
volume: 45
number: 2
pages: 1076--1088
month: may
monthnumber: 5
year: 2024
CODEN: SJMAEL
DOI: https://doi.org/10.1137/23m1585817
ISSN: 0895-4798 (print), 1095-7162 (electronic) OR 08954798 (print), 10957162 (electronic)
ISSNL: 0895-4798 OR 08954798
bibdate: Fri May 31 08:23:04 2024
bibtimestamp: 2024.05.31 08:23:04 ???
fjournal: SIAM Journal on Matrix Analysis and Applications
acknowledgement: ack-nhfb
ajournal: SIAM J. Matrix Anal. Appl.
journalURL: http://epubs.siam.org/simax
rawauthor: Qinmeng Zou
rawtitle: Probabilistic Rounding Error Analysis of Modified {Gram--Schmidt}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjmatanaappl.bib

entry:
@Article{Zou:2024:PRE,
  author =       "Qinmeng Zou",
  title =        "Probabilistic Rounding Error Analysis of Modified
                 {Gram--Schmidt}",
  journal =      j-SIAM-J-MAT-ANA-APPL,
  volume =       "45",
  number =       "2",
  pages =        "1076--1088",
  month =        may,
  year =         "2024",
  CODEN =        "SJMAEL",
  DOI =          "https://doi.org/10.1137/23m1585817",
  ISSN =         "0895-4798 (print), 1095-7162 (electronic)",
  ISSN-L =       "0895-4798",
  bibdate =      "Fri May 31 08:23:04 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjmatanaappl.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "SIAM J. Matrix Anal. Appl.",
  fjournal =     "SIAM Journal on Matrix Analysis and Applications",
  journal-URL =  "http://epubs.siam.org/simax",
}


bibtype: article
filename: fparith.bib
label: Allred:2025:FNT
author: Taylor Allred and Xinyi Li and Ashton Wiersdorf and Ben Greenman and Ganesh Gopalakrishnan
title: FlowFPX: Nimble Tools for Debugging Floating-Point Exceptions
journal: Proceedings of the JuliaCon Conferences
volume: 7
number: 67
pages: 148:1--148:8
year: 2025
DOI: https://doi.org/10.21105/jcon.00148
bibdate: Wed Jan 22 13:56:37 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/julia.bib
bibtimestamp: 2025.01.22 13:56:37 ???
keywords: debugging; floating-point; Julia
acknowledgement: ack-nhfb
rawauthor: Taylor Allred and Xinyi Li and Ashton Wiersdorf and Ben Greenman and Ganesh Gopalakrishnan
rawtitle: {FlowFPX}: Nimble Tools for Debugging Floating-Point Exceptions
abstract:
Reliable numerical computations are central to scientific computing, but the floating-point arithmetic that enables large-scale models is error-prone. Numeric exceptions are a common occurrence and can propagate through code, leading to flawed results. This paper presents FlowFPX, a toolkit for systematically debugging floating-point exceptions by recording their flow, coalescing exception contexts, and fuzzing in select locations. These tools help scientists discover when exceptions happen and track down their origin, smoothing the way to a reliable codebase.

ORCID:
Allred, Taylor/0009-0000-7238-1816; Li, Xinyi/0009-0005-7276-7715; Wiersdorf, Ashton/0000-0001-5524-7930; Greenman, Ben/0000-0001-7078-9287; Gopalakrishnan, Ganesh/0000-0002-4161-9278

entry:
@Article{Allred:2025:FNT,
  author =       "Taylor Allred and Xinyi Li and Ashton Wiersdorf and
                 Ben Greenman and Ganesh Gopalakrishnan",
  title =        "{FlowFPX}: Nimble Tools for Debugging Floating-Point
                 Exceptions",
  journal =      "Proceedings of the {JuliaCon} Conferences",
  volume =       "7",
  number =       "67",
  pages =        "148:1--148:8",
  year =         "2025",
  DOI =          "https://doi.org/10.21105/jcon.00148",
  bibdate =      "Wed Jan 22 13:56:37 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/julia.bib",
  abstract =     "Reliable numerical computations are central to
                 scientific computing, but the floating-point arithmetic
                 that enables large-scale models is error-prone. Numeric
                 exceptions are a common occurrence and can propagate
                 through code, leading to flawed results. This paper
                 presents FlowFPX, a toolkit for systematically
                 debugging floating-point exceptions by recording their
                 flow, coalescing exception contexts, and fuzzing in
                 select locations. These tools help scientists discover
                 when exceptions happen and track down their origin,
                 smoothing the way to a reliable codebase.",
  acknowledgement = ack-nhfb,
  keywords =     "debugging; floating-point; Julia",
  ORCID-numbers = "Allred, Taylor/0009-0000-7238-1816; Li,
                 Xinyi/0009-0005-7276-7715; Wiersdorf,
                 Ashton/0000-0001-5524-7930; Greenman,
                 Ben/0000-0001-7078-9287; Gopalakrishnan,
                 Ganesh/0000-0002-4161-9278",
}


bibtype: article
filename: fparith.bib
label: Cui:2025:PES
author: Mengqi Cui and Jinchen Xu and Yuchang Zhou and Hongru Yang and Liguang Ji and Bei Zhou
title: PESA: error sensitivity analysis tool for floating-point computational programs
journal: j-J-SUPERCOMPUTING
volume: 81
number: 3
pages: ??--??
month: feb
monthnumber: 2
year: 2025
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-025-06962-z
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Wed Feb 19 09:44:27 MST 2025
bibtimestamp: 2025.02.19 09:44:27 MST
URL: https://link.springer.com/article/10.1007/s11227-025-06962-z
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
ajournal: J. Supercomputing
articleno: 477
journalURL: http://link.springer.com/journal/11227
rawauthor: Mengqi Cui and Jinchen Xu and Yuchang Zhou and Hongru Yang and Liguang Ji and Bei Zhou
rawtitle: {PESA}: error sensitivity analysis tool for floating-point computational programs
entry:
@Article{Cui:2025:PES,
  author =       "Mengqi Cui and Jinchen Xu and Yuchang Zhou and Hongru
                 Yang and Liguang Ji and Bei Zhou",
  title =        "{PESA}: error sensitivity analysis tool for
                 floating-point computational programs",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "81",
  number =       "3",
  pages =        "??--??",
  month =        feb,
  year =         "2025",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-025-06962-z",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Wed Feb 19 09:44:27 MST 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib",
  URL =          "https://link.springer.com/article/10.1007/s11227-025-06962-z",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Supercomputing",
  articleno =    "477",
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: misc
filename: fparith.bib
label: Darcy:2025:FJ
author: Joseph Darcy
title: Float16.java
pages: ??--??
year: 2025
bibdate: Mon Mar 10 13:45:31 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.03.10 13:45:31 ???
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Joseph Darcy
rawtitle: Float16.java
URL:
https://github.com/openjdk/jdk/blob/dbdbbd473061d7e8077ed07ccc6b03065a8c2ffc/src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Float16.java#L1240

remark:
The code comments provide an informal analysis that Float16 fused multiply-add (FMA) can be correctly implemented in IEEE 754 Binary64 arithmetic, including for NaN, Infinity, and signed zero arguments.

entry:
@Misc{Darcy:2025:FJ,
  author =       "Joseph Darcy",
  title =        "Float16.java",
  howpublished = "Web site",
  year =         "2025",
  bibdate =      "Mon Mar 10 13:45:31 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://github.com/openjdk/jdk/blob/dbdbbd473061d7e8077ed07ccc6b03065a8c2ffc/src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Float16.java#L1240",
  acknowledgement = ack-nhfb,
  remark =       "The code comments provide an informal analysis that
                 Float16 fused multiply-add (FMA) can be correctly
                 implemented in IEEE 754 Binary64 arithmetic, including
                 for NaN, Infinity, and signed zero arguments.",
}


bibtype: techreport
filename: fparith.bib
label: Gladman:2025:AMF
author: Brian Gladman and Vincenzo Innocente and John Mather and Paul Zimmermann
title: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
pages: 27
day: 10
month: feb
monthnumber: 2
year: 2025
bibdate: Mon Feb 10 10:00:22 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.02.10 10:00:22 ???
URL: https://members.loria.fr/PZimmermann/papers/accuracy.pdf
acknowledgement: ack-nhfb
rawauthor: Brian Gladman and Vincenzo Innocente and John Mather and Paul Zimmermann
rawtitle: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
remark:
Tabular comparison of AMD, Apple, ARM, CUDA, FreeBSD, GNU, Intel, LLVM, Microsoft Musl, Newlib, OpenLibm, RadeonOpenCompute (ROCm), and RedHat -lm libraries for correct rounding, versus results from MPFR.

entry:
@TechReport{Gladman:2025:AMF,
  author =       "Brian Gladman and Vincenzo Innocente and John Mather
                 and Paul Zimmermann",
  title =        "Accuracy of Mathematical Functions in Single, Double,
                 Double Extended, and Quadruple Precision",
  institution =  "????",
  pages =        "27",
  day =          "10",
  month =        feb,
  year =         "2025",
  bibdate =      "Mon Feb 10 10:00:22 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://members.loria.fr/PZimmermann/papers/accuracy.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Tabular comparison of AMD, Apple, ARM, CUDA, FreeBSD,
                 GNU, Intel, LLVM, Microsoft Musl, Newlib, OpenLibm,
                 RadeonOpenCompute (ROCm), and RedHat -lm libraries for
                 correct rounding, versus results from MPFR.",
}


bibtype: article
filename: fparith.bib
label: Imbach:2025:FER
author: Remi Imbach and Guillaume Moroz
title: Fast evaluation and root finding for polynomials with floating-point coefficients
journal: j-J-SYMBOLIC-COMP
volume: 127
pages: ??--??
month: mar
monthnumber: 3
year: 2025
CODEN: JSYCEH
DOI: https://doi.org/10.1016/j.jsc.2024.102372
ISSN: 0747-7171 (print), 1095-855X (electronic) OR 07477171 (print), 1095855X (electronic)
ISSNL: 0747-7171 OR 07477171
bibdate: Fri Sep 6 08:44:41 MDT 2024
bibtimestamp: 2024.09.06 08:44:41 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0747717124000762
fjournal: Journal of Symbolic Computation
acknowledgement: ack-nhfb
articleno: 102372
journalURL: http://www.sciencedirect.com/science/journal/07477171
rawauthor: R{\'e}mi Imbach and Guillaume Moroz
rawtitle: Fast evaluation and root finding for polynomials with floating-point coefficients
entry:
@Article{Imbach:2025:FER,
  author =       "R{\'e}mi Imbach and Guillaume Moroz",
  title =        "Fast evaluation and root finding for polynomials with
                 floating-point coefficients",
  journal =      j-J-SYMBOLIC-COMP,
  volume =       "127",
  number =       "??",
  pages =        "??--??",
  month =        mar # "\slash " # apr,
  year =         "2025",
  CODEN =        "JSYCEH",
  DOI =          "https://doi.org/10.1016/j.jsc.2024.102372",
  ISSN =         "0747-7171 (print), 1095-855X (electronic)",
  ISSN-L =       "0747-7171",
  bibdate =      "Fri Sep 6 08:44:41 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsymcomp.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0747717124000762",
  acknowledgement = ack-nhfb,
  articleno =    "102372",
  fjournal =     "Journal of Symbolic Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07477171",
}


bibtype: article
filename: fparith.bib
label: Ma:2025:STF
author: Dongyu Ma and Zeyu Liang and Luming Yin and Hongliang Liang
title: Symbolic testing of floating-point bugs and exceptions
journal: j-J-SYST-SOFTW
volume: 219
pages: ??--??
month: jan
monthnumber: 1
year: 2025
CODEN: JSSODM
DOI: https://doi.org/10.1016/j.jss.2024.112226; https://doi.org/10.2139/ssrn.4797965
ISSN: 0164-1212 (print), 1873-1228 (electronic) OR 01641212 (print), 18731228 (electronic)
ISSNL: 0164-1212 OR 01641212
bibdate: Thu Nov 7 07:42:59 MST 2024
bibtimestamp: 2024.11.07 07:42:59 MST
fjournal: Journal of Systems and Software
acknowledgement: ack-nhfb
articleno: 112226
journalURL: http://www.sciencedirect.com/science/journal/01641212
rawauthor: Dongyu Ma and Zeyu Liang and Luming Yin and Hongliang Liang
rawtitle: Symbolic testing of floating-point bugs and exceptions
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jsystsoftw2020.bib

URL:
http://www.sciencedirect.com/science/article/pii/S016412122400270X; https://papers.ssrn.com/sol3/papers.cfm?abstract_id=4797965

keywords:
CVE (Common Vulnerabilities and Exposures) bug reports; floating-point arithmetic; GNU Scientific Library (GSL); interval arithmetic; LLVM/CLang compiler system; MuPDF (viewing and converting PDF (Portable Document Format) files); SoX (audio editing); symbolic execution

entry:
@Article{Ma:2025:STF,
  author =       "Dongyu Ma and Zeyu Liang and Luming Yin and Hongliang
                 Liang",
  title =        "Symbolic testing of floating-point bugs and
                 exceptions",
  journal =      j-J-SYST-SOFTW,
  volume =       "219",
  number =       "??",
  pages =        "??--??",
  month =        jan,
  year =         "2025",
  CODEN =        "JSSODM",
  DOI =          "https://doi.org/10.1016/j.jss.2024.112226;
                 https://doi.org/10.2139/ssrn.4797965",
  ISSN =         "0164-1212 (print), 1873-1228 (electronic)",
  ISSN-L =       "0164-1212",
  bibdate =      "Thu Nov 7 07:42:59 MST 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsystsoftw2020.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S016412122400270X;
                 https://papers.ssrn.com/sol3/papers.cfm?abstract_id=4797965",
  acknowledgement = ack-nhfb,
  articleno =    "112226",
  fjournal =     "Journal of Systems and Software",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01641212",
  keywords =     "CVE (Common Vulnerabilities and Exposures) bug
                 reports; floating-point arithmetic; GNU Scientific
                 Library (GSL); interval arithmetic; LLVM/CLang compiler
                 system; MuPDF (viewing and converting PDF (Portable
                 Document Format) files); SoX (audio editing); symbolic
                 execution",
}


bibtype: article
filename: fparith.bib
label: Rathor:2025:AFE
author: Mahendra Rathor
title: ALOHA-FP2I: Efficient Algorithms and Hardware for Multi-Mode Rounding of Floating Point to Integer
journal: j-TECS
volume: 24
number: 1
pages: 12:1--12:26
month: jan
monthnumber: 1
year: 2025
DOI: https://doi.org/10.1145/3701560
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Thu Jan 2 07:31:47 MST 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tecs.bib
bibtimestamp: 2025.01.02 07:31:47 MST
URL: https://dl.acm.org/doi/10.1145/3701560
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
ajournal: ACM Trans. Embed. Comput. Syst.
articleno: 12
journalURL: https://dl.acm.org/loi/tecs
rawauthor: Mahendra Rathor
abstract:
Modern technology is relying on hardware accelerators to achieve enhanced performance of computing systems. In the modern computing paradigm, floating point representation of numbers has gained popularity owing to its wide dynamic range. Rounding of floating point numbers to integer is used in modern processor architectures e.g., ARM and Intel's architecture (IA) as well as in specific applications such as multimedia. However, the academic literature lacks discussion on hardware designs for rounding binary floating point numbers to integer in different rounding modes. This article presents novel efficient algorithms and hardware architecture designs for rounding binary floating point numbers to the integer for the following rounding modes: round towards zero, round up (towards positive infinity), round down (towards negative infinity), round to the nearest integer, and round to nearest even. The article also proposes an integrated multi-mode rounding (IMR) algorithm and hardware design which can be configured to a specific rounding mode among the above-mentioned five modes. This article proposes a mantissa bit of rounding (MBR) to determine the condition of rounding for the various modes. The MBR is identified on the basis of the dynamic range and precision features of floating point representation. To the best of our knowledge, we present the individual as well as an integrated hardware design for the various rounding modes for the first time in the literature. The proposed designs have been implemented on an FPGA platform to analyze the design metrics such as area, delay, and power. The results imply that the proposed designs are suitable to aid the intended hardware accelerators as they are efficient in terms of the design parameters. Moreover, this article presents the integration of the proposed rounding hardware design with the compression processor and evaluates the integration overhead which is found to be nominal (<1%).

rawabstract:
Modern technology is relying on hardware accelerators to achieve enhanced performance of computing systems. In the modern computing paradigm, floating point representation of numbers has gained popularity owing to its wide dynamic range. Rounding of floating point numbers to integer is used in modern processor architectures e.g., ARM and Intel's architecture (IA) as well as in specific applications such as multimedia. However, the academic literature lacks discussion on hardware designs for rounding binary floating point numbers to integer in different rounding modes. This article presents novel efficient algorithms and hardware architecture designs for rounding binary floating point numbers to the integer for the following rounding modes: round towards zero, round up (towards positive infinity), round down (towards negative infinity), round to the nearest integer, and round to nearest even. The article also proposes an integrated multi-mode rounding (IMR) algorithm and hardware design which can be configured to a specific rounding mode among the above-mentioned five modes. This article proposes a mantissa bit of rounding (MBR) to determine the condition of rounding for the various modes. The MBR is identified on the basis of the dynamic range and precision features of floating point representation. To the best of our knowledge, we present the individual as well as an integrated hardware design for the various rounding modes for the first time in the literature. The proposed designs have been implemented on an FPGA platform to analyze the design metrics such as area, delay, and power. The results imply that the proposed designs are suitable to aid the intended hardware accelerators as they are efficient in terms of the design parameters. Moreover, this article presents the integration of the proposed rounding hardware design with the compression processor and evaluates the integration overhead which is found to be nominal (<1\%).

rawtitle:
{ALOHA-FP2I}: Efficient Algorithms and Hardware for Multi-Mode Rounding of Floating Point to Integer

entry:
@Article{Rathor:2025:AFE,
  author =       "Mahendra Rathor",
  title =        "{ALOHA-FP2I}: Efficient Algorithms and Hardware for
                 Multi-Mode Rounding of Floating Point to Integer",
  journal =      j-TECS,
  volume =       "24",
  number =       "1",
  pages =        "12:1--12:26",
  month =        jan,
  year =         "2025",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3701560",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Thu Jan 2 07:31:47 MST 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3701560",
  abstract =     "Modern technology is relying on hardware accelerators
                 to achieve enhanced performance of computing systems.
                 In the modern computing paradigm, floating point
                 representation of numbers has gained popularity owing
                 to its wide dynamic range. Rounding of floating point
                 numbers to integer is used in modern processor
                 architectures e.g., ARM and Intel's architecture (IA)
                 as well as in specific applications such as multimedia.
                 However, the academic literature lacks discussion on
                 hardware designs for rounding binary floating point
                 numbers to integer in different rounding modes. This
                 article presents novel efficient algorithms and
                 hardware architecture designs for rounding binary
                 floating point numbers to the integer for the following
                 rounding modes: round towards zero, round up (towards
                 positive infinity), round down (towards negative
                 infinity), round to the nearest integer, and round to
                 nearest even. The article also proposes an integrated
                 multi-mode rounding (IMR) algorithm and hardware design
                 which can be configured to a specific rounding mode
                 among the above-mentioned five modes. This article
                 proposes a mantissa bit of rounding (MBR) to determine
                 the condition of rounding for the various modes. The
                 MBR is identified on the basis of the dynamic range and
                 precision features of floating point representation. To
                 the best of our knowledge, we present the individual as
                 well as an integrated hardware design for the various
                 rounding modes for the first time in the literature.
                 The proposed designs have been implemented on an FPGA
                 platform to analyze the design metrics such as area,
                 delay, and power. The results imply that the proposed
                 designs are suitable to aid the intended hardware
                 accelerators as they are efficient in terms of the
                 design parameters. Moreover, this article presents the
                 integration of the proposed rounding hardware design
                 with the compression processor and evaluates the
                 integration overhead which is found to be nominal
                 (<1\%).",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Embed. Comput. Syst.",
  articleno =    "12",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "https://dl.acm.org/loi/tecs",
}


bibtype: article
filename: fparith.bib
label: Wen:2025:PPW
author: Chenyi Wen and Haonan Du and Jiayi Wang and Zhengrui Chen and Li Zhang and Qi Sun and Cheng Zhuo
journal: j-TODAES
volume: 30
number: 2
pages: 21:1--21:??
month: mar
monthnumber: 3
year: 2025
CODEN: ATASFO
DOI: https://doi.org/10.1145/3706634
ISSN: 1084-4309 (print), 1557-7309 (electronic) OR 10844309 (print), 15577309 (electronic)
ISSNL: 1084-4309 OR 10844309
bibdate: Thu Feb 13 06:21:20 MST 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/todaes.bib
bibtimestamp: 2025.02.13 06:21:20 MST
URL: https://dl.acm.org/doi/10.1145/3706634
fjournal: ACM Transactions on Design Automation of Electronic Systems
acknowledgement: ack-nhfb
ajournal: ACM Transact. Des. Automat. Electron. Syst.
articleno: 21
journalURL: https://dl.acm.org/loi/todaes
rawauthor: Chenyi Wen and Haonan Du and Jiayi Wang and Zhengrui Chen and Li Zhang and Qi Sun and Cheng Zhuo
title:
PACE: a Piece-Wise Approximate Floating-Point Divider with Runtime Configurability and High Energy Efficiency

abstract:
Approximate computing emerges as a viable solution to enhance energy efficiency in applications sensitive to human perception, particularly on edge devices. This work introduces a novel piece-wise approximate floating-point divider that boasts resource ldots 

rawabstract:
Approximate computing emerges as a viable solution to enhance energy efficiency in applications sensitive to human perception, particularly on edge devices. This work introduces a novel piece-wise approximate floating-point divider that boasts resource \ldots{}

rawtitle:
{PACE}: a Piece-Wise Approximate Floating-Point Divider with Runtime Configurability and High Energy Efficiency

entry:
@Article{Wen:2025:PPW,
  author =       "Chenyi Wen and Haonan Du and Jiayi Wang and Zhengrui
                 Chen and Li Zhang and Qi Sun and Cheng Zhuo",
  title =        "{PACE}: a Piece-Wise Approximate Floating-Point
                 Divider with Runtime Configurability and High Energy
                 Efficiency",
  journal =      j-TODAES,
  volume =       "30",
  number =       "2",
  pages =        "21:1--21:??",
  month =        mar,
  year =         "2025",
  CODEN =        "ATASFO",
  DOI =          "https://doi.org/10.1145/3706634",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Thu Feb 13 06:21:20 MST 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/todaes.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3706634",
  abstract =     "Approximate computing emerges as a viable solution to
                 enhance energy efficiency in applications sensitive to
                 human perception, particularly on edge devices. This
                 work introduces a novel piece-wise approximate
                 floating-point divider that boasts resource \ldots{}",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Transact. Des. Automat. Electron. Syst.",
  articleno =    "21",
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems",
  journal-URL =  "https://dl.acm.org/loi/todaes",
}


bibtype: article
filename: fparith.bib
label: Zhao:2025:ISS
author: Gaoyang Zhao and Junzhong Shen and Rongzhen Lin and Hua Li and Yaohua Wang
title: ISOAcc: In-situ Shift Operation-based Accelerator For Efficient in-SRAM Multiplication
journal: j-TODAES
volume: 30
number: 2
pages: 22:1--22:??
month: mar
monthnumber: 3
year: 2025
CODEN: ATASFO
DOI: https://doi.org/10.1145/3707205
ISSN: 1084-4309 (print), 1557-7309 (electronic) OR 10844309 (print), 15577309 (electronic)
ISSNL: 1084-4309 OR 10844309
bibdate: Thu Feb 13 06:21:20 MST 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/todaes.bib
bibtimestamp: 2025.02.13 06:21:20 MST
URL: https://dl.acm.org/doi/10.1145/3707205
fjournal: ACM Transactions on Design Automation of Electronic Systems
acknowledgement: ack-nhfb
ajournal: ACM Transact. Des. Automat. Electron. Syst.
articleno: 22
journalURL: https://dl.acm.org/loi/todaes
rawauthor: Gaoyang Zhao and Junzhong Shen and Rongzhen Lin and Hua Li and Yaohua Wang
rawtitle: {ISOAcc}: In-situ Shift Operation-based Accelerator For Efficient in-{SRAM} Multiplication
abstract:
Digital SRAM-based CIM architectures must balance three critical factors: quantized neural network bitwidth, accuracy loss, and computational efficiency, each crucial to optimizing performance and efficiency. In Domain Specific Accelerators (DSAs), flexible and specific hardware design, when incorporated with tailored Power-of-2 (P-2) quantization schemes, addresses this issue. However, in CIMs, the absence of flexible and specific hardware to support dynamic switching between general and tailored quantization schemes hinders the adoption of efficient quantization methods. In this article, we propose the In-situ Shift Operation based Accelerator (ISOAcc) for efficient SRAM-based multiplication. The key idea is to introduce transmission gates near the SRAM array to enable the selection of bits from either the same or the neighbor line when data flows from one row to another. This functionally equals a shift operation. By configuring the transmission gates array in a cascade manner, ISOAcc can support 0 to 15-bit shift with a negligible overhead. The ISOAcc can directly leverage P-2 quantization schemes in hardware, thereby greatly reducing multiplication cycles. We have chosen five well-known neural networks to evaluate ISOAcc. The evaluations show that ISOAcc achieves an average performance improvement of 3.24 $ times $ and an energy reduction of 75%, compared with the state-of-the-art (SOTA) SRAM-based CIM design, Bit-Parallel.

rawabstract:
Digital SRAM-based CIM architectures must balance three critical factors: quantized neural network bitwidth, accuracy loss, and computational efficiency, each crucial to optimizing performance and efficiency. In Domain Specific Accelerators (DSAs), flexible and specific hardware design, when incorporated with tailored Power-of-2 (P-2) quantization schemes, addresses this issue. However, in CIMs, the absence of flexible and specific hardware to support dynamic switching between general and tailored quantization schemes hinders the adoption of efficient quantization methods. In this article, we propose the In-situ Shift Operation based Accelerator (ISOAcc) for efficient SRAM-based multiplication. The key idea is to introduce transmission gates near the SRAM array to enable the selection of bits from either the same or the neighbor line when data flows from one row to another. This functionally equals a shift operation. By configuring the transmission gates array in a cascade manner, ISOAcc can support 0 to 15-bit shift with a negligible overhead. The ISOAcc can directly leverage P-2 quantization schemes in hardware, thereby greatly reducing multiplication cycles. We have chosen five well-known neural networks to evaluate ISOAcc. The evaluations show that ISOAcc achieves an average performance improvement of 3.24 $ \times $ and an energy reduction of 75\%, compared with the state-of-the-art (SOTA) SRAM-based CIM design, Bit-Parallel.

entry:
@Article{Zhao:2025:ISS,
  author =       "Gaoyang Zhao and Junzhong Shen and Rongzhen Lin and
                 Hua Li and Yaohua Wang",
  title =        "{ISOAcc}: In-situ Shift Operation-based Accelerator
                 For Efficient in-{SRAM} Multiplication",
  journal =      j-TODAES,
  volume =       "30",
  number =       "2",
  pages =        "22:1--22:??",
  month =        mar,
  year =         "2025",
  CODEN =        "ATASFO",
  DOI =          "https://doi.org/10.1145/3707205",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Thu Feb 13 06:21:20 MST 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/todaes.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3707205",
  abstract =     "Digital SRAM-based CIM architectures must balance
                 three critical factors: quantized neural network
                 bitwidth, accuracy loss, and computational efficiency,
                 each crucial to optimizing performance and efficiency.
                 In Domain Specific Accelerators (DSAs), flexible and
                 specific hardware design, when incorporated with
                 tailored Power-of-2 (P-2) quantization schemes,
                 addresses this issue. However, in CIMs, the absence of
                 flexible and specific hardware to support dynamic
                 switching between general and tailored quantization
                 schemes hinders the adoption of efficient quantization
                 methods. In this article, we propose the In-situ Shift
                 Operation based Accelerator (ISOAcc) for efficient
                 SRAM-based multiplication. The key idea is to introduce
                 transmission gates near the SRAM array to enable the
                 selection of bits from either the same or the neighbor
                 line when data flows from one row to another. This
                 functionally equals a shift operation. By configuring
                 the transmission gates array in a cascade manner,
                 ISOAcc can support 0 to 15-bit shift with a negligible
                 overhead. The ISOAcc can directly leverage P-2
                 quantization schemes in hardware, thereby greatly
                 reducing multiplication cycles. We have chosen five
                 well-known neural networks to evaluate ISOAcc. The
                 evaluations show that ISOAcc achieves an average
                 performance improvement of 3.24 $ \times $ and an
                 energy reduction of 75\%, compared with the
                 state-of-the-art (SOTA) SRAM-based CIM design,
                 Bit-Parallel.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Transact. Des. Automat. Electron. Syst.",
  articleno =    "22",
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems",
  journal-URL =  "https://dl.acm.org/loi/todaes",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:20xx:CMP
author: Anonymous
title: The CORE-MATH project
pages: 22:1--22:??
year: 20xx
bibdate: Mon Dec 04 07:10:51 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.04 07:10:51 ???
URL: https://core-math.gitlabpages.inria.fr/
acknowledgement: ack-nhfb
howpublished: Web site and code archive
rawauthor: Anonymous
rawtitle: The {CORE-MATH} project
remark:
From the Web site: ``CORE-MATH Mission: provide on-the-shelf high performance open-source mathematical functions with correct rounding that can be integrated into current mathematical libraries (GNU libc, Intel Math Library, AMD Libm, Newlib, OpenLibm, Musl, Apple Libm, llvm-libc, Microsoft libm, CUDA libm, ROCm)''

entry:
@Misc{Anonymous:20xx:CMP,
  author =       "Anonymous",
  title =        "The {CORE-MATH} project",
  howpublished = "Web site and code archive",
  year =         "20xx",
  bibdate =      "Mon Dec 04 07:10:51 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://core-math.gitlabpages.inria.fr/",
  acknowledgement = ack-nhfb,
  remark =       "From the Web site: ``CORE-MATH Mission: provide
                 on-the-shelf high performance open-source mathematical
                 functions with correct rounding that can be integrated
                 into current mathematical libraries (GNU libc, Intel
                 Math Library, AMD Libm, Newlib, OpenLibm, Musl, Apple
                 Libm, llvm-libc, Microsoft libm, CUDA libm, ROCm)''",
}


bibtype: misc
filename: fparith.bib
label: QinetiQ:20xx:QFP
author: QinetiQ
title: Quixilica floating point cores
pages: 22:1--22:??
year: 20xx
bibdate: Sat Oct 9 12:58:32 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 12:58:32 ???
URL: http://www.tekmicro.com/
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: {QinetiQ}
rawtitle: {Quixilica} floating point cores
entry:
@Misc{QinetiQ:20xx:QFP,
  author =       "{QinetiQ}",
  title =        "{Quixilica} floating point cores",
  howpublished = "Web document",
  year =         "20xx",
  bibdate =      "Sat Oct 9 12:58:32 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.tekmicro.com/",
  acknowledgement = ack-nhfb,
}


bibtype: proceedings
filename: fparith.bib
label: Anonymous:1948:PSL
editor: Anonymous
volume: 16
publisher: pub-HARVARD
address: pub-HARVARD:adr
pages: xxix + 302
year: 1948
LCCN: QA75 .S96 1947
bibdate: Mon Nov 4 07:46:57 MST 2002
bibtimestamp: 2002.11.04 07:46:57 MST
series: The Annals of the Computation Laboratory of Harvard University
keywords: calculators --- congresses; electronic digital computers --- congresses
acknowledgement: ack-nhfb
raweditor: Anonymous
booktitle:
Proceedings of a Symposium on Large-Scale Digital Calculating Machinery: Jointly Sponsored by The Navy Department Bureau of Ordnance and Harvard University at The Computation Laboratory 7--10 January 1947

title:
Proceedings of a Symposium on Large-Scale Digital Calculating Machinery: Jointly Sponsored by The Navy Department Bureau of Ordnance and Harvard University at The Computation Laboratory 7--10 January 1947

bibsource:
https://www.math.utah.edu/pub/bibnet/authors/b/babbage-charles.bib; https://www.math.utah.edu/pub/tex/bib/adabooks.bib; https://www.math.utah.edu/pub/tex/bib/annhistcomput.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

remark:
Goldstine's paper is listed in the table of contents, but is absent from the volume. The printed order of a few papers differs from that shown in the table of contents; the order has been corrected in the data in this entry.

TOC:
Program of the Symposium on Large-Scale Digital Calculating Machinery: 7--10 January 1947 First Session: Tuesday, 7 January 1947 1O:00 a.m. Opening Addresses Mr. Edward Reynolds, Administrative Vice President of Harvard University / 3--3 Rear Admiral C. T. Joy, USN, Naval Proving Ground, Dahlgren, Virginia / 4--6 Professor Howard H. Aiken, Chairman, Harvard University / 7--7 11:00 a.m. Inspection of the Computation Laboratory and of Mark II Calculator Second Session: Tuesday, 7 January 1947, 2:00 p.m. Existing Calculating Machines / Professor Willard E. Bleick, Chairman, Post Graduate School, U.S. Naval Academy, Annapolis / Mr. Richard H. Babbage, Montreal, Canada / The Work of Charles Babbage / 13--22 Mr. Richard M. Bloch, Harvard University / Mark I Calculator / 23--30 Dr. Lewis P. Tabor, University of Pennsylvania / Brief Description and Operating Characteristics of the ENIAC / 31--40 Mr. Samuel B. Williams, Consulting Electrical Engineer / Bell Telephone Laboratories' Relay Computing System / 41--68 Mr. Robert V. D. Campbell, Harvard University / Mark II Calculator / 69--79 Third Session: Wednesday, 8 January 1947, 9:30 a.m. The Logic of Large-Scale Calculating Machinery / Professor Vendell H. Furry, Chairman, Harvard University Dr. Alexander W. Wundheiler, Bureau of Ordnance / Problems of Mathematical Analysis Involved in Machine Computations / 83--90 Dr. George R. Stibitz, University of Vermont / The Organization of Large-Scale Calculating Machinery / 91--100 Fourth Session: Wednesday, 8 January 1947, 2:00 p.m. Storage Devices Dr. John H. Curtiss, Chairman / National Bureau of Standards / Dr. T. Kite Sharpless, University of Pennsylvania / Mercury Delay Lines as a Memory Unit / 103--109 Professor Leon Brillouin, Harvard University / Slow Electromagnetic Waves / 110--124 Dr. Jay W. Forrester, Massachusetts Institute of Technology / High-Speed Electrostatic Storage / 125--129 Dr. Benjamin L. Moore, Harvard University / Magnetic and Phosphor Coated Discs / 130--132 Dr. Jan Rajchman, Radio Corporation of America / The Selectron --- A Tube for Selective Electrostatic Storage / 133--145 Dr. Arthur W. Tyler, Eastman Kodak Company / Optical and Photographic Storage Techniques / 146--150 Fifth Session: Thursday, 9 January 1947, 9:30 a.m. Numerical Methods and Suggested Problems for Solution Dr. Mina Rees, Chairman, Office of Naval Research Professor Richard Courant, New York University / Method of Finite Differences for the Solution of Partial Differential Equations / 153--156 Dr. Raymond J. Seeger, Naval Ordnance Laboratory / On Computational Techniques for Certain Problems in Fluid Dynamics / 157--168 Professor Wassily W. Leontief, Harvard University / Computational Problems Arising in Connection with Economic Analysis of interindustrial Relationships / 169--175 Professor Hans A. Rademacher, University of Pennsylvania / On the Accumulation of Errors in Processes of Integration on High-Speed Calculating Machines / 176--187 Professor Howard W. Emmons, Harvard University / Fluid Mechanics Computations / 188--193 Dr. L. S. Dederick, Ballistic Research Laboratory, Aberdeen, Maryland / Firing Tables / 194--199 Sixth Session: Thursday, 9 January 1947, 2:00 p.m. Sequencing, Coding, and Problem Preparation Dr. Julius A. Stratton, Chairman, Massachusetts Institute of Technology Dr. John W. Mauchly, Electronic Control Company / Preparation of Problems for EDVAC-Type Machines / 203--207 Mr. Joseph 0. Harrison, Jr., Harvard University / The Preparation of Problems for the Mark I Calculator / 208--210 Dr. Herman H. Goldstine, Institute for Advanced Study / Coding for Large-Scale Calculating Machinery / ??--?? Seventh Session: Friday, 10 January 1947, 9:30 a.m. Input and Output Devices Professor E. Leon Chaffee, Chairman, Harvard University Mr. Frederick G. Miller, Harvard University / Application of Printing Telegraph Techniques to Large-Scale Calculating Machinery / 213--222 Mr. Otto Kornei, The Brush Development Company / Survey of Magnetic Recording / 223--237 Mr. Harrison W. Fuller, Harvard University / The Numeroscope / 238--247 Dr. Samuel N. Alexander, National Bureau of Standards / Input and Output Devices for Electronic Digital Calculating Machinery / 248--253 Dr. Morris Rubinoff, Harvard University / An Input Device Using Multiple Gates / 254--259 Dr. R. D. O'Neal, Eastman Kodak Company / Photographic Methods of Handling Input and Output Data / 260--266 Mr. C. Bradford Sheppard, Electronic Control Company / Transfer Between External and Internal Memory / 267--273 Eighth Session: Friday, 10 January 1947, 2:00 p.m. Conclusions and Open Discussion Professor Charles C. Bramble, Chairman, Post Graduate School, U.S. Naval Academy, Annapolis / Professor Samuel H. Caldwell, Massachusetts Institute of Technology / Publication, Classification, and Patents / 277--283 Dr. Louis Couffignal (in absentia), Centre National de la Recherche Scientifique / Le Domaine du Calcul Mecanique / 284--296 Dr. Alan T. Waterman, Office of Naval Research / New Vistas in Mathematics / 298--302

rawbooktitle:
Proceedings of a {Symposium on Large-Scale Digital Calculating Machinery}: Jointly Sponsored by {The Navy Department Bureau of Ordnance and Harvard University at The Computation Laboratory 7--10 January 1947}

rawtitle:
Proceedings of a {Symposium on Large-Scale Digital Calculating Machinery}: Jointly Sponsored by {The Navy Department Bureau of Ordnance and Harvard University at The Computation Laboratory 7--10 January 1947}

rawTOC:
Program of the Symposium on Large-Scale Digital Calculating Machinery: 7--10 January 1947 \\ First Session: Tuesday, 7 January 1947 1O:00 a.m. \\ Opening Addresses \\ Mr. Edward Reynolds, Administrative Vice President of Harvard University / 3--3 \\ Rear Admiral C. T. Joy, USN, Naval Proving Ground, Dahlgren, Virginia / 4--6 \\ Professor Howard H. Aiken, Chairman, Harvard University / 7--7 \\ 11:00 a.m. Inspection of the Computation Laboratory and of Mark II Calculator \\ Second Session: Tuesday, 7 January 1947, 2:00 p.m. \\ Existing Calculating Machines / \\ Professor Willard E. Bleick, Chairman, Post Graduate School, U.S. Naval Academy, Annapolis / \\ Mr. Richard H. Babbage, Montreal, Canada / The Work of Charles Babbage / 13--22 \\ Mr. Richard M. Bloch, Harvard University / Mark I Calculator / 23--30 \\ Dr. Lewis P. Tabor, University of Pennsylvania / Brief Description and Operating Characteristics of the ENIAC / 31--40 \\ Mr. Samuel B. Williams, Consulting Electrical Engineer / Bell Telephone Laboratories' Relay Computing System / 41--68 \\ Mr. Robert V. D. Campbell, Harvard University / Mark II Calculator / 69--79 \\ Third Session: Wednesday, 8 January 1947, 9:30 a.m. \\ The Logic of Large-Scale Calculating Machinery / \\ Professor \Vendell H. Furry, Chairman, Harvard University \\ Dr. Alexander W. Wundheiler, Bureau of Ordnance / Problems of Mathematical Analysis Involved in Machine Computations / 83--90 \\ Dr. George R. Stibitz, University of Vermont / The Organization of Large-Scale Calculating Machinery / 91--100 \\ Fourth Session: Wednesday, 8 January 1947, 2:00 p.m. \\ Storage Devices \\ Dr. John H. Curtiss, Chairman / National Bureau of Standards / \\ Dr. T. Kite Sharpless, University of Pennsylvania / Mercury Delay Lines as a Memory Unit / 103--109 \\ Professor Leon Brillouin, Harvard University / Slow Electromagnetic Waves / 110--124 \\ Dr. Jay W. Forrester, Massachusetts Institute of Technology / High-Speed Electrostatic Storage / 125--129 \\ Dr. Benjamin L. Moore, Harvard University / Magnetic and Phosphor Coated Discs / 130--132 \\ Dr. Jan Rajchman, Radio Corporation of America / The Selectron --- A Tube for Selective Electrostatic Storage / 133--145 \\ Dr. Arthur W. Tyler, Eastman Kodak Company / Optical and Photographic Storage Techniques / 146--150 \\ Fifth Session: Thursday, 9 January 1947, 9:30 a.m. \\ Numerical Methods and Suggested Problems for Solution \\ Dr. Mina Rees, Chairman, Office of Naval Research \\ Professor Richard Courant, New York University / Method of Finite Differences for the Solution of Partial Differential Equations / 153--156 \\ Dr. Raymond J. Seeger, Naval Ordnance Laboratory / On Computational Techniques for Certain Problems in Fluid Dynamics / 157--168 \\ Professor Wassily W. Leontief, Harvard University / Computational Problems Arising in Connection with Economic Analysis of interindustrial Relationships / 169--175 \\ Professor Hans A. Rademacher, University of Pennsylvania / On the Accumulation of Errors in Processes of Integration on High-Speed Calculating Machines / 176--187 \\ Professor Howard W. Emmons, Harvard University / Fluid Mechanics Computations / 188--193 \\ Dr. L. S. Dederick, Ballistic Research Laboratory, Aberdeen, Maryland / Firing Tables / 194--199 \\ Sixth Session: Thursday, 9 January 1947, 2:00 p.m. \\ Sequencing, Coding, and Problem Preparation \\ Dr. Julius A. Stratton, Chairman, Massachusetts Institute of Technology \\ Dr. John W. Mauchly, Electronic Control Company / Preparation of Problems for EDVAC-Type Machines / 203--207 \\ Mr. Joseph 0. Harrison, Jr., Harvard University / The Preparation of Problems for the Mark I Calculator / 208--210 \\ Dr. Herman H. Goldstine, Institute for Advanced Study / Coding for Large-Scale Calculating Machinery / ??--?? \\ Seventh Session: Friday, 10 January 1947, 9:30 a.m. \\ Input and Output Devices \\ Professor E. Leon Chaffee, Chairman, Harvard University \\ Mr. Frederick G. Miller, Harvard University / Application of Printing Telegraph Techniques to Large-Scale Calculating Machinery / 213--222 \\ Mr. Otto Kornei, The Brush Development Company / Survey of Magnetic Recording / 223--237 \\ Mr. Harrison W. Fuller, Harvard University / The Numeroscope / 238--247 \\ Dr. Samuel N. Alexander, National Bureau of Standards / Input and Output Devices for Electronic Digital Calculating Machinery / 248--253 \\ Dr. Morris Rubinoff, Harvard University / An Input Device Using Multiple Gates / 254--259 \\ Dr. R. D. O'Neal, Eastman Kodak Company / Photographic Methods of Handling Input and Output Data / 260--266 \\ Mr. C. Bradford Sheppard, Electronic Control Company / Transfer Between External and Internal Memory / 267--273 \\ Eighth Session: Friday, 10 January 1947, 2:00 p.m. \\ Conclusions and Open Discussion \\ Professor Charles C. Bramble, Chairman, Post Graduate School, U.S. Naval Academy, Annapolis / \\ Professor Samuel H. Caldwell, Massachusetts Institute of Technology / Publication, Classification, and Patents / 277--283 \\ Dr. Louis Couffignal (in absentia), Centre National de la Recherche Scientifique / Le Domaine du Calcul M{\'e}canique / 284--296 \\ Dr. Alan T. Waterman, Office of Naval Research / New Vistas in Mathematics / 298--302

entry:
@Proceedings{Anonymous:1948:PSL,
  editor =       "Anonymous",
  booktitle =    "Proceedings of a {Symposium on Large-Scale Digital
                 Calculating Machinery}: Jointly Sponsored by {The Navy
                 Department Bureau of Ordnance and Harvard University at
                 The Computation Laboratory 7--10 January 1947}",
  title =        "Proceedings of a {Symposium on Large-Scale Digital
                 Calculating Machinery}: Jointly Sponsored by {The Navy
                 Department Bureau of Ordnance and Harvard University at
                 The Computation Laboratory 7--10 January 1947}",
  volume =       "16",
  publisher =    pub-HARVARD,
  address =      pub-HARVARD:adr,
  pages =        "xxix + 302",
  year =         "1948",
  LCCN =         "QA75 .S96 1947",
  bibdate =      "Mon Nov 4 07:46:57 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/b/babbage-charles.bib;
                 https://www.math.utah.edu/pub/tex/bib/adabooks.bib;
                 https://www.math.utah.edu/pub/tex/bib/annhistcomput.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "The Annals of the Computation Laboratory of Harvard
                 University",
  acknowledgement = ack-nhfb,
  keywords =     "calculators --- congresses; electronic digital
                 computers --- congresses",
  remark =       "Goldstine's paper is listed in the table of contents,
                 but is absent from the volume. The printed order of a
                 few papers differs from that shown in the table of
                 contents; the order has been corrected in the data in
                 this entry.",
  tableofcontents = "Program of the Symposium on Large-Scale Digital
                 Calculating Machinery: 7--10 January 1947 \\
                 First Session: Tuesday, 7 January 1947 1O:00 a.m. \\
                 Opening Addresses \\
                 Mr. Edward Reynolds, Administrative Vice President of
                 Harvard University / 3--3 \\
                 Rear Admiral C. T. Joy, USN, Naval Proving Ground,
                 Dahlgren, Virginia / 4--6 \\
                 Professor Howard H. Aiken, Chairman, Harvard University
                 / 7--7 \\
                 11:00 a.m. Inspection of the Computation Laboratory and
                 of Mark II Calculator \\
                 Second Session: Tuesday, 7 January 1947, 2:00 p.m. \\
                 Existing Calculating Machines / \\
                 Professor Willard E. Bleick, Chairman, Post Graduate
                 School, U.S. Naval Academy, Annapolis / \\
                 Mr. Richard H. Babbage, Montreal, Canada / The Work of
                 Charles Babbage / 13--22 \\
                 Mr. Richard M. Bloch, Harvard University / Mark I
                 Calculator / 23--30 \\
                 Dr. Lewis P. Tabor, University of Pennsylvania / Brief
                 Description and Operating Characteristics of the ENIAC
                 / 31--40 \\
                 Mr. Samuel B. Williams, Consulting Electrical Engineer
                 / Bell Telephone Laboratories' Relay Computing System /
                 41--68 \\
                 Mr. Robert V. D. Campbell, Harvard University / Mark II
                 Calculator / 69--79 \\
                 Third Session: Wednesday, 8 January 1947, 9:30 a.m. \\
                 The Logic of Large-Scale Calculating Machinery / \\
                 Professor \Vendell H. Furry, Chairman, Harvard
                 University \\
                 Dr. Alexander W. Wundheiler, Bureau of Ordnance /
                 Problems of Mathematical Analysis Involved in Machine
                 Computations / 83--90 \\
                 Dr. George R. Stibitz, University of Vermont / The
                 Organization of Large-Scale Calculating Machinery /
                 91--100 \\
                 Fourth Session: Wednesday, 8 January 1947, 2:00 p.m.
                 \\
                 Storage Devices \\
                 Dr. John H. Curtiss, Chairman / National Bureau of
                 Standards / \\
                 Dr. T. Kite Sharpless, University of Pennsylvania /
                 Mercury Delay Lines as a Memory Unit / 103--109 \\
                 Professor Leon Brillouin, Harvard University / Slow
                 Electromagnetic Waves / 110--124 \\
                 Dr. Jay W. Forrester, Massachusetts Institute of
                 Technology / High-Speed Electrostatic Storage /
                 125--129 \\
                 Dr. Benjamin L. Moore, Harvard University / Magnetic
                 and Phosphor Coated Discs / 130--132 \\
                 Dr. Jan Rajchman, Radio Corporation of America / The
                 Selectron --- A Tube for Selective Electrostatic
                 Storage / 133--145 \\
                 Dr. Arthur W. Tyler, Eastman Kodak Company / Optical
                 and Photographic Storage Techniques / 146--150 \\
                 Fifth Session: Thursday, 9 January 1947, 9:30 a.m. \\
                 Numerical Methods and Suggested Problems for Solution
                 \\
                 Dr. Mina Rees, Chairman, Office of Naval Research \\
                 Professor Richard Courant, New York University / Method
                 of Finite Differences for the Solution of Partial
                 Differential Equations / 153--156 \\
                 Dr. Raymond J. Seeger, Naval Ordnance Laboratory / On
                 Computational Techniques for Certain Problems in Fluid
                 Dynamics / 157--168 \\
                 Professor Wassily W. Leontief, Harvard University /
                 Computational Problems Arising in Connection with
                 Economic Analysis of interindustrial Relationships /
                 169--175 \\
                 Professor Hans A. Rademacher, University of
                 Pennsylvania / On the Accumulation of Errors in
                 Processes of Integration on High-Speed Calculating
                 Machines / 176--187 \\
                 Professor Howard W. Emmons, Harvard University / Fluid
                 Mechanics Computations / 188--193 \\
                 Dr. L. S. Dederick, Ballistic Research Laboratory,
                 Aberdeen, Maryland / Firing Tables / 194--199 \\
                 Sixth Session: Thursday, 9 January 1947, 2:00 p.m. \\
                 Sequencing, Coding, and Problem Preparation \\
                 Dr. Julius A. Stratton, Chairman, Massachusetts
                 Institute of Technology \\
                 Dr. John W. Mauchly, Electronic Control Company /
                 Preparation of Problems for EDVAC-Type Machines /
                 203--207 \\
                 Mr. Joseph 0. Harrison, Jr., Harvard University / The
                 Preparation of Problems for the Mark I Calculator /
                 208--210 \\
                 Dr. Herman H. Goldstine, Institute for Advanced Study /
                 Coding for Large-Scale Calculating Machinery / ??--??
                 \\
                 Seventh Session: Friday, 10 January 1947, 9:30 a.m. \\
                 Input and Output Devices \\
                 Professor E. Leon Chaffee, Chairman, Harvard University
                 \\
                 Mr. Frederick G. Miller, Harvard University /
                 Application of Printing Telegraph Techniques to
                 Large-Scale Calculating Machinery / 213--222 \\
                 Mr. Otto Kornei, The Brush Development Company / Survey
                 of Magnetic Recording / 223--237 \\
                 Mr. Harrison W. Fuller, Harvard University / The
                 Numeroscope / 238--247 \\
                 Dr. Samuel N. Alexander, National Bureau of Standards /
                 Input and Output Devices for Electronic Digital
                 Calculating Machinery / 248--253 \\
                 Dr. Morris Rubinoff, Harvard University / An Input
                 Device Using Multiple Gates / 254--259 \\
                 Dr. R. D. O'Neal, Eastman Kodak Company / Photographic
                 Methods of Handling Input and Output Data / 260--266
                 \\
                 Mr. C. Bradford Sheppard, Electronic Control Company /
                 Transfer Between External and Internal Memory /
                 267--273 \\
                 Eighth Session: Friday, 10 January 1947, 2:00 p.m. \\
                 Conclusions and Open Discussion \\
                 Professor Charles C. Bramble, Chairman, Post Graduate
                 School, U.S. Naval Academy, Annapolis / \\
                 Professor Samuel H. Caldwell, Massachusetts Institute
                 of Technology / Publication, Classification, and
                 Patents / 277--283 \\
                 Dr. Louis Couffignal (in absentia), Centre National de
                 la Recherche Scientifique / Le Domaine du Calcul
                 M{\'e}canique / 284--296 \\
                 Dr. Alan T. Waterman, Office of Naval Research / New
                 Vistas in Mathematics / 298--302",
}


bibtype: proceedings
filename: fparith.bib
label: Householder:1951:MCM
editor: Alston S. Householder and George E. Forsythe and Hallett-Hunt Germond
volume: 12
publisher: pub-USGPO
address: pub-USGPO:adr
pages: 49
year: 1951
bibdate: Tue Jan 31 06:36:58 2017
bibtimestamp: 2017.01.31 06:36:58 ???
series: ser-APPL-MATH-SER-NBS
acknowledgement: ack-nhfb
raweditor: Alston S. Householder and George E. Forsythe and Hallett-Hunt Germond
booktitle:
Monte Carlo method. Proceedings of a Symposium Held June 29, 30 and July 1, 1949 in Los Angeles, California

title:
Monte Carlo method. Proceedings of a Symposium Held June 29, 30 and July 1, 1949 in Los Angeles, California

bibsource:
https://www.math.utah.edu/pub/bibnet/authors/f/forsythe-george-elmer.bib; https://www.math.utah.edu/pub/bibnet/authors/v/von-neumann-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcw.bib; https://www.math.utah.edu/pub/tex/bib/prng.bib

TOC:
Preface / iii Foreword / v 1. Showers produced by low-energy electrons and photons / Robert R. Wilson / 1 2. An alignment chart for Monte Carlo solution of the transport problem / B. I. Spinrad, G. H. Goertzel, W. S. Snyder / 4 3. Neutron age calculations in water, graphite, and tissue / Alston S. Householder / 6 4. Methods of probabilities in chains applied to particle transmission through matter / Wendell C. DeMarcus, Lewis Nelson / 9 5. Stochastic methods in statistical mechanics / W. Gilbert King / 12 6. Report on a Monte Carlo calculation performed with the Eniac / Maria Mayer / 19 7. Calculation of shielding properties of water for high energy neutrons / Preston C. Hammer / 21 8. A Monte Carlo technique for estimating particle attenuation in bulk matter / B. A. Shoor, Lewis Nelson, Wendell DeMarcus, Robert L. Echols / 24 9. Estimation of particle transmission by random sampling / Herman Kahn, T. E. Harris / 27 10. History of RAND's random digits --- Summary / W. George Brown / 31 11. The mid-square method of generating digits / Preston C. Hammer / 33 12. Generation and testing of random digits at the National Bureau of Standards, Los Angeles / George E. Forsythe / 34 13. Various techniques used in connection with random digits / John von Neumann / 36 14. Round table discussion / H. H. Germond / 39

rawbooktitle:
{Monte Carlo method. Proceedings of a Symposium Held June 29, 30 and July 1, 1949 in Los Angeles, California}

rawtitle:
{Monte Carlo method. Proceedings of a Symposium Held June 29, 30 and July 1, 1949 in Los Angeles, California}

rawTOC:
Preface / iii \\ Foreword / v \\ 1. Showers produced by low-energy electrons and photons / Robert R. Wilson / 1 \\ 2. An alignment chart for Monte Carlo solution of the transport problem / B. I. Spinrad, G. H. Goertzel, W. S. Snyder / 4 \\ 3. Neutron age calculations in water, graphite, and tissue / Alston S. Householder / 6 \\ 4. Methods of probabilities in chains applied to particle transmission through matter / Wendell C. DeMarcus, Lewis Nelson / 9 \\ 5. Stochastic methods in statistical mechanics / W. Gilbert King / 12 \\ 6. Report on a Monte Carlo calculation performed with the Eniac / Maria Mayer / 19 \\ 7. Calculation of shielding properties of water for high energy neutrons / Preston C. Hammer / 21 \\ 8. A Monte Carlo technique for estimating particle attenuation in bulk matter / B. A. Shoor, Lewis Nelson, Wendell DeMarcus, Robert L. Echols / 24 \\ 9. Estimation of particle transmission by random sampling / Herman Kahn, T. E. Harris / 27 \\ 10. History of RAND's random digits --- Summary / W. George Brown / 31 \\ 11. The mid-square method of generating digits / Preston C. Hammer / 33 \\ 12. Generation and testing of random digits at the National Bureau of Standards, Los Angeles / George E. Forsythe / 34 \\ 13. Various techniques used in connection with random digits / John von Neumann / 36 \\ 14. Round table discussion / H. H. Germond / 39

entry:
@Proceedings{Householder:1951:MCM,
  editor =       "Alston S. Householder and George E. Forsythe and
                 Hallett-Hunt Germond",
  booktitle =    "{Monte Carlo method. Proceedings of a Symposium Held
                 June 29, 30 and July 1, 1949 in Los Angeles,
                 California}",
  title =        "{Monte Carlo method. Proceedings of a Symposium Held
                 June 29, 30 and July 1, 1949 in Los Angeles,
                 California}",
  volume =       "12",
  publisher =    pub-USGPO,
  address =      pub-USGPO:adr,
  pages =        "49",
  year =         "1951",
  bibdate =      "Tue Jan 31 06:36:58 2017",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/f/forsythe-george-elmer.bib;
                 https://www.math.utah.edu/pub/bibnet/authors/v/von-neumann-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcw.bib;
                 https://www.math.utah.edu/pub/tex/bib/prng.bib",
  series =       ser-APPL-MATH-SER-NBS,
  acknowledgement = ack-nhfb,
  tableofcontents = "Preface / iii \\
                 Foreword / v \\
                 1. Showers produced by low-energy electrons and photons
                 / Robert R. Wilson / 1 \\
                 2. An alignment chart for Monte Carlo solution of the
                 transport problem / B. I. Spinrad, G. H. Goertzel, W.
                 S. Snyder / 4 \\
                 3. Neutron age calculations in water, graphite, and
                 tissue / Alston S. Householder / 6 \\
                 4. Methods of probabilities in chains applied to
                 particle transmission through matter / Wendell C.
                 DeMarcus, Lewis Nelson / 9 \\
                 5. Stochastic methods in statistical mechanics / W.
                 Gilbert King / 12 \\
                 6. Report on a Monte Carlo calculation performed with
                 the Eniac / Maria Mayer / 19 \\
                 7. Calculation of shielding properties of water for
                 high energy neutrons / Preston C. Hammer / 21 \\
                 8. A Monte Carlo technique for estimating particle
                 attenuation in bulk matter / B. A. Shoor, Lewis Nelson,
                 Wendell DeMarcus, Robert L. Echols / 24 \\
                 9. Estimation of particle transmission by random
                 sampling / Herman Kahn, T. E. Harris / 27 \\
                 10. History of RAND's random digits --- Summary / W.
                 George Brown / 31 \\
                 11. The mid-square method of generating digits /
                 Preston C. Hammer / 33 \\
                 12. Generation and testing of random digits at the
                 National Bureau of Standards, Los Angeles / George E.
                 Forsythe / 34 \\
                 13. Various techniques used in connection with random
                 digits / John von Neumann / 36 \\
                 14. Round table discussion / H. H. Germond / 39",
}


