# bibtab

bibtype: article
filename: fparith.bib
label: Takahashi:2005:AMP
author: Daisuke Takahashi
title: An algorithm for multiple-precision floating-point multiplication
journal: j-APPL-MATH-COMP
volume: 166
number: 2
pages: 291--298
day: 15
month: jul
monthnumber: 7
year: 2005
CODEN: AMHCBQ
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
MRclass: 65G99
MRnumber: MR2143788 (2006a:65075)
bibdate: Mon Jul 4 09:15:46 MDT 2005
bibtimestamp: 2005.07.04 09:15:46 MDT
fjournal: Applied Mathematics and Computation
keywords: Fast Fourier transform; Multiple-precision arithmetic; Multiplication; Program derivation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: Daisuke Takahashi
rawtitle: An algorithm for multiple-precision floating-point multiplication
bibsource:
http://www.sciencedirect.com/science/journal/00963003; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We present an algorithm for multiple-precision floating-point multiplication. The conventional algorithms based on the fast Fourier transform (FFT) multiply two $n$-bit numbers to obtain a $ 2 n $-bit result. In multiple-precision floating-point multiplication, we need only the returned result whose precision is equal to the multiple-precision floating-point number. We show that the overall arithmetic operations for FFT-based multiple-precision floating-point multiplication are reduced by decomposition of the full-length multiplication into shorter-length multiplication.

rawabstract:
We present an algorithm for multiple-precision floating-point multiplication. The conventional algorithms based on the fast Fourier transform (FFT) multiply two $n$-bit numbers to obtain a $ 2 n $-bit result. In multiple-precision floating-point multiplication, we need only the returned result whose precision is equal to the multiple-precision floating-point number. We show that the overall arithmetic operations for FFT-based multiple-precision floating-point multiplication are reduced by decomposition of the full-length multiplication into shorter-length multiplication.

entry:
@Article{Takahashi:2005:AMP,
  author =       "Daisuke Takahashi",
  title =        "An algorithm for multiple-precision floating-point
                 multiplication",
  journal =      j-APPL-MATH-COMP,
  volume =       "166",
  number =       "2",
  pages =        "291--298",
  day =          "15",
  month =        jul,
  year =         "2005",
  CODEN =        "AMHCBQ",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  MRclass =      "65G99",
  MRnumber =     "MR2143788 (2006a:65075)",
  bibdate =      "Mon Jul 4 09:15:46 MDT 2005",
  bibsource =    "http://www.sciencedirect.com/science/journal/00963003;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present an algorithm for multiple-precision
                 floating-point multiplication. The conventional
                 algorithms based on the fast Fourier transform (FFT)
                 multiply two $n$-bit numbers to obtain a $ 2 n $-bit
                 result. In multiple-precision floating-point
                 multiplication, we need only the returned result whose
                 precision is equal to the multiple-precision
                 floating-point number. We show that the overall
                 arithmetic operations for FFT-based multiple-precision
                 floating-point multiplication are reduced by
                 decomposition of the full-length multiplication into
                 shorter-length multiplication.",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
  keywords =     "Fast Fourier transform; Multiple-precision arithmetic;
                 Multiplication; Program derivation",
}


bibtype: techreport
filename: fparith.bib
label: Tang:2005:BBI
author: Ping Tak Peter Tang
type: Technical report
institution: Intel Corporation
address: San Jose, CA, USA
pages: 291--298
day: 17
month: jun
monthnumber: 6
year: 2005
bibdate: Thu Oct 14 14:50:39 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.14 14:50:39 ???
keywords: BID (Binary-Integer Decimal) Encoding; decimal floating point arithmetic
remark: Last Updated: July 12, 2005. Minor Modifications: January 3, 2006
acknowledgement: ack-nhfb
rawauthor: Ping Tak Peter Tang
title:
BID --- Binary-Integer Decimal Encoding for Decimal Floating Point: a Format Friendly to Software Emulation and Compiler Native Support

rawtitle:
{BID} --- Binary-Integer Decimal Encoding for Decimal Floating Point: a Format Friendly to Software Emulation and Compiler Native Support

entry:
@TechReport{Tang:2005:BBI,
  author =       "Ping Tak Peter Tang",
  title =        "{BID} --- Binary-Integer Decimal Encoding for Decimal
                 Floating Point: a Format Friendly to Software Emulation
                 and Compiler Native Support",
  type =         "Technical report",
  institution =  "Intel Corporation",
  address =      "San Jose, CA, USA",
  day =          "17",
  month =        jun,
  year =         "2005",
  bibdate =      "Thu Oct 14 14:50:39 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "BID (Binary-Integer Decimal) Encoding; decimal
                 floating point arithmetic",
  remark =       "Last Updated: July 12, 2005. Minor Modifications:
                 January 3, 2006",
}


bibtype: techreport
filename: fparith.bib
label: Tang:2005:GBE
author: Ping Tak Peter Tang
title: On Generalized BCD Encodings for Decimal Floating Point
type: Technical comment
institution: Software and Solutions Group, Intel Corporation
address: San Jose, CA, USA
pages: 291--298
day: 7
month: mar
monthnumber: 3
year: 2005
bibdate: Sat Nov 05 21:19:43 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.11.05 21:19:43 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Ping Tak Peter Tang
rawtitle: On Generalized {BCD} Encodings for Decimal Floating Point
entry:
@TechReport{Tang:2005:GBE,
  author =       "Ping Tak Peter Tang",
  title =        "On Generalized {BCD} Encodings for Decimal Floating
                 Point",
  type =         "Technical comment",
  institution =  "Software and Solutions Group, Intel Corporation",
  address =      "San Jose, CA, USA",
  day =          "7",
  month =        mar,
  year =         "2005",
  bibdate =      "Sat Nov 05 21:19:43 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Tsuiki:2005:RNC
author: Hideki Tsuiki
title: Real number computation with committed choice logic programming languages
journal: j-J-LOGIC-ALG-PROG
volume: 64
number: 1
pages: 61--84
month: jul
monthnumber: 7
year: 2005
DOI: https://doi.org/10.1016/j.jlap.2004.07.005
ISSN: 1567-8326 (print), 1873-5940 (electronic) OR 15678326 (print), 18735940 (electronic)
ISSNL: 1567-8326 OR 15678326
bibdate: Thu Oct 17 10:09:18 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 10:09:18 ???
fjournal: Journal of Logic and Algebraic Programming
remark: Special issue on Practical development of exact real number computation.
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/15678326
rawauthor: Hideki Tsuiki
rawtitle: Real number computation with committed choice logic programming languages
entry:
@Article{Tsuiki:2005:RNC,
  author =       "Hideki Tsuiki",
  title =        "Real number computation with committed choice logic
                 programming languages",
  journal =      j-J-LOGIC-ALG-PROG,
  volume =       "64",
  number =       "1",
  pages =        "61--84",
  month =        jul,
  year =         "2005",
  DOI =          "https://doi.org/10.1016/j.jlap.2004.07.005",
  ISSN =         "1567-8326 (print), 1873-5940 (electronic)",
  ISSN-L =       "1567-8326",
  bibdate =      "Thu Oct 17 10:09:18 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Logic and Algebraic Programming",
  journal-URL =  "http://www.sciencedirect.com/science/journal/15678326",
  remark =       "Special issue on Practical development of exact real
                 number computation.",
}


bibtype: incollection
filename: fparith.bib
label: Turing:2005:PEC
author: Alan M. Turing
title: Proposed Electronic Calculator (1945)
crossref: Copeland:2005:ATA
pages: ??--??
year: 2005
DOI: https://doi.org/10.1093/acprof:oso/9780198565932.003.0021
bibdate: Mon Nov 01 18:47:26 2010
bibtimestamp: 2010.11.01 18:47:26 ???
acknowledgement: ack-nhfb
authordates: Alan Mathison Turing (23 June 1912--7 June 1954)
rawauthor: Alan M. Turing
rawtitle: Proposed Electronic Calculator (1945)
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/t/turing-alan-mathison.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
This chapter presents Alan M. Turing's report, `Proposed Electronic Calculator'. The report was submitted to the Executive Committee of the National Physical Laboratory in February 1946, under the description `Report by Dr. A. M. Turing on Proposals for the Development of an Automatic Computing Engine (ACE)'. The design set out in `Proposed Electronic Calculator' was the basis for all the ACE computers.

rawabstract:
This chapter presents Alan M. Turing's report, `Proposed Electronic Calculator'. The report was submitted to the Executive Committee of the National Physical Laboratory in February 1946, under the description `Report by Dr. A. M. Turing on Proposals for the Development of an Automatic Computing Engine (ACE)'. The design set out in `Proposed Electronic Calculator' was the basis for all the ACE computers.

entry:
@InCollection{Turing:2005:PEC,
  author =       "Alan M. Turing",
  title =        "Proposed Electronic Calculator (1945)",
  crossref =     "Copeland:2005:ATA",
  pages =        "??--??",
  year =         "2005",
  DOI =          "https://doi.org/10.1093/acprof:oso/9780198565932.003.0021",
  bibdate =      "Mon Nov 01 18:47:26 2010",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/t/turing-alan-mathison.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This chapter presents Alan M. Turing's report,
                 `Proposed Electronic Calculator'. The report was
                 submitted to the Executive Committee of the National
                 Physical Laboratory in February 1946, under the
                 description `Report by Dr. A. M. Turing on Proposals
                 for the Development of an Automatic Computing Engine
                 (ACE)'. The design set out in `Proposed Electronic
                 Calculator' was the basis for all the ACE computers.",
  acknowledgement = ack-nhfb,
  author-dates = "Alan Mathison Turing (23 June 1912--7 June 1954)",
}


bibtype: inproceedings
filename: fparith.bib
label: Usevitch:2005:JCL
author: B. Usevitch
booktitle: Proceedings. DCC 2005 Data Compression Conference, 29--31 March 2005
title: JPEG2000 Compliant Lossless Coding of Floating Point Data
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 484--484
year: 2005
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: B. Usevitch
rawbooktitle: Proceedings. {DCC 2005} Data Compression Conference, 29--31 March 2005
rawtitle: {JPEG2000} Compliant Lossless Coding of Floating Point Data
entry:
@InProceedings{Usevitch:2005:JCL,
  author =       "B. Usevitch",
  booktitle =    "Proceedings. {DCC 2005} Data Compression Conference,
                 29--31 March 2005",
  title =        "{JPEG2000} Compliant Lossless Coding of Floating Point
                 Data",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "484--484",
  year =         "2005",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Verdonk:2005:BSI
author: B. Verdonk and J. Vervloet and A. Cuyt
title: Blending Set and Interval Arithmetic for Maximal Reliability
journal: j-COMPUTING
volume: 74
number: 1
pages: 41--65
month: feb
monthnumber: 2
year: 2005
CODEN: CMPTA2
DOI: https://doi.org/10.1007/s00607-004-0090-2
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
bibdate: Tue Jul 5 09:25:15 MDT 2005
bibtimestamp: 2005.07.05 09:25:15 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=74&issue=1&spage=41
fjournal: Computing: Archiv fur informatik und numerik
keywords: inclusion property; Interval arithmetic
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/607
rawauthor: B. Verdonk and J. Vervloet and A. Cuyt
rawtitle: Blending Set and Interval Arithmetic for Maximal Reliability
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=74&issue=1; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
In both [3] and [8], the authors review the implementation of the basic operations in interval arithmetic, and in particular discuss the different approaches given in the literature for interval division when the divisor interval contains zero. In these papers, and in the references therein, the basic operations are defined for real or extended real interval operands.par Division by an interval containing zero is a special case of an interval function for which the input arguments contain points outside the domain of the underlying point function. A number of approaches exist in the literature, [7], [12], to remove restrictions on the domain of interval functions and hence obtain a closed, exception-free interval system.par In this paper, we present an alternative approach to remove restrictions on the domain of interval functions and to guarantee the inclusion property in all situations, even when some input intervals contain points that lie outside the domain of the underlying point function. To achieve this, we allow for the (efficient) set-based representation of non-real results. The computed intervals are sharp, yet contain more information and the resulting interval system is closed and exception-free. We also show how the presented ideas can be implemented in an interval arithmetic library. The performance overhead is negligible compared to the fact that the implementation using the new approach offers 100% reliability in return.par The structure of the paper is as follows. We set off with a motivating example in Sect. 1. In Sect. 2, we review various approaches to interval division and then introduce vset-division of real intervals, based on the newly introduced concept of value set or vset. In Sect. 3, we give a formal definition of real vset-intervals and arithmetic on these intervals. We prove a number of essential properties and point out the likenesses and differences with other approaches. Finally, in Sect. 4, we discuss the implementation of vset-interval arithmetic in a floating-point context.

rawabstract:
In both [3] and [8], the authors review the implementation of the basic operations in interval arithmetic, and in particular discuss the different approaches given in the literature for interval division when the divisor interval contains zero. In these papers, and in the references therein, the basic operations are defined for real or extended real interval operands.\par Division by an interval containing zero is a special case of an interval function for which the input arguments contain points outside the domain of the underlying point function. A number of approaches exist in the literature, [7], [12], to remove restrictions on the domain of interval functions and hence obtain a closed, exception-free interval system.\par In this paper, we present an alternative approach to remove restrictions on the domain of interval functions and to guarantee the inclusion property in all situations, even when some input intervals contain points that lie outside the domain of the underlying point function. To achieve this, we allow for the (efficient) set-based representation of non-real results. The computed intervals are sharp, yet contain more information and the resulting interval system is closed and exception-free. We also show how the presented ideas can be implemented in an interval arithmetic library. The performance overhead is negligible compared to the fact that the implementation using the new approach offers 100\% reliability in return.\par The structure of the paper is as follows. We set off with a motivating example in Sect. 1. In Sect. 2, we review various approaches to interval division and then introduce vset-division of real intervals, based on the newly introduced concept of value set or vset. In Sect. 3, we give a formal definition of real vset-intervals and arithmetic on these intervals. We prove a number of essential properties and point out the likenesses and differences with other approaches. Finally, in Sect. 4, we discuss the implementation of vset-interval arithmetic in a floating-point context.

entry:
@Article{Verdonk:2005:BSI,
  author =       "B. Verdonk and J. Vervloet and A. Cuyt",
  title =        "Blending Set and Interval Arithmetic for Maximal
                 Reliability",
  journal =      j-COMPUTING,
  volume =       "74",
  number =       "1",
  pages =        "41--65",
  month =        feb,
  year =         "2005",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/s00607-004-0090-2",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  bibdate =      "Tue Jul 5 09:25:15 MDT 2005",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=74&issue=1;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=74&issue=1&spage=41",
  abstract =     "In both [3] and [8], the authors review the
                 implementation of the basic operations in interval
                 arithmetic, and in particular discuss the different
                 approaches given in the literature for interval
                 division when the divisor interval contains zero. In
                 these papers, and in the references therein, the basic
                 operations are defined for real or extended real
                 interval operands.\par

                 Division by an interval containing zero is a special
                 case of an interval function for which the input
                 arguments contain points outside the domain of the
                 underlying point function. A number of approaches exist
                 in the literature, [7], [12], to remove restrictions on
                 the domain of interval functions and hence obtain a
                 closed, exception-free interval system.\par

                 In this paper, we present an alternative approach to
                 remove restrictions on the domain of interval functions
                 and to guarantee the inclusion property in all
                 situations, even when some input intervals contain
                 points that lie outside the domain of the underlying
                 point function. To achieve this, we allow for the
                 (efficient) set-based representation of non-real
                 results. The computed intervals are sharp, yet contain
                 more information and the resulting interval system is
                 closed and exception-free. We also show how the
                 presented ideas can be implemented in an interval
                 arithmetic library. The performance overhead is
                 negligible compared to the fact that the implementation
                 using the new approach offers 100\% reliability in
                 return.\par

                 The structure of the paper is as follows. We set off
                 with a motivating example in Sect. 1. In Sect. 2, we
                 review various approaches to interval division and then
                 introduce vset-division of real intervals, based on the
                 newly introduced concept of value set or vset. In Sect.
                 3, we give a formal definition of real vset-intervals
                 and arithmetic on these intervals. We prove a number of
                 essential properties and point out the likenesses and
                 differences with other approaches. Finally, in Sect. 4,
                 we discuss the implementation of vset-interval
                 arithmetic in a floating-point context.",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
  keywords =     "inclusion property; Interval arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Wahid:2005:EFC
author: Khan Wahid and Vassil Dimitrov and Graham Jullien
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-138.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Khan Wahid and Vassil Dimitrov and Graham Jullien
title:
Error-Free Computation of $ 8 times 8 $ $2$-D DCT and IDCT using Two-Dimensional Algebraic Integer Quantization

abstract:
This paper presents a novel error-free (infinite-precision) architecture for the fast implementation of both $ 8 times 8 $ $2$-D Discrete Cosine Transform and Inverse DCT. The architecture uses a new algebraic integer quantization of a $1$-D radix-8 DCT that allows the separable computation of a $2$-D $ 8 times 8 $ DCT without any intermediate number representation conversions. This is a considerable improvement on previously introduced algebraic integer encoding techniques to compute both DCT and IDCT which eliminates the requirements to approximate the transformation matrix elements by obtaining their exact representations and hence mapping the transcendental functions without any errors. Using this encoding scheme, an entire $ 8 times 8 $ $1$-D DCT-SQ (scalar quantization) algorithm can be implemented with only 24 adders. Apart from the multiplication-free nature, this new mapping scheme fits to this algorithm, eliminating any computational or quantization errors and resulting short-word-length and high-speed-design.

rawabstract:
This paper presents a novel error-free (infinite-precision) architecture for the fast implementation of both $ 8 \times 8 $ $2$-D Discrete Cosine Transform and Inverse DCT. The architecture uses a new algebraic integer quantization of a $1$-D radix-8 DCT that allows the separable computation of a $2$-D $ 8 \times 8 $ DCT without any intermediate number representation conversions. This is a considerable improvement on previously introduced algebraic integer encoding techniques to compute both DCT and IDCT which eliminates the requirements to approximate the transformation matrix elements by obtaining their exact representations and hence mapping the transcendental functions without any errors. Using this encoding scheme, an entire $ 8 \times 8 $ $1$-D DCT-SQ (scalar quantization) algorithm can be implemented with only 24 adders. Apart from the multiplication-free nature, this new mapping scheme fits to this algorithm, eliminating any computational or quantization errors and resulting short-word-length and high-speed-design.

rawtitle:
Error-Free Computation of $ 8 \times 8 $ {$2$-D} {DCT} and {IDCT} using Two-Dimensional Algebraic Integer Quantization

entry:
@InProceedings{Wahid:2005:EFC,
  author =       "Khan Wahid and Vassil Dimitrov and Graham Jullien",
  title =        "Error-Free Computation of $ 8 \times 8 $ {$2$-D} {DCT}
                 and {IDCT} using Two-Dimensional Algebraic Integer
                 Quantization",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-138.pdf",
  abstract =     "This paper presents a novel error-free
                 (infinite-precision) architecture for the fast
                 implementation of both $ 8 \times 8 $ $2$-D Discrete
                 Cosine Transform and Inverse DCT. The architecture uses
                 a new algebraic integer quantization of a $1$-D radix-8
                 DCT that allows the separable computation of a $2$-D $
                 8 \times 8 $ DCT without any intermediate number
                 representation conversions. This is a considerable
                 improvement on previously introduced algebraic integer
                 encoding techniques to compute both DCT and IDCT which
                 eliminates the requirements to approximate the
                 transformation matrix elements by obtaining their exact
                 representations and hence mapping the transcendental
                 functions without any errors. Using this encoding
                 scheme, an entire $ 8 \times 8 $ $1$-D DCT-SQ (scalar
                 quantization) algorithm can be implemented with only 24
                 adders. Apart from the multiplication-free nature, this
                 new mapping scheme fits to this algorithm, eliminating
                 any computational or quantization errors and resulting
                 short-word-length and high-speed-design.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: article
filename: fparith.bib
label: Wait:2005:IPF
author: C. D. Wait
title: IBM PowerPC 440 FPU with complex-arithmetic extensions
journal: j-IBM-JRD
volume: 49
number: 2/3
pages: 249--254
year: 2005
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Wed Jun 1 08:14:41 MDT 2005
bibsource: http://www.research.ibm.com/journal/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.01 08:14:41 MDT
URL: http://www.research.ibm.com/journal/rd/492/wait.pdf
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawauthor: C. D. Wait
rawtitle: {IBM PowerPC 440 FPU} with complex-arithmetic extensions
abstract:
The PowerPC 440 floating-point unit (FPU) with complex-arithmetic extensions is an embedded application-specific integrated circuit (ASIC) core designed to be used with the IBM PowerPC 440 processor core on the Blue Gene/L compute chip. The FPU core implements the floating-point instruction set from the PowerPC Architecture and the floating-point instruction extensions created to aid in matrix and complex-arithmetic operations. The FPU instruction extensions de ne double-precision operations that are primarily single-instruction multiple-data (SIMD) and require two (primary and secondary) arithmetic pipelines and floating-point register files. However, to aid complex-arithmetic routines, some FPU extensions actually perform different (yet closely related) operations while executing in the arithmetic pipelines. The FPU core implements an operand crossbar between the primary and secondary arithmetic datapaths to enable each pipeline operand access from the primary or secondary register file. The PowerPC 440 processor core provides 128-bit storage buses and simultaneous issue of an arithmetic instruction with a storage instruction, allowing the FPU core to fully utilize the parallel arithmetic pipes.

rawabstract:
The PowerPC 440 floating-point unit (FPU) with complex-arithmetic extensions is an embedded application-specific integrated circuit (ASIC) core designed to be used with the IBM PowerPC 440 processor core on the Blue Gene/L compute chip. The FPU core implements the floating-point instruction set from the PowerPC Architecture and the floating-point instruction extensions created to aid in matrix and complex-arithmetic operations. The FPU instruction extensions de ne double-precision operations that are primarily single-instruction multiple-data (SIMD) and require two (primary and secondary) arithmetic pipelines and floating-point register files. However, to aid complex-arithmetic routines, some FPU extensions actually perform different (yet closely related) operations while executing in the arithmetic pipelines. The FPU core implements an operand crossbar between the primary and secondary arithmetic datapaths to enable each pipeline operand access from the primary or secondary register file. The PowerPC 440 processor core provides 128-bit storage buses and simultaneous issue of an arithmetic instruction with a storage instruction, allowing the FPU core to fully utilize the parallel arithmetic pipes.

entry:
@Article{Wait:2005:IPF,
  author =       "C. D. Wait",
  title =        "{IBM PowerPC 440 FPU} with complex-arithmetic
                 extensions",
  journal =      j-IBM-JRD,
  volume =       "49",
  number =       "2/3",
  pages =        "249--254",
  month =        "????",
  year =         "2005",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Wed Jun 1 08:14:41 MDT 2005",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.research.ibm.com/journal/rd/492/wait.pdf",
  abstract =     "The PowerPC 440 floating-point unit (FPU) with
                 complex-arithmetic extensions is an embedded
                 application-specific integrated circuit (ASIC) core
                 designed to be used with the IBM PowerPC 440 processor
                 core on the Blue Gene/L compute chip. The FPU core
                 implements the floating-point instruction set from the
                 PowerPC Architecture and the floating-point instruction
                 extensions created to aid in matrix and
                 complex-arithmetic operations. The FPU instruction
                 extensions de ne double-precision operations that are
                 primarily single-instruction multiple-data (SIMD) and
                 require two (primary and secondary) arithmetic
                 pipelines and floating-point register files. However,
                 to aid complex-arithmetic routines, some FPU extensions
                 actually perform different (yet closely related)
                 operations while executing in the arithmetic pipelines.
                 The FPU core implements an operand crossbar between the
                 primary and secondary arithmetic datapaths to enable
                 each pipeline operand access from the primary or
                 secondary register file. The PowerPC 440 processor core
                 provides 128-bit storage buses and simultaneous issue
                 of an arithmetic instruction with a storage
                 instruction, allowing the FPU core to fully utilize the
                 parallel arithmetic pipes.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  ordernumber =  "G322-0240",
}


bibtype: inproceedings
filename: fparith.bib
label: Walter:2005:DDP
author: Colin Walter and David Samyde
title: Data Dependent Power Use in Multipliers
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-126.pdf
acknowledgement: ack-nhfb
rawauthor: Colin Walter and David Samyde
rawtitle: Data Dependent Power Use in Multipliers
abstract:
Recent research has demonstrated the vulnerability of certain smart card architectures to power and electromagnetic analysis when multiplier operations are insufficiently shielded from external monitoring. Here several standard multipliers are investigated in more detail in order to provide the foundation for understanding potential weaknesses and enabling the subsequent successful repair of those systems. A model is built which accurately predicts power use as a function of the Hamming weights of inputs without the combinatorial explosion of exhaustive simulation. This confirms that power use is indeed data dependent at least for those multipliers. Laboratory experiments confirm that EMR also corresponds closely to these power predictions over a wide range of frequencies.

keywords:
ARITH-17; Differential power analysis; DPA; EMA; multiplication; multiplier; RSA cryptosystem.; smart card

rawabstract:
Recent research has demonstrated the vulnerability of certain smart card architectures to power and electromagnetic analysis when multiplier operations are insufficiently shielded from external monitoring. Here several standard multipliers are investigated in more detail in order to provide the foundation for understanding potential weaknesses and enabling the subsequent successful repair of those systems. A model is built which accurately predicts power use as a function of the Hamming weights of inputs without the combinatorial explosion of exhaustive simulation. This confirms that power use is indeed data dependent at least for those multipliers. Laboratory experiments confirm that EMR also corresponds closely to these power predictions over a wide range of frequencies.

entry:
@InProceedings{Walter:2005:DDP,
  author =       "Colin Walter and David Samyde",
  title =        "Data Dependent Power Use in Multipliers",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-126.pdf",
  abstract =     "Recent research has demonstrated the vulnerability of
                 certain smart card architectures to power and
                 electromagnetic analysis when multiplier operations are
                 insufficiently shielded from external monitoring. Here
                 several standard multipliers are investigated in more
                 detail in order to provide the foundation for
                 understanding potential weaknesses and enabling the
                 subsequent successful repair of those systems. A model
                 is built which accurately predicts power use as a
                 function of the Hamming weights of inputs without the
                 combinatorial explosion of exhaustive simulation. This
                 confirms that power use is indeed data dependent at
                 least for those multipliers. Laboratory experiments
                 confirm that EMR also corresponds closely to these
                 power predictions over a wide range of frequencies.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17; Differential power analysis; DPA; EMA;
                 multiplication; multiplier; RSA cryptosystem.; smart
                 card",
  pagecount =    "9",
}


bibtype: inproceedings
filename: fparith.bib
label: Walters:2005:EFA
author: George Walters and Michael Schulte
title: Efficient Function Approximation Using Truncated Multipliers and Squarers
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-190.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: George Walters and Michael Schulte
rawtitle: Efficient Function Approximation Using Truncated Multipliers and Squarers
abstract:
This paper presents a technique for designing linear and quadratic interpolators for function approximation using truncated multipliers and squarers. Initial coefficient values are found using a Chebyshev series approximation, and then adjusted through exhaustive simulation to minimize the maximum absolute error of the interpolator output. This technique is suitable for any function and any precision up to 24-bits (IEEE single precision). Designs for linear and quadratic interpolators that implement the reciprocal function, $ f(x) = 1 / x, $ are presented and analyzed as an example. We show that a 24-bit truncated reciprocal quadratic interpolator with a design specification of $ pm 1 $ ulp error requires 24.1% fewer partial products to implement than a comparable standard interpolator with the same error specification.

rawabstract:
This paper presents a technique for designing linear and quadratic interpolators for function approximation using truncated multipliers and squarers. Initial coefficient values are found using a Chebyshev series approximation, and then adjusted through exhaustive simulation to minimize the maximum absolute error of the interpolator output. This technique is suitable for any function and any precision up to 24-bits (IEEE single precision). Designs for linear and quadratic interpolators that implement the reciprocal function, $ f(x) = 1 / x, $ are presented and analyzed as an example. We show that a 24-bit truncated reciprocal quadratic interpolator with a design specification of $ \pm 1 $ ulp error requires 24.1\% fewer partial products to implement than a comparable standard interpolator with the same error specification.

entry:
@InProceedings{Walters:2005:EFA,
  author =       "George Walters and Michael Schulte",
  title =        "Efficient Function Approximation Using Truncated
                 Multipliers and Squarers",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-190.pdf",
  abstract =     "This paper presents a technique for designing linear
                 and quadratic interpolators for function approximation
                 using truncated multipliers and squarers. Initial
                 coefficient values are found using a Chebyshev series
                 approximation, and then adjusted through exhaustive
                 simulation to minimize the maximum absolute error of
                 the interpolator output. This technique is suitable for
                 any function and any precision up to 24-bits (IEEE
                 single precision). Designs for linear and quadratic
                 interpolators that implement the reciprocal function, $
                 f(x) = 1 / x, $ are presented and analyzed as an
                 example. We show that a 24-bit truncated reciprocal
                 quadratic interpolator with a design specification of $
                 \pm 1 $ ulp error requires 24.1\% fewer partial
                 products to implement than a comparable standard
                 interpolator with the same error specification.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:2005:DFPa
author: L.-K. Wang and M. J. Schulte
title: Decimal Floating-Point Square Root Using Newton--Raphson Iteration
crossref: Vassiliadis:2005:IIC
pages: 309--315
year: 2005
bibdate: Sun Mar 04 10:19:28 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 10:19:28 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2005-05.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: L.-K. Wang and M. J. Schulte
rawtitle: Decimal Floating-Point Square Root Using {Newton--Raphson} Iteration
abstract:
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth in commercial, financial, and Internet-based applications, decimal floating point arithmetic is now attracting more attention and hardware support for decimal operations is being considered by various computer manufacturers. In order to standardize decimal number formats and operations, specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic (IEEE-754R). This paper presents an efficient arithmetic algorithm and hardware design for decimal floating-point square root. This design uses an optimized piecewise linear approximation, a modified Newton--Raphson iteration, a specialized rounding technique, and a modified decimal multiplier. Synthesis results show that a 64-bit (16-digit) implementation of decimal square root, which is compliant with IEEE-754R, has an estimated critical path delay of 0.95 ns and a maximum latency of 210 clock cycles when implemented using a sequential multiplier and LSI Logic's 0.11 micron Gflx-P standard cell library.

rawabstract:
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth in commercial, financial, and Internet-based applications, decimal floating point arithmetic is now attracting more attention and hardware support for decimal operations is being considered by various computer manufacturers. In order to standardize decimal number formats and operations, specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic (IEEE-754R). This paper presents an efficient arithmetic algorithm and hardware design for decimal floating-point square root. This design uses an optimized piecewise linear approximation, a modified Newton--Raphson iteration, a specialized rounding technique, and a modified decimal multiplier. Synthesis results show that a 64-bit (16-digit) implementation of decimal square root, which is compliant with IEEE-754R, has an estimated critical path delay of 0.95 ns and a maximum latency of 210 clock cycles when implemented using a sequential multiplier and LSI Logic's 0.11 micron Gflx-P standard cell library.

entry:
@InProceedings{Wang:2005:DFPa,
  author =       "L.-K. Wang and M. J. Schulte",
  title =        "Decimal Floating-Point Square Root Using
                 {Newton--Raphson} Iteration",
  crossref =     "Vassiliadis:2005:IIC",
  pages =        "309--315",
  year =         "2005",
  bibdate =      "Sun Mar 04 10:19:28 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2005-05.pdf",
  abstract =     "With continued reductions in feature size, additional
                 functionality may be added to future microprocessors to
                 boost the performance of important application domains.
                 Due to growth in commercial, financial, and
                 Internet-based applications, decimal floating point
                 arithmetic is now attracting more attention and
                 hardware support for decimal operations is being
                 considered by various computer manufacturers. In order
                 to standardize decimal number formats and operations,
                 specifications for decimal floating-point arithmetic
                 have been added to the draft revision of the IEEE-754
                 Standard for Floating-Point Arithmetic (IEEE-754R).
                 This paper presents an efficient arithmetic algorithm
                 and hardware design for decimal floating-point square
                 root. This design uses an optimized piecewise linear
                 approximation, a modified Newton--Raphson iteration, a
                 specialized rounding technique, and a modified decimal
                 multiplier. Synthesis results show that a 64-bit
                 (16-digit) implementation of decimal square root, which
                 is compliant with IEEE-754R, has an estimated critical
                 path delay of 0.95 ns and a maximum latency of 210
                 clock cycles when implemented using a sequential
                 multiplier and LSI Logic's 0.11 micron Gflx-P standard
                 cell library.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Whidborne:2005:OCF
author: James F. Whidborne and Da-Wei Gu and Jun Wu and Sheng Chen
title: Optimal controller and filter realizations using finite-precision, floating-point arithmetic
journal: j-INT-J-SYST-SCI
volume: 36
number: 7
pages: 405--413
year: 2005
CODEN: IJSYA9
ISSN: 0020-7721 (print), 1464-5319 (electronic) OR 00207721 (print), 14645319 (electronic)
ISSNL: 0020-7721 OR 00207721
MRclass: 93B50 (93B40 93E11)
MRnumber: MR2152458
bibdate: Thu Nov 8 19:16:14 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:16:14 ???
fjournal: International Journal of Systems Science. Principles and Applications of Systems and Integration
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/tsys20
rawauthor: James F. Whidborne and Da-Wei Gu and Jun Wu and Sheng Chen
rawtitle: Optimal controller and filter realizations using finite-precision, floating-point arithmetic
entry:
@Article{Whidborne:2005:OCF,
  author =       "James F. Whidborne and Da-Wei Gu and Jun Wu and Sheng
                 Chen",
  title =        "Optimal controller and filter realizations using
                 finite-precision, floating-point arithmetic",
  journal =      j-INT-J-SYST-SCI,
  volume =       "36",
  number =       "7",
  pages =        "405--413",
  year =         "2005",
  CODEN =        "IJSYA9",
  ISSN =         "0020-7721 (print), 1464-5319 (electronic)",
  ISSN-L =       "0020-7721",
  MRclass =      "93B50 (93B40 93E11)",
  MRnumber =     "MR2152458",
  bibdate =      "Thu Nov 8 19:16:14 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of Systems Science. Principles
                 and Applications of Systems and Integration",
  journal-URL =  "http://www.tandfonline.com/loi/tsys20",
}


bibtype: incollection
filename: fparith.bib
label: Wilkinson:2005:PAN
author: James H. Wilkinson
title: The Pilot ACE at the National Physical Laboratory
crossref: Copeland:2005:ATA
pages: 93--105
year: 2005
DOI: https://doi.org/10.1093/acprof:oso/9780198565932.003.0005
bibdate: Mon Nov 01 18:18:06 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.11.01 18:18:06 ???
URL: http://www.ingentaconnect.com/content/oso/2353639/2005/00000001/00000001/art00006
acknowledgement: ack-nhfb
rawauthor: James H. Wilkinson
rawtitle: The {Pilot ACE} at the {National Physical Laboratory}
abstract:
This chapter discusses the pilot Automatic Computing Engine (ACE) project at the National Physical Laboratory. The Pilot ACE had been designed purely as an experimental machine to demonstrate the competence of the team as computer engineers. It was originally intended that when it was successfully completed a full-scale computer would be built. However, when it was successful, it was the only electronic computer in a government department and the engineers came under very heavy pressure to use the Pilot ACE for serious computing. They implemented a small set of modifications which included the addition of an automatic multiplier and improvements to the control unit which made programming a little less arduous. The computer was then put into general use and did yeoman service for a number of years.

remark:
Reprint of article in em The Radio and Electronic Engineer, Vol. 45, No. 7, pp. 336--340, July 1975. From the article:par ``A great deal of quite detailed coding was done by the ACE team in the period from 1946--1948. It included basic subroutines for such things as multi-length arithmetic (including multiplication, division and square roots), floating-point arithmetic (both single-precision and double-precision) and interval arithmetic. The subroutines for floating-point arithmetic were particularly detailed; they were coded by G. G. Alway and myself in 1947 and were for both Version V and Version VII. They were almost certainly the earliest floating-point subroutines and it is interesting that those for the Version V were essentially the same as the subroutines which were subsequently used on the Pilot ACE itself. At a time when the arithmetic provided on modern computers is often so disappointing it is interesting to recall that the subroutines included provision for accumulating inner-products in double-precision floating-point arithmetic and all rounding was immaculate.''par ``Even double precision and triple precision floating-point routines were reasonably fast and we gained extensive experience with such computation long before it was much used elsewhere. I think it is not unreasonable to claim that the development of floating-point error analysis at NPL, which was well in advance of that elsewhere, was an indirect consequence of our use of optimum coding.''

rawabstract:
This chapter discusses the pilot Automatic Computing Engine (ACE) project at the National Physical Laboratory. The Pilot ACE had been designed purely as an experimental machine to demonstrate the competence of the team as computer engineers. It was originally intended that when it was successfully completed a full-scale computer would be built. However, when it was successful, it was the only electronic computer in a government department and the engineers came under very heavy pressure to use the Pilot ACE for serious computing. They implemented a small set of modifications which included the addition of an automatic multiplier and improvements to the control unit which made programming a little less arduous. The computer was then put into general use and did yeoman service for a number of years.

entry:
@InCollection{Wilkinson:2005:PAN,
  author =       "James H. Wilkinson",
  title =        "The {Pilot ACE} at the {National Physical
                 Laboratory}",
  crossref =     "Copeland:2005:ATA",
  pages =        "93--105",
  year =         "2005",
  DOI =          "https://doi.org/10.1093/acprof:oso/9780198565932.003.0005",
  bibdate =      "Mon Nov 01 18:18:06 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.ingentaconnect.com/content/oso/2353639/2005/00000001/00000001/art00006",
  abstract =     "This chapter discusses the pilot Automatic Computing
                 Engine (ACE) project at the National Physical
                 Laboratory. The Pilot ACE had been designed purely as
                 an experimental machine to demonstrate the competence
                 of the team as computer engineers. It was originally
                 intended that when it was successfully completed a
                 full-scale computer would be built. However, when it
                 was successful, it was the only electronic computer in
                 a government department and the engineers came under
                 very heavy pressure to use the Pilot ACE for serious
                 computing. They implemented a small set of
                 modifications which included the addition of an
                 automatic multiplier and improvements to the control
                 unit which made programming a little less arduous. The
                 computer was then put into general use and did yeoman
                 service for a number of years.",
  acknowledgement = ack-nhfb,
  remark =       "Reprint of article in {\em The Radio and Electronic
                 Engineer, Vol. 45, No. 7, pp. 336--340, July 1975}.
                 From the article:\par

                 ``A great deal of quite detailed coding was done by the
                 ACE team in the period from 1946--1948. It included
                 basic subroutines for such things as multi-length
                 arithmetic (including multiplication, division and
                 square roots), floating-point arithmetic (both
                 single-precision and double-precision) and interval
                 arithmetic. The subroutines for floating-point
                 arithmetic were particularly detailed; they were coded
                 by G. G. Alway and myself in 1947 and were for both
                 Version V and Version VII. They were almost certainly
                 the earliest floating-point subroutines and it is
                 interesting that those for the Version V were
                 essentially the same as the subroutines which were
                 subsequently used on the Pilot ACE itself. At a time
                 when the arithmetic provided on modern computers is
                 often so disappointing it is interesting to recall that
                 the subroutines included provision for accumulating
                 inner-products in double-precision floating-point
                 arithmetic and all rounding was
                 immaculate.''\par

                 ``Even double precision and triple precision
                 floating-point routines were reasonably fast and we
                 gained extensive experience with such computation long
                 before it was much used elsewhere. I think it is not
                 unreasonable to claim that the development of
                 floating-point error analysis at NPL, which was well in
                 advance of that elsewhere, was an indirect consequence
                 of our use of optimum coding.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Wo:2005:SSC
author: Zhaojun Wo and Israel Koren
title: Synthesis of Saturating Counters Using Traditional and Non-traditional Basic Counters
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-191.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Zhaojun Wo and Israel Koren
rawtitle: Synthesis of Saturating Counters Using Traditional and Non-traditional Basic Counters
abstract:
Saturating counters are a newly defined class of generalized parallel counters that provide the exact number of inputs which are equal to 1 only if this number is below a given threshold. Such counters are useful in, for example, self-test and repair units for embedded memories. This paper defines saturating counters for arbitrary threshold values and presents several alternatives for their implementation. The delay and area of the proposed design alternatives are then estimated using a 0.25$ mu $ m cell library. Finally, we study the behavior of saturating counters when the threshold approaches the number of input bits, i.e., the special case of non-saturating parallel counters.

rawabstract:
Saturating counters are a newly defined class of generalized parallel counters that provide the exact number of inputs which are equal to 1 only if this number is below a given threshold. Such counters are useful in, for example, self-test and repair units for embedded memories. This paper defines saturating counters for arbitrary threshold values and presents several alternatives for their implementation. The delay and area of the proposed design alternatives are then estimated using a 0.25$ \mu $ m cell library. Finally, we study the behavior of saturating counters when the threshold approaches the number of input bits, i.e., the special case of non-saturating parallel counters.

entry:
@InProceedings{Wo:2005:SSC,
  author =       "Zhaojun Wo and Israel Koren",
  title =        "Synthesis of Saturating Counters Using Traditional and
                 Non-traditional Basic Counters",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-191.pdf",
  abstract =     "Saturating counters are a newly defined class of
                 generalized parallel counters that provide the exact
                 number of inputs which are equal to 1 only if this
                 number is below a given threshold. Such counters are
                 useful in, for example, self-test and repair units for
                 embedded memories. This paper defines saturating
                 counters for arbitrary threshold values and presents
                 several alternatives for their implementation. The
                 delay and area of the proposed design alternatives are
                 then estimated using a 0.25$ \mu $ m cell library.
                 Finally, we study the behavior of saturating counters
                 when the threshold approaches the number of input bits,
                 i.e., the special case of non-saturating parallel
                 counters.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: article
filename: fparith.bib
label: Yang:2005:IMM
author: Jen-Ho Yang and Chin-Chen Chang and Chih-Hung Wang
title: An iterative modular multiplication algorithm in RNS
journal: j-APPL-MATH-COMP
volume: 171
number: 1
pages: 637--645
day: 1
month: dec
monthnumber: 12
year: 2005
CODEN: AMHCBQ
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Sat Jul 12 09:02:51 MDT 2008
bibtimestamp: 2008.07.12 09:02:51 MDT
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: Jen-Ho Yang and Chin-Chen Chang and Chih-Hung Wang
rawtitle: An iterative modular multiplication algorithm in {RNS}
bibsource:
http://www.sciencedirect.com/science/journal/00963003; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Yang:2005:IMM,
  author =       "Jen-Ho Yang and Chin-Chen Chang and Chih-Hung Wang",
  title =        "An iterative modular multiplication algorithm in
                 {RNS}",
  journal =      j-APPL-MATH-COMP,
  volume =       "171",
  number =       "1",
  pages =        "637--645",
  day =          "1",
  month =        dec,
  year =         "2005",
  CODEN =        "AMHCBQ",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Sat Jul 12 09:02:51 MDT 2008",
  bibsource =    "http://www.sciencedirect.com/science/journal/00963003;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
}


bibtype: inproceedings
filename: fparith.bib
label: Yatskiv:2005:MAB
author: V. Yatskiv and N. Yatskiv
title: Multiple Access on the Basis of Residue Number System Transformation
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 527--530
year: 2005
DOI: https://doi.org/10.1109/IDAACS.2005.283039
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: V. Yatskiv and N. Yatskiv
rawtitle: Multiple Access on the Basis of Residue Number System Transformation
booktitle:
Proceedings of The Third Workshop 2005 IEEE Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications

rawbooktitle:
Proceedings of The Third Workshop 2005 {IEEE} Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications

entry:
@InProceedings{Yatskiv:2005:MAB,
  author =       "V. Yatskiv and N. Yatskiv",
  booktitle =    "Proceedings of The Third Workshop 2005 {IEEE}
                 Intelligent Data Acquisition and Advanced Computing
                 Systems: Technology and Applications",
  title =        "Multiple Access on the Basis of Residue Number System
                 Transformation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "527--530",
  year =         "2005",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/IDAACS.2005.283039",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "In this paper research of efficiency channelizing
                 methods on the basis of residue number of classes of
                 transformation is conducted. Research is conducted on
                 the basis of calculation of delay mean time before
                 transmission. The results of \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Zeydel:2005:EMA
author: Bart Zeydel and Theo Kluter and Vojin Oklobdzija
title: Efficient Mapping of Addition Recurrence Algorithms in CMOS
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-181.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Bart Zeydel and Theo Kluter and Vojin Oklobdzija
rawtitle: Efficient Mapping of Addition Recurrence Algorithms in {CMOS}
abstract:
Efficient adder design requires proper selection of a recurrence algorithm and its realization. Each of the algorithms: Weinberger's, Ling's and Doran's were analyzed for its flexibility in representation and suitability for realization in CMOS. We describe general techniques for developing efficient realizations based on CMOS technology constraints when using Ling's algorithm. From these techniques we propose two high-performance realizations that achieve 1 FO4 delay improvement at the same energy and 50% energy reduction at the same delay than existing Ling and Weinberger designs.

rawabstract:
Efficient adder design requires proper selection of a recurrence algorithm and its realization. Each of the algorithms: Weinberger's, Ling's and Doran's were analyzed for its flexibility in representation and suitability for realization in CMOS. We describe general techniques for developing efficient realizations based on CMOS technology constraints when using Ling's algorithm. From these techniques we propose two high-performance realizations that achieve 1 FO4 delay improvement at the same energy and 50\% energy reduction at the same delay than existing Ling and Weinberger designs.

entry:
@InProceedings{Zeydel:2005:EMA,
  author =       "Bart Zeydel and Theo Kluter and Vojin Oklobdzija",
  title =        "Efficient Mapping of Addition Recurrence Algorithms in
                 {CMOS}",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-181.pdf",
  abstract =     "Efficient adder design requires proper selection of a
                 recurrence algorithm and its realization. Each of the
                 algorithms: Weinberger's, Ling's and Doran's were
                 analyzed for its flexibility in representation and
                 suitability for realization in CMOS. We describe
                 general techniques for developing efficient
                 realizations based on CMOS technology constraints when
                 using Ling's algorithm. From these techniques we
                 propose two high-performance realizations that achieve
                 1 FO4 delay improvement at the same energy and 50\%
                 energy reduction at the same delay than existing Ling
                 and Weinberger designs.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "7",
}


bibtype: article
filename: fparith.bib
label: Zhu:2005:NDA
author: Yong-Kang Zhu and Jun-Hai Yong and Guo-Qin Zheng
title: A New Distillation Algorithm for Floating-Point Summation
journal: j-SIAM-J-SCI-COMP
volume: 26
number: 6
pages: 2066--2078
month: nov
monthnumber: 11
year: 2005
CODEN: SJOCE3
DOI: https://doi.org/10.1137/030602009
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
MRclass: 65G05, 65B10
MRnumber: MR2196589 (2006i:65078)
bibdate: Mon Nov 21 14:52:48 MST 2005
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/SISC/26/6; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.11.21 14:52:48 MST
URL: http://epubs.siam.org/sam-bin/dbq/article/60200
fjournal: SIAM Journal on Scientific Computing
keywords: accurate floating-point summation; distillation; rounding error
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: Yong-Kang Zhu and Jun-Hai Yong and Guo-Qin Zheng
rawtitle: A New Distillation Algorithm for Floating-Point Summation
abstract:
The summation of $n$ floating-point numbers is ubiquitous in numerical computations. We present a new distillation algorithm for floating-point summation which is stable, efficient, and accurate. The algorithm iteratively ``distills'' the summands without discarding any significant digit until the partial sums cannot change the whole sum. It uses standard floating-point arithmetic and does not rely on the choice of radix or any other specific assumption. Furthermore, the error bound of our algorithm is independent of $n$ and less than 1 ulp.

rawabstract:
The summation of $n$ floating-point numbers is ubiquitous in numerical computations. We present a new distillation algorithm for floating-point summation which is stable, efficient, and accurate. The algorithm iteratively ``distills'' the summands without discarding any significant digit until the partial sums cannot change the whole sum. It uses standard floating-point arithmetic and does not rely on the choice of radix or any other specific assumption. Furthermore, the error bound of our algorithm is independent of $n$ and less than 1 ulp.

entry:
@Article{Zhu:2005:NDA,
  author =       "Yong-Kang Zhu and Jun-Hai Yong and Guo-Qin Zheng",
  title =        "A New Distillation Algorithm for Floating-Point
                 Summation",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "26",
  number =       "6",
  pages =        "2066--2078",
  month =        nov,
  year =         "2005",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/030602009",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  MRclass =      "65G05, 65B10",
  MRnumber =     "MR2196589 (2006i:65078)",
  bibdate =      "Mon Nov 21 14:52:48 MST 2005",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/26/6;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://epubs.siam.org/sam-bin/dbq/article/60200",
  abstract =     "The summation of $n$ floating-point numbers is
                 ubiquitous in numerical computations. We present a new
                 distillation algorithm for floating-point summation
                 which is stable, efficient, and accurate. The algorithm
                 iteratively ``distills'' the summands without
                 discarding any significant digit until the partial sums
                 cannot change the whole sum. It uses standard
                 floating-point arithmetic and does not rely on the
                 choice of radix or any other specific assumption.
                 Furthermore, the error bound of our algorithm is
                 independent of $n$ and less than 1 ulp.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "accurate floating-point summation; distillation;
                 rounding error",
}


bibtype: inproceedings
filename: fparith.bib
label: Zhuo:2005:DSF
author: Ling Zhuo and G. R. Morris and V. K. Prasanna
title: Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 147a-147a
year: 2005
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: Ling Zhuo and G. R. Morris and V. K. Prasanna
rawtitle: Designing Scalable {FPGA}-Based Reduction Circuits Using Pipelined Floating-Point Cores
booktitle:
Proceedings. 19th IEEE International Parallel and Distributed Processing Symposium, 04--08 April 2005

abstract:
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when using single-cycle arithmetic cores. ldots 

rawabstract:
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when using single-cycle arithmetic cores. \ldots{}

rawbooktitle:
Proceedings. 19th {IEEE} International Parallel and Distributed Processing Symposium, 04--08 April 2005

entry:
@InProceedings{Zhuo:2005:DSF,
  author =       "Ling Zhuo and G. R. Morris and V. K. Prasanna",
  booktitle =    "Proceedings. 19th {IEEE} International Parallel and
                 Distributed Processing Symposium, 04--08 April 2005",
  title =        "Designing Scalable {FPGA}-Based Reduction Circuits
                 Using Pipelined Floating-Point Cores",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "147a-147a",
  year =         "2005",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The use of pipelined floating-point arithmetic cores
                 to create high-performance FPGA-based computational
                 kernels has introduced a new class of problems that do
                 not exist when using single-cycle arithmetic cores.
                 \ldots{}",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Zimmermann:2005:EBC
author: Paul Zimmermann and Richard Brent and Colin Percival
title: Error bounds on complex floating-point multiplication
pages: 147a-147a
day: 14
month: dec
monthnumber: 12
year: 2005
bibdate: Wed Dec 14 09:56:25 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.12.14 09:56:25 ???
URL: http://www.loria.fr/~zimmerma/talks/cm.pdf
keywords: complex floating-point arithmetic; correct rounding; floating-point arithmetic
remark: Article submitted to Mathematics of Computation (2005), 12 pages.
acknowledgement: ack-nhfb
howpublished: World-Wide Web slides
rawauthor: Paul Zimmermann and Richard Brent and Colin Percival
rawtitle: Error bounds on complex floating-point multiplication
abstract:
Providing that no overflow or underflow occur, no denormal values are produced, arithmetic results are correctly rounded to a nearest representable value, $ z_0 z_1 neq 0 $, and $ epsilon leq 2^-5 $, the relative error $ |z_2 (z_0 z_1)^-1 - 1 | $ is less than $ epsilon sqrt 5 = (1 / 2) beta ^1 - t sqrt 5 $.

rawabstract:
Providing that no overflow or underflow occur, no denormal values are produced, arithmetic results are correctly rounded to a nearest representable value, $ z_0 z_1 \neq 0 $, and $ \epsilon \leq 2^{-5} $, the relative error $ |z_2 (z_0 z_1)^{-1} - 1 | $ is less than $ \epsilon \sqrt {5} = (1 / 2) \beta^{1 - t} \sqrt {5} $.

entry:
@Misc{Zimmermann:2005:EBC,
  author =       "Paul Zimmermann and Richard Brent and Colin Percival",
  title =        "Error bounds on complex floating-point
                 multiplication",
  howpublished = "World-Wide Web slides",
  day =          "14",
  month =        dec,
  year =         "2005",
  bibdate =      "Wed Dec 14 09:56:25 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.loria.fr/~zimmerma/talks/cm.pdf",
  abstract =     "Providing that no overflow or underflow occur, no
                 denormal values are produced, arithmetic results are
                 correctly rounded to a nearest representable value, $
                 z_0 z_1 \neq 0 $, and $ \epsilon \leq 2^{-5} $, the
                 relative error $ |z_2 (z_0 z_1)^{-1} - 1 | $ is less
                 than $ \epsilon \sqrt {5} = (1 / 2) \beta^{1 - t} \sqrt
                 {5} $.",
  acknowledgement = ack-nhfb,
  keywords =     "complex floating-point arithmetic; correct rounding;
                 floating-point arithmetic",
  remark =       "Article submitted to Mathematics of Computation
                 (2005), 12 pages.",
}


bibtype: misc
filename: fparith.bib
label: Zimmermann:2005:MPT
author: Paul Zimmermann and Nathalie Revol and Patrick Pelissier
title: tt mpcheck: a program to test the accuracy of elementary functions
pages: 147a-147a
year: 2005
bibdate: Sat Nov 05 21:16:00 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.11.05 21:16:00 ???
URL: http://www.loria.fr/~zimmerma/free/mpcheck-1.1.0.tar.gz; http://www.loria.fr/~zimmerma/mpcheck/
acknowledgement: ack-nhfb
howpublished: World-Wide Web software archive
rawauthor: Paul Zimmermann and Nathalie Revol and Patrick P{\'e}lissier
rawtitle: {{\tt mpcheck}}: a program to test the accuracy of elementary functions
entry:
@Misc{Zimmermann:2005:MPT,
  author =       "Paul Zimmermann and Nathalie Revol and Patrick
                 P{\'e}lissier",
  title =        "{{\tt mpcheck}}: a program to test the accuracy of
                 elementary functions",
  howpublished = "World-Wide Web software archive",
  year =         "2005",
  bibdate =      "Sat Nov 05 21:16:00 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.loria.fr/~zimmerma/free/mpcheck-1.1.0.tar.gz;
                 http://www.loria.fr/~zimmerma/mpcheck/",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Zimmermann:2005:MVC
author: Paul Zimmermann
title: MPFR: vers un calcul flottant correct ? (French) [MPFR: Towards correct floating-point arithmetic?]
type: Online interactive report.
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
pages: 147a-147a
year: 2005
bibdate: Sun Sep 10 07:38:21 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.10 07:38:21 ???
URL: http://interstices.info/display.jsp?id=c_9345
language: French
acknowledgement: ack-nhfb
rawauthor: Paul Zimmermann
abstract:
Obtenir un seul resultat pour un calcul donne: a premiere vue, cela semble une evidence; c'est en fait un vaste sujet de recherche auquel les chercheurs apportent petit a petit leurs contributions. Une nouvelle etape est franchie aujourd'hui grace a MPFR, une bibliotheque de calcul multi-precision sur les nombres flottants. (French) [Getting a single result for a given calculation seems obvious at first sight. In fact, it is a vast area of research to which researchers are adding their contributions little by little. A new level is reached today thanks to MPFR, a multiple-precision library for floating-point arithmetic.]

rawabstract:
Obtenir un seul r{\'e}sultat pour un calcul donn{\'e}: {\`a} premi{\`e}re vue, cela semble une {\'e}vidence; c'est en fait un vaste sujet de recherche auquel les chercheurs apportent petit {\`a} petit leurs contributions. Une nouvelle {\'e}tape est franchie aujourd'hui gr{\^a}ce {\`a} MPFR, une biblioth{\`e}que de calcul multi-pr{\'e}cision sur les nombres flottants. ({French}) [Getting a single result for a given calculation seems obvious at first sight. In fact, it is a vast area of research to which researchers are adding their contributions little by little. A new level is reached today thanks to MPFR, a multiple-precision library for floating-point arithmetic.]

rawtitle:
{MPFR}: vers un calcul flottant correct ? ({French}) [{MPFR}: Towards correct floating-point arithmetic?]

entry:
@TechReport{Zimmermann:2005:MVC,
  author =       "Paul Zimmermann",
  title =        "{MPFR}: vers un calcul flottant correct ? ({French})
                 [{MPFR}: Towards correct floating-point arithmetic?]",
  type =         "Online interactive report.",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  year =         "2005",
  bibdate =      "Sun Sep 10 07:38:21 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://interstices.info/display.jsp?id=c_9345",
  abstract =     "Obtenir un seul r{\'e}sultat pour un calcul donn{\'e}:
                 {\`a} premi{\`e}re vue, cela semble une {\'e}vidence;
                 c'est en fait un vaste sujet de recherche auquel les
                 chercheurs apportent petit {\`a} petit leurs
                 contributions. Une nouvelle {\'e}tape est franchie
                 aujourd'hui gr{\^a}ce {\`a} MPFR, une biblioth{\`e}que
                 de calcul multi-pr{\'e}cision sur les nombres
                 flottants. ({French}) [Getting a single result for a
                 given calculation seems obvious at first sight. In
                 fact, it is a vast area of research to which
                 researchers are adding their contributions little by
                 little. A new level is reached today thanks to MPFR, a
                 multiple-precision library for floating-point
                 arithmetic.]",
  acknowledgement = ack-nhfb,
  language =     "French",
}


bibtype: misc
filename: fparith.bib
label: Zimmermann:2005:WTA
author: Paul Zimmermann
title: Why transcendentals and arbitrary precision?
pages: 147a-147a
day: 15
month: dec
monthnumber: 12
year: 2005
bibdate: Thu Dec 15 15:03:09 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.12.15 15:03:09 ???
URL: http://www.loria.fr/~zimmerma/talks/why.pdf
acknowledgement: ack-nhfb
howpublished: World-Wide Web slides
rawauthor: Paul Zimmermann
rawtitle: Why transcendentals and arbitrary precision?
entry:
@Misc{Zimmermann:2005:WTA,
  author =       "Paul Zimmermann",
  title =        "Why transcendentals and arbitrary precision?",
  howpublished = "World-Wide Web slides",
  day =          "15",
  month =        dec,
  year =         "2005",
  bibdate =      "Thu Dec 15 15:03:09 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.loria.fr/~zimmerma/talks/why.pdf",
  acknowledgement = ack-nhfb,
  summary =      "This talk surveys the state of the computation of
                 transcendental functions on current hardware platforms,
                 and discusses the cost of implementing
                 correctly-rounded results.",
}


bibtype: techreport
filename: fparith.bib
label: Zimmermann:2005:XXX
author: Paul Zimmermann
title: 5,341,321
type: Technical report
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
pages: 2
day: 8
month: jun
monthnumber: 6
year: 2005
bibdate: Sun Sep 10 07:32:04 2006
bibtimestamp: 2006.09.10 07:32:04 ???
URL: http://www.loria.fr/~zimmerma/papers/5341321.ps.gz
keywords: floating-point division; Karp--Markstein patent on modified Newton--Raphson iteration
acknowledgement: ack-nhfb
rawauthor: Paul Zimmermann
rawtitle: 5,341,321
abstract:
This short note shows the nasty effects of patents for the development of free software, even for patents that were not written with software applications in mind.

remark:
The title is the number of the U.S. Patent on the algorithm described in the article, which is a completely trivial modification of Newton--Raphson iteration, published in cite Karp:1997:HPD. The patent itself is cite Karp:1994:FPA, and it expired on 5 May 2013.

rawabstract:
This short note shows the nasty effects of patents for the development of free software, even for patents that were not written with software applications in mind.

entry:
@TechReport{Zimmermann:2005:XXX,
  author =       "Paul Zimmermann",
  title =        "5,341,321",
  type =         "Technical report",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  pages =        "2",
  day =          "8",
  month =        jun,
  year =         "2005",
  bibdate =      "Sun Sep 10 07:32:04 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.loria.fr/~zimmerma/papers/5341321.ps.gz",
  abstract =     "This short note shows the nasty effects of patents for
                 the development of free software, even for patents that
                 were not written with software applications in mind.",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point division; Karp--Markstein patent on
                 modified Newton--Raphson iteration",
  remark =       "The title is the number of the U.S. Patent on the
                 algorithm described in the article, which is a
                 completely trivial modification of Newton--Raphson
                 iteration, published in \cite{Karp:1997:HPD}. The
                 patent itself is \cite{Karp:1994:FPA}, and it expired
                 on 5 May 2013.",
}


bibtype: inproceedings
filename: fparith.bib
label: Anderson:2006:AMF
author: Cristina S. Anderson and Shane Story and Nikita Astafiev
title: Accurate Math Functions on the Intel IA-32 Architecture: a Performance-Driven Design
crossref: Anonymous:2006:PCR
pages: ??--??
year: 2006
bibdate: Tue Jun 27 10:28:05 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.06.27 10:28:05 ???
keywords: elementary functions
acknowledgement: ack-nhfb
rawauthor: Cristina S. Anderson and Shane Story and Nikita Astafiev
rawtitle: Accurate Math Functions on the {Intel IA-32} Architecture: a Performance-Driven Design
entry:
@InProceedings{Anderson:2006:AMF,
  author =       "Cristina S. Anderson and Shane Story and Nikita
                 Astafiev",
  title =        "Accurate Math Functions on the {Intel IA-32}
                 Architecture: a Performance-Driven Design",
  crossref =     "Anonymous:2006:PCR",
  pages =        "??--??",
  year =         "2006",
  bibdate =      "Tue Jun 27 10:28:05 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "elementary functions",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2006:IFPa
author: Anonymous
title: Intel and Floating Point: Updating One of the Industry's Most Successful Standards
pages: ??--??
day: 20
month: jul
monthnumber: 7
year: 2006
bibdate: Wed Nov 22 21:51:25 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.11.22 21:51:25 ???
URL: http://www.intel.com/standards/floatingpoint.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: Anonymous
rawtitle: {Intel} and Floating Point: Updating One of the Industry's Most Successful Standards
entry:
@Misc{Anonymous:2006:IFPa,
  author =       "Anonymous",
  title =        "{Intel} and Floating Point: Updating One of the
                 Industry's Most Successful Standards",
  howpublished = "World-Wide Web document",
  day =          "20",
  month =        jul,
  year =         "2006",
  bibdate =      "Wed Nov 22 21:51:25 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.intel.com/standards/floatingpoint.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2006:IFPb
author: Anonymous
title: IBM's forthcoming Power6 processor can count to 10
pages: ??--??
month: oct
monthnumber: 10
year: 2006
bibdate: Wed Oct 11 07:44:23 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.10.11 07:44:23 ???
URL: http://news.zdnet.com/2100-9584_22-6124451.html
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: Anonymous
rawtitle: {IBM}'s forthcoming {Power6} processor can count to 10
remark:
Reports that the 5GHz Power6 is due in mid-2007, and adds hardware support for decimal floating-point arithmetic.

entry:
@Misc{Anonymous:2006:IFPb,
  author =       "Anonymous",
  title =        "{IBM}'s forthcoming {Power6} processor can count to
                 10",
  howpublished = "World-Wide Web document",
  month =        oct,
  year =         "2006",
  bibdate =      "Wed Oct 11 07:44:23 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://news.zdnet.com/2100-9584_22-6124451.html",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
  remark =       "Reports that the 5GHz Power6 is due in mid-2007, and
                 adds hardware support for decimal floating-point
                 arithmetic.",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2006:RSI
author: Anonymous
title: Reference Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic
pages: ??--??
year: 2006
bibdate: Wed Nov 22 21:40:41 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.11.22 21:40:41 ???
URL: http://cache-www.intel.com/cd/00/00/29/43/294339_294339.pdf
keywords: BID encoding; decimal floating-point arithmetic
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: Anonymous
rawtitle: Reference Software Implementation of the {IEEE 754R} Decimal Floating-Point Arithmetic
remark:
Describes new rounding algorithms that eliminate the need to convert a binary integer decimal representation to decimal, round, and convert back. The article claims median speedups of 6 to 60 over the IBM densely packed format used in the decNumber package. However, no information is given about the availability of this reference implementation. See also cite Cornea:2006:SII.

entry:
@Misc{Anonymous:2006:RSI,
  author =       "Anonymous",
  title =        "Reference Software Implementation of the {IEEE 754R}
                 Decimal Floating-Point Arithmetic",
  howpublished = "World-Wide Web document",
  year =         "2006",
  bibdate =      "Wed Nov 22 21:40:41 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://cache-www.intel.com/cd/00/00/29/43/294339_294339.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "BID encoding; decimal floating-point arithmetic",
  remark =       "Describes new rounding algorithms that eliminate the
                 need to convert a binary integer decimal representation
                 to decimal, round, and convert back. The article claims
                 median speedups of 6 to 60 over the IBM densely packed
                 format used in the decNumber package. However, no
                 information is given about the availability of this
                 reference implementation. See also
                 \cite{Cornea:2006:SII}.",
}


bibtype: article
filename: fparith.bib
label: Avanzi:2006:SMK
author: Roberto M. Avanzi and Clemens Heuberger and Helmut Prodinger
journal: j-ALGORITHMICA
volume: 46
number: 3--4
pages: 249--270
month: nov
monthnumber: 11
year: 2006
CODEN: ALGOEJ
DOI: https://doi.org/10.1007/s00453-006-0105-9
ISSN: 0178-4617 (print), 1432-0541 (electronic) OR 01784617 (print), 14320541 (electronic)
ISSNL: 0178-4617 OR 01784617
bibdate: Wed Jul 9 22:25:03 MDT 2008
bibtimestamp: 2008.07.09 22:25:03 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0178-4617&volume=46&issue=3&spage=249
fjournal: Algorithmica
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/453
rawauthor: Roberto M. Avanzi and Clemens Heuberger and Helmut Prodinger
title:
Scalar Multiplication on Koblitz Curves Using the Frobenius Endomorphism and Its Combination with Point Halving: Extensions and Mathematical Analysis

bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0178-4617&volume=46&issue=3; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
Scalar Multiplication on {Koblitz} Curves Using the {Frobenius} Endomorphism and Its Combination with Point Halving: Extensions and Mathematical Analysis

entry:
@Article{Avanzi:2006:SMK,
  author =       "Roberto M. Avanzi and Clemens Heuberger and Helmut
                 Prodinger",
  title =        "Scalar Multiplication on {Koblitz} Curves Using the
                 {Frobenius} Endomorphism and Its Combination with Point
                 Halving: Extensions and Mathematical Analysis",
  journal =      j-ALGORITHMICA,
  volume =       "46",
  number =       "3--4",
  pages =        "249--270",
  month =        nov,
  year =         "2006",
  CODEN =        "ALGOEJ",
  DOI =          "https://doi.org/10.1007/s00453-006-0105-9",
  ISSN =         "0178-4617 (print), 1432-0541 (electronic)",
  ISSN-L =       "0178-4617",
  bibdate =      "Wed Jul 9 22:25:03 MDT 2008",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0178-4617&volume=46&issue=3;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0178-4617&volume=46&issue=3&spage=249",
  acknowledgement = ack-nhfb,
  fjournal =     "Algorithmica",
  journal-URL =  "http://link.springer.com/journal/453",
}


bibtype: article
filename: fparith.bib
label: Bajard:2006:AOF
author: J.-C. Bajard and L. Imbert and C. Negre
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 9
pages: 1167--1177
month: sep
monthnumber: 9
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.136
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:56 MDT 2011
bibtimestamp: 2011.07.04 15:35:56 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1668044
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J.-C. Bajard and L. Imbert and C. Negre
title:
Arithmetic Operations in Finite Fields of Medium Prime Characteristic Using the Lagrange Representation

rawtitle:
Arithmetic Operations in Finite Fields of Medium Prime Characteristic Using the {Lagrange} Representation

entry:
@Article{Bajard:2006:AOF,
  author =       "J.-C. Bajard and L. Imbert and C. Negre",
  title =        "Arithmetic Operations in Finite Fields of Medium Prime
                 Characteristic Using the {Lagrange} Representation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "9",
  pages =        "1167--1177",
  month =        sep,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.136",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:56 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1668044",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Bartzis:2006:EBB
author: Constantinos Bartzis and Tevfik Bultan
title: Efficient BDDs for bounded arithmetic constraints
journal: j-INT-J-SOFTW-TOOLS-TECHNOL-TRANSFER
volume: 8
number: 1
pages: 26--36
month: feb
monthnumber: 2
year: 2006
DOI: https://doi.org/10.1007/s10009-004-0171-8
ISSN: 1433-2779 (print), 1433-2787 (electronic) OR 14332779 (print), 14332787 (electronic)
ISSNL: 1433-2779 OR 14332779
bibdate: Wed Jul 9 18:12:21 MDT 2008
bibtimestamp: 2008.07.09 18:12:21 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=1433-2779&volume=8&issue=1&spage=26
fjournal: International Journal on Software Tools for Technology Transfer: STTT
keywords: BDD; Integer arithmetic; Model checking; SMV
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10009
rawauthor: Constantinos Bartzis and Tevfik Bultan
rawtitle: Efficient {BDDs} for bounded arithmetic constraints
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=1433-2779&volume=8&issue=1; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Bartzis:2006:EBB,
  author =       "Constantinos Bartzis and Tevfik Bultan",
  title =        "Efficient {BDDs} for bounded arithmetic constraints",
  journal =      j-INT-J-SOFTW-TOOLS-TECHNOL-TRANSFER,
  volume =       "8",
  number =       "1",
  pages =        "26--36",
  month =        feb,
  year =         "2006",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s10009-004-0171-8",
  ISSN =         "1433-2779 (print), 1433-2787 (electronic)",
  ISSN-L =       "1433-2779",
  bibdate =      "Wed Jul 9 18:12:21 MDT 2008",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=1433-2779&volume=8&issue=1;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=1433-2779&volume=8&issue=1&spage=26",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal on Software Tools for Technology
                 Transfer: STTT",
  journal-URL =  "http://link.springer.com/journal/10009",
  keywords =     "BDD; Integer arithmetic; Model checking; SMV",
}


bibtype: article
filename: fparith.bib
label: Bernal:2006:IRD
author: Javier Bernal and Christoph J. Witzgall
title: Integer Representation of Decimal Numbers for Exact Computations
journal: j-J-RES-NATL-BUR-STAND
volume: 111
number: 2
pages: 79--88
month: mar
monthnumber: 3
year: 2006
DOI: https://doi.org/10.6028/jres.111.006
bibdate: Tue Nov 05 15:32:18 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.11.05 15:32:18 ???
URL: https://nvlpubs.nist.gov/nistpubs/jres/111/2/V111.N02.A02.pdf
acknowledgement: ack-nhfb
rawauthor: Javier Bernal and Christoph J. Witzgall
rawtitle: Integer Representation of Decimal Numbers for Exact Computations
abstract:
A scheme is presented and software is documented for representing as integers input decimal numbers that have been stored in a computer as double precision floating point numbers and for carrying out multiplications, additions and subtractions based on these numbers in an exact manner. The input decimal numbers must not have more than nine digits to the left of the decimal point. The decimal fractions of their floating point representations are all first rounded off at a prespecified location, a location no more than nine digits away from the decimal point. The number of digits to the left of the decimal point for each input number besides not being allowed to exceed nine must then be such that the total number of digits from the leftmost digit of the number to the location where round-off is to occur does not exceed fourteen.

keywords:
computational geometry; Delaunay triangulation; exact integer arithmetic; power diagram; regular triangulation; robustness; Voronoi diagram

rawabstract:
A scheme is presented and software is documented for representing as integers input decimal numbers that have been stored in a computer as double precision floating point numbers and for carrying out multiplications, additions and subtractions based on these numbers in an exact manner. The input decimal numbers must not have more than nine digits to the left of the decimal point. The decimal fractions of their floating point representations are all first rounded off at a prespecified location, a location no more than nine digits away from the decimal point. The number of digits to the left of the decimal point for each input number besides not being allowed to exceed nine must then be such that the total number of digits from the leftmost digit of the number to the location where round-off is to occur does not exceed fourteen.

entry:
@Article{Bernal:2006:IRD,
  author =       "Javier Bernal and Christoph J. Witzgall",
  title =        "Integer Representation of Decimal Numbers for Exact
                 Computations",
  journal =      j-J-RES-NATL-BUR-STAND,
  volume =       "111",
  number =       "2",
  pages =        "79--88",
  month =        mar # "\slash " # apr,
  year =         "2006",
  DOI =          "https://doi.org/10.6028/jres.111.006",
  bibdate =      "Tue Nov 05 15:32:18 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://nvlpubs.nist.gov/nistpubs/jres/111/2/V111.N02.A02.pdf",
  abstract =     "A scheme is presented and software is documented for
                 representing as integers input decimal numbers that
                 have been stored in a computer as double precision
                 floating point numbers and for carrying out
                 multiplications, additions and subtractions based on
                 these numbers in an exact manner. The input decimal
                 numbers must not have more than nine digits to the left
                 of the decimal point. The decimal fractions of their
                 floating point representations are all first rounded
                 off at a prespecified location, a location no more than
                 nine digits away from the decimal point. The number of
                 digits to the left of the decimal point for each input
                 number besides not being allowed to exceed nine must
                 then be such that the total number of digits from the
                 leftmost digit of the number to the location where
                 round-off is to occur does not exceed fourteen.",
  acknowledgement = ack-nhfb,
  keywords =     "computational geometry; Delaunay triangulation; exact
                 integer arithmetic; power diagram; regular
                 triangulation; robustness; Voronoi diagram",
}


bibtype: techreport
filename: fparith.bib
label: Bertot:2006:PGS
author: Yves Bertot and Nicolas Magaud and Paul Zimmermann
title: A proof of GMP square root using the Coq assistant
type: Research Report
number: RR-4475
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
pages: 28
year: 2006
bibdate: Sun Sep 10 08:34:35 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.10 08:34:35 ???
acknowledgement: ack-nhfb
rawauthor: Yves Bertot and Nicolas Magaud and Paul Zimmermann
rawtitle: A proof of {GMP} square root using the {Coq} assistant
URL:
ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-4475.pdf; ftp://ftp.inria.fr/INRIA/publication/publi-ps-gz/RR/RR-4475.ps.gz; http://www.inria.fr/rrrt/rr-4475.html

abstract:
We present a formal proof (at the implementation level) of an efficient algorithm proposed in to compute square roots of arbitrarily large integers. This program, which is part of the GNU Multiple Precision Arithmetic Library (GMP), is completely proven within the system. Proofs are developed using the Correctness tool to deal with imperative features of the program. The formalization is rather large (more than 13000 lines) and requires some advanced techniques for proof management and reuse.

rawabstract:
We present a formal proof (at the implementation level) of an efficient algorithm proposed in to compute square roots of arbitrarily large integers. This program, which is part of the GNU Multiple Precision Arithmetic Library (GMP), is completely proven within the system. Proofs are developed using the Correctness tool to deal with imperative features of the program. The formalization is rather large (more than 13000 lines) and requires some advanced techniques for proof management and reuse.

entry:
@TechReport{Bertot:2006:PGS,
  author =       "Yves Bertot and Nicolas Magaud and Paul Zimmermann",
  title =        "A proof of {GMP} square root using the {Coq}
                 assistant",
  type =         "Research Report",
  number =       "RR-4475",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  pages =        "28",
  year =         "2006",
  bibdate =      "Sun Sep 10 08:34:35 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-4475.pdf;
                 ftp://ftp.inria.fr/INRIA/publication/publi-ps-gz/RR/RR-4475.ps.gz;
                 http://www.inria.fr/rrrt/rr-4475.html",
  abstract =     "We present a formal proof (at the implementation
                 level) of an efficient algorithm proposed in to compute
                 square roots of arbitrarily large integers. This
                 program, which is part of the GNU Multiple Precision
                 Arithmetic Library (GMP), is completely proven within
                 the system. Proofs are developed using the Correctness
                 tool to deal with imperative features of the program.
                 The formalization is rather large (more than 13000
                 lines) and requires some advanced techniques for proof
                 management and reuse.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Bik:2006:MVF
author: Aart J. C. Bik and Xinmin Tian and Milind B. Girkar
title: Multimedia vectorization of floating-point MIN / MAX reductions
journal: j-CCPE
volume: 18
number: 9
pages: 997--1007
day: 10
month: aug
monthnumber: 8
year: 2006
CODEN: CCPEBO
DOI: https://doi.org/10.1002/cpe.1009
ISSN: 1532-0626 (print), 1532-0634 (electronic) OR 15320626 (print), 15320634 (electronic)
ISSNL: 1532-0626 OR 15320626
bibdate: Mon Dec 5 10:08:04 MST 2011
bibtimestamp: 2011.12.05 10:08:04 MST
fjournal: Concurrency and Computation: Practice and Experience
acknowledgement: ack-nhfb
journalURL: http://www.interscience.wiley.com/jpages/1532-0626
onlinedate: 12 Jan 2006
rawauthor: Aart J. C. Bik and Xinmin Tian and Milind B. Girkar
rawtitle: Multimedia vectorization of floating-point {MIN\slash MAX} reductions
bibsource:
http://www.interscience.wiley.com/jpages/1532-0626; https://www.math.utah.edu/pub/tex/bib/ccpe.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Bik:2006:MVF,
  author =       "Aart J. C. Bik and Xinmin Tian and Milind B. Girkar",
  title =        "Multimedia vectorization of floating-point {MIN\slash
                 MAX} reductions",
  journal =      j-CCPE,
  volume =       "18",
  number =       "9",
  pages =        "997--1007",
  day =          "10",
  month =        aug,
  year =         "2006",
  CODEN =        "CCPEBO",
  DOI =          "https://doi.org/10.1002/cpe.1009",
  ISSN =         "1532-0626 (print), 1532-0634 (electronic)",
  ISSN-L =       "1532-0626",
  bibdate =      "Mon Dec 5 10:08:04 MST 2011",
  bibsource =    "http://www.interscience.wiley.com/jpages/1532-0626;
                 https://www.math.utah.edu/pub/tex/bib/ccpe.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Concurrency and Computation: Prac\-tice and
                 Experience",
  journal-URL =  "http://www.interscience.wiley.com/jpages/1532-0626",
  onlinedate =   "12 Jan 2006",
}


bibtype: article
filename: fparith.bib
label: Boldo:2006:PFF
author: S. Boldo
journal: j-LECT-NOTES-COMP-SCI
volume: 4130
pages: 52--66
year: 2006
CODEN: LNCSD9
DOI: https://doi.org/10.1007/11814771_6
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
MRnumber: MR2354672
bibdate: Sun Feb 19 07:32:26 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.02.19 07:32:26 ???
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: S. Boldo
title:
Pitfalls of a full floating-point proof: example on the formal proof of the Veltkamp / Dekker algorithms

rawtitle:
Pitfalls of a full floating-point proof: example on the formal proof of the {Veltkamp\slash Dekker} algorithms

entry:
@Article{Boldo:2006:PFF,
  author =       "S. Boldo",
  title =        "Pitfalls of a full floating-point proof: example on
                 the formal proof of the {Veltkamp\slash Dekker}
                 algorithms",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "4130",
  pages =        "52--66",
  year =         "2006",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/11814771_6",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  MRnumber =     "MR2354672",
  bibdate =      "Sun Feb 19 07:32:26 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: misc
filename: fparith.bib
label: Bonten:2006:ACF
author: J. H. M. Bonten
title: Arithmetic Computer Formats
pages: 52--66
day: 5
month: oct
monthnumber: 10
year: 2006
bibdate: Tue Oct 30 11:08:12 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.30 11:08:12 ???
URL: http://home.hetnet.nl/mr_1/81/jhm.bonten/computers/bitsandbytes/wordsizes/
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: J. H. M. Bonten
rawtitle: Arithmetic Computer Formats
abstract:
This map contains a set of descriptions of the memory-word formats for the floating point numbers used in some extinct, old and modern species of the computer-fauna. Also it contains some theory about the storage of these numbers. And it gives some proposals to improve the use of decimal numbers, both in Cobol and in Fortran/C/C++.

keywords:
Burroughs 6700; Burroughs 7700; Burroughs 7900; Cray 1; DEC Alpha; DEC PDP-10; DEC PDP-11; DEC VAX; IBM 7094; IEEE-754; Unisys-A; Univac 1100; Univac 418

rawabstract:
This map contains a set of descriptions of the memory-word formats for the floating point numbers used in some extinct, old and modern species of the computer-fauna. Also it contains some theory about the storage of these numbers. And it gives some proposals to improve the use of decimal numbers, both in Cobol and in Fortran/C/C++.

entry:
@Misc{Bonten:2006:ACF,
  author =       "J. H. M. Bonten",
  title =        "Arithmetic Computer Formats",
  howpublished = "Web document",
  day =          "5",
  month =        oct,
  year =         "2006",
  bibdate =      "Tue Oct 30 11:08:12 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://home.hetnet.nl/mr_1/81/jhm.bonten/computers/bitsandbytes/wordsizes/",
  abstract =     "This map contains a set of descriptions of the
                 memory-word formats for the floating point numbers used
                 in some extinct, old and modern species of the
                 computer-fauna. Also it contains some theory about the
                 storage of these numbers. And it gives some proposals
                 to improve the use of decimal numbers, both in Cobol
                 and in Fortran/C/C++.",
  acknowledgement = ack-nhfb,
  keywords =     "Burroughs 6700; Burroughs 7700; Burroughs 7900; Cray
                 1; DEC Alpha; DEC PDP-10; DEC PDP-11; DEC VAX; IBM
                 7094; IEEE-754; Unisys-A; Univac 1100; Univac 418",
}


bibtype: article
filename: fparith.bib
label: Briggs:2006:IER
author: Keith Briggs
title: Implementing exact real arithmetic in tt python, C++ and C
journal: j-THEOR-COMP-SCI
volume: 351
number: 1
pages: 74--81
day: 14
month: feb
monthnumber: 2
year: 2006
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Tue Mar 29 06:48:55 MDT 2011
bibtimestamp: 2011.03.29 06:48:55 MDT
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: Keith Briggs
rawtitle: Implementing exact real arithmetic in {\tt python}, {C++} and {C}
bibsource:
http://www.sciencedirect.com/science/journal/03043975; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
I discuss the design and performance issues arising in the efficient implementation of the scaled-integer exact real arithmetic model introduced by Boehm and others. This system represents a real number with a automatically controlled level of precision by a rational with implicit denominator. I describe three practical codes, in python, C++ and C. These allow the convenient use of this computational paradigm in commonly used imperative languages.

rawabstract:
I discuss the design and performance issues arising in the efficient implementation of the scaled-integer exact real arithmetic model introduced by Boehm and others. This system represents a real number with a automatically controlled level of precision by a rational with implicit denominator. I describe three practical codes, in python, C++ and C. These allow the convenient use of this computational paradigm in commonly used imperative languages.

entry:
@Article{Briggs:2006:IER,
  author =       "Keith Briggs",
  title =        "Implementing exact real arithmetic in {\tt python},
                 {C++} and {C}",
  journal =      j-THEOR-COMP-SCI,
  volume =       "351",
  number =       "1",
  pages =        "74--81",
  day =          "14",
  month =        feb,
  year =         "2006",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Tue Mar 29 06:48:55 MDT 2011",
  bibsource =    "http://www.sciencedirect.com/science/journal/03043975;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "I discuss the design and performance issues arising in
                 the efficient implementation of the scaled-integer
                 exact real arithmetic model introduced by Boehm and
                 others. This system represents a real number with a
                 automatically controlled level of precision by a
                 rational with implicit denominator. I describe three
                 practical codes, in python, C++ and C. These allow the
                 convenient use of this computational paradigm in
                 commonly used imperative languages.",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
}


bibtype: inproceedings
filename: fparith.bib
label: Castellanos:2006:BDF
author: I. D. Castellanos and J. E. Stine
title: A 64-bit Decimal Floating-Point Comparator
crossref: Dimopoulos:2006:IIC
pages: 138--144
year: 2006
DOI: https://doi.org/10.1109/ASAP.2006.2
bibdate: Mon Mar 19 10:17:28 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.19 10:17:28 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: I. D. Castellanos and J. E. Stine
rawtitle: A 64-bit Decimal Floating-Point Comparator
abstract:
Decimal arithmetic is growing in importance as scientific studies reveal that current financial and commercial applications spend a high percentage overhead in this type of calculations. Typically, software is utilized to emulate decimal floating point arithmetic in these applications. On the other hand, functional units that employ decimal floating point hardware can improve performance by two or three orders of magnitude. This paper presents the design and implementation of a novel decimal floating-point comparator compliant with the current draft revision of the IEEE-754 Standard for floating-point arithmetic. It utilizes a novel BCD magnitude comparator with logarithmic delay and it supports 64-bit decimal floating-point numbers. Area and delay results are examined for an implementation in TSMC SCN6M SCMOS technology.

rawabstract:
Decimal arithmetic is growing in importance as scientific studies reveal that current financial and commercial applications spend a high percentage overhead in this type of calculations. Typically, software is utilized to emulate decimal floating point arithmetic in these applications. On the other hand, functional units that employ decimal floating point hardware can improve performance by two or three orders of magnitude. This paper presents the design and implementation of a novel decimal floating-point comparator compliant with the current draft revision of the IEEE-754 Standard for floating-point arithmetic. It utilizes a novel BCD magnitude comparator with logarithmic delay and it supports 64-bit decimal floating-point numbers. Area and delay results are examined for an implementation in TSMC SCN6M SCMOS technology.

entry:
@InProceedings{Castellanos:2006:BDF,
  author =       "I. D. Castellanos and J. E. Stine",
  title =        "A 64-bit Decimal Floating-Point Comparator",
  crossref =     "Dimopoulos:2006:IIC",
  pages =        "138--144",
  year =         "2006",
  DOI =          "https://doi.org/10.1109/ASAP.2006.2",
  bibdate =      "Mon Mar 19 10:17:28 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Decimal arithmetic is growing in importance as
                 scientific studies reveal that current financial and
                 commercial applications spend a high percentage
                 overhead in this type of calculations. Typically,
                 software is utilized to emulate decimal floating point
                 arithmetic in these applications. On the other hand,
                 functional units that employ decimal floating point
                 hardware can improve performance by two or three orders
                 of magnitude. This paper presents the design and
                 implementation of a novel decimal floating-point
                 comparator compliant with the current draft revision of
                 the IEEE-754 Standard for floating-point arithmetic. It
                 utilizes a novel BCD magnitude comparator with
                 logarithmic delay and it supports 64-bit decimal
                 floating-point numbers. Area and delay results are
                 examined for an implementation in TSMC SCN6M SCMOS
                 technology.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Chang:2006:DAR
author: Chin-Chen Chang and Yeu-Pong Lai
title: A division algorithm for residue numbers
journal: j-APPL-MATH-COMP
volume: 172
number: 1
pages: 368--378
day: 1
month: jan
monthnumber: 1
year: 2006
CODEN: AMHCBQ
DOI: https://doi.org/10.1016/j.amc.2005.02.008
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Sat Jul 12 09:02:52 MDT 2008
bibtimestamp: 2008.07.12 09:02:52 MDT
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: Chin-Chen Chang and Yeu-Pong Lai
rawtitle: A division algorithm for residue numbers
abstract:
In the residue number system, modular multiplication, modular addition, and modular subtraction are closure operations. However, modular division is also important for applying the residue number system. Inspired by Gamberger's work, we create a division operation to be used in residue number system. In Gamberger's scheme, the transformation from residues to a binary integer is required for keeping the remainder. To eliminate the overhead in transformation, our scheme uses only the residues so that the computing efficiency can be improved. Besides, we also provide an efficient way to find a multiplicative inverse.

rawabstract:
In the residue number system, modular multiplication, modular addition, and modular subtraction are closure operations. However, modular division is also important for applying the residue number system. Inspired by Gamberger's work, we create a division operation to be used in residue number system. In Gamberger's scheme, the transformation from residues to a binary integer is required for keeping the remainder. To eliminate the overhead in transformation, our scheme uses only the residues so that the computing efficiency can be improved. Besides, we also provide an efficient way to find a multiplicative inverse.

entry:
@Article{Chang:2006:DAR,
  author =       "Chin-Chen Chang and Yeu-Pong Lai",
  title =        "A division algorithm for residue numbers",
  journal =      j-APPL-MATH-COMP,
  volume =       "172",
  number =       "1",
  pages =        "368--378",
  day =          "1",
  month =        jan,
  year =         "2006",
  CODEN =        "AMHCBQ",
  DOI =          "https://doi.org/10.1016/j.amc.2005.02.008",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Sat Jul 12 09:02:52 MDT 2008",
  bibsource =    "http://www.sciencedirect.com/science/journal/00963003;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In the residue number system, modular multiplication,
                 modular addition, and modular subtraction are closure
                 operations. However, modular division is also important
                 for applying the residue number system. Inspired by
                 Gamberger's work, we create a division operation to be
                 used in residue number system. In Gamberger's scheme,
                 the transformation from residues to a binary integer is
                 required for keeping the remainder. To eliminate the
                 overhead in transformation, our scheme uses only the
                 residues so that the computing efficiency can be
                 improved. Besides, we also provide an efficient way to
                 find a multiplicative inverse.",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
}


bibtype: inproceedings
filename: fparith.bib
label: Choi:2006:DCB
author: Sung Woo Choi and Sung-il Pae and Hyungju Park and Chee Yap
title: Decidability of Collision between a Helical Motion and an Algebraic Motion
crossref: Anonymous:2006:PCR
pages: ??--??
year: 2006
bibdate: Tue Jun 27 10:28:05 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.06.27 10:28:05 ???
acknowledgement: ack-nhfb
rawauthor: Sung Woo Choi and Sung-il Pae and Hyungju Park and Chee Yap
rawtitle: Decidability of Collision between a Helical Motion and an Algebraic Motion
entry:
@InProceedings{Choi:2006:DCB,
  author =       "Sung Woo Choi and Sung-il Pae and Hyungju Park and
                 Chee Yap",
  title =        "Decidability of Collision between a Helical Motion and
                 an Algebraic Motion",
  crossref =     "Anonymous:2006:PCR",
  pages =        "??--??",
  year =         "2006",
  bibdate =      "Tue Jun 27 10:28:05 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Cornea:2006:SII
author: Marius Cornea and Cristina Anderson
title: Software Implementation of the IEEE 754R Decimal Floating-Point Architecture
pages: ??--??
day: 10--12
month: jul
monthnumber: 7
year: 2006
bibdate: Wed Nov 22 21:47:16 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.11.22 21:47:16 ???
note: See also cite Anonymous:2006:RSI.
URL: http://rnc7.loria.fr/cornea_poster.pdf
keywords: BID encoding; decimal floating-point arithmetic
acknowledgement: ack-nhfb
howpublished: World-Wide Web slides
rawauthor: Marius Cornea and Cristina Anderson
rawnote: See also \cite{Anonymous:2006:RSI}.
rawtitle: Software Implementation of the {IEEE 754R} Decimal Floating-Point Architecture
entry:
@Misc{Cornea:2006:SII,
  author =       "Marius Cornea and Cristina Anderson",
  title =        "Software Implementation of the {IEEE 754R} Decimal
                 Floating-Point Architecture",
  howpublished = "World-Wide Web slides",
  day =          "10--12",
  month =        jul,
  year =         "2006",
  bibdate =      "Wed Nov 22 21:47:16 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See also \cite{Anonymous:2006:RSI}.",
  URL =          "http://rnc7.loria.fr/cornea_poster.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "BID encoding; decimal floating-point arithmetic",
}


bibtype: manual
filename: fparith.bib
label: Cowlishaw:2006:DCL
author: Mike Cowlishaw
title: The decNumber C library
organization: pub-IBM
address: pub-IBM:adr
pages: ??--??
day: 22
month: nov
monthnumber: 11
year: 2006
bibdate: Fri Apr 20 08:02:33 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.04.20 08:02:33 ???
note: Version 3.37
URL: http://download.icu-project.org/ex/files/decNumber/decNumber-icu-337.zip
keywords: decimal floating-point arithmetic; DPD encoding
acknowledgement: ack-nhfb
rawauthor: Mike Cowlishaw
rawnote: Version 3.37
rawtitle: The {decNumber C} library
entry:
@Manual{Cowlishaw:2006:DCL,
  author =       "Mike Cowlishaw",
  title =        "The {decNumber C} library",
  organization = pub-IBM,
  address =      pub-IBM:adr,
  day =          "22",
  month =        nov,
  year =         "2006",
  bibdate =      "Fri Apr 20 08:02:33 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Version 3.37",
  URL =          "http://download.icu-project.org/ex/files/decNumber/decNumber-icu-337.zip",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic; DPD encoding",
}


bibtype: article
filename: fparith.bib
label: Dahab:2006:SMU
author: R. Dahab and D. Hankerson and F. Hu and M. Long and J. Lopez and A. Menezes
title: Software multiplication using Gaussian normal bases
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 8
pages: 974--984
month: aug
monthnumber: 8
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.132
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:55 MDT 2011
bibtimestamp: 2011.07.04 15:35:55 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650195
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: R. Dahab and D. Hankerson and F. Hu and M. Long and J. Lopez and A. Menezes
rawtitle: Software multiplication using {Gaussian} normal bases
entry:
@Article{Dahab:2006:SMU,
  author =       "R. Dahab and D. Hankerson and F. Hu and M. Long and J.
                 Lopez and A. Menezes",
  title =        "Software multiplication using {Gaussian} normal
                 bases",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "8",
  pages =        "974--984",
  month =        aug,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.132",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:55 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650195",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: deDinechin:2006:STP
author: Florent de Dinechin and Sergey Maidanov
title: Software techniques for perfect elementary functions in floating-point interval arithmetic
crossref: Anonymous:2006:PCR
pages: ??--??
year: 2006
bibdate: Tue Jun 27 10:28:05 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.06.27 10:28:05 ???
keywords: elementary functions
acknowledgement: ack-nhfb
rawauthor: Florent de Dinechin and Sergey Maidanov
rawtitle: Software techniques for perfect elementary functions in floating-point interval arithmetic
entry:
@InProceedings{deDinechin:2006:STP,
  author =       "Florent de Dinechin and Sergey Maidanov",
  title =        "Software techniques for perfect elementary functions
                 in floating-point interval arithmetic",
  crossref =     "Anonymous:2006:PCR",
  pages =        "??--??",
  year =         "2006",
  bibdate =      "Tue Jun 27 10:28:05 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "elementary functions",
}


bibtype: article
filename: fparith.bib
label: Demmel:2006:EBE
title: Error bounds from extra-precise iterative refinement
journal: j-TOMS
volume: 32
number: 2
pages: 325--351
month: jun
monthnumber: 6
year: 2006
CODEN: ACMSCU
DOI: https://doi.org/10.1145/1141885.1141894
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Wed Aug 23 10:29:48 MDT 2006
bibtimestamp: 2006.08.23 10:29:48 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/toms
rawtitle: Error bounds from extra-precise iterative refinement
author:
James Demmel and Yozo Hida and William Kahan and Xiaoye S. Li and Sonil Mukherjee and E. Jason Riedy

bibsource:
http://www.acm.org/pubs/contents/journals/toms/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
We present the design and testing of an algorithm for iterative refinement of the solution of linear equations where the residual is computed with extra precision. This algorithm was originally proposed in 1948 and analyzed in the 1960s as a means to compute very accurate solutions to all but the most ill-conditioned linear systems. However, two obstacles have until now prevented its adoption in standard subroutine libraries like LAPACK: (1) There was no standard way to access the higher precision arithmetic needed to compute residuals, and (2) it was unclear how to compute a reliable error bound for the computed solution. The completion of the new BLAS Technical Forum Standard has essentially removed the first obstacle. To overcome the second obstacle, we show how the application of iterative refinement can be used to compute an error bound in any norm at small cost and use this to compute both an error bound in the usual infinity norm, and a componentwise relative error bound. We report extensive test results on over $ 6.2 $ million matrices of dimensions $5$, $ 10$, $ 100$, and $ 1000$. As long as a normwise (componentwise) condition number computed by the algorithm is less than $ 1 / m a x 10, sqrt n varepsilon _w$, the computed normwise (componentwise) error bound is at most $ 2 m a x 10, sqrt n cdot varepsilon _w$, and indeed bounds the true error. Here, $n$ is the matrix dimension and $ varepsilon _w = 2^-24$ is the working precision. Residuals were computed in double precision (53 bits of precision). In other words, the algorithm always computed a tiny error at negligible extra cost for most linear systems. For worse conditioned problems (which we can detect using condition estimation), we obtained small correct error bounds in over 90% of cases.

rawabstract:
We present the design and testing of an algorithm for iterative refinement of the solution of linear equations where the residual is computed with extra precision. This algorithm was originally proposed in 1948 and analyzed in the 1960s as a means to compute very accurate solutions to all but the most ill-conditioned linear systems. However, two obstacles have until now prevented its adoption in standard subroutine libraries like LAPACK: (1) There was no standard way to access the higher precision arithmetic needed to compute residuals, and (2) it was unclear how to compute a reliable error bound for the computed solution. The completion of the new BLAS Technical Forum Standard has essentially removed the first obstacle. To overcome the second obstacle, we show how the application of iterative refinement can be used to compute an error bound in any norm at small cost and use this to compute both an error bound in the usual infinity norm, and a componentwise relative error bound. We report extensive test results on over $ 6.2 $ million matrices of dimensions $5$, $ 10$, $ 100$, and $ 1000$. As long as a normwise (componentwise) condition number computed by the algorithm is less than $ 1 / m a x \{ 10, \sqrt {n} \} \varepsilon_w$, the computed normwise (componentwise) error bound is at most $ 2 m a x \{ 10, \sqrt {n} \} \cdot \varepsilon_w$, and indeed bounds the true error. Here, $n$ is the matrix dimension and $ \varepsilon_w = 2^{-24}$ is the working precision. Residuals were computed in double precision (53 bits of precision). In other words, the algorithm always computed a tiny error at negligible extra cost for most linear systems. For worse conditioned problems (which we can detect using condition estimation), we obtained small correct error bounds in over 90\% of cases.

rawauthor:
James Demmel and Yozo Hida and William Kahan and Xiaoye S. Li and Sonil Mukherjee and E. Jason Riedy

entry:
@Article{Demmel:2006:EBE,
  author =       "James Demmel and Yozo Hida and William Kahan and
                 Xiaoye S. Li and Sonil Mukherjee and E. Jason Riedy",
  title =        "Error bounds from extra-precise iterative refinement",
  journal =      j-TOMS,
  volume =       "32",
  number =       "2",
  pages =        "325--351",
  month =        jun,
  year =         "2006",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/1141885.1141894",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Wed Aug 23 10:29:48 MDT 2006",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  abstract =     "We present the design and testing of an algorithm for
                 iterative refinement of the solution of linear
                 equations where the residual is computed with extra
                 precision. This algorithm was originally proposed in
                 1948 and analyzed in the 1960s as a means to compute
                 very accurate solutions to all but the most
                 ill-conditioned linear systems. However, two obstacles
                 have until now prevented its adoption in standard
                 subroutine libraries like LAPACK: (1) There was no
                 standard way to access the higher precision arithmetic
                 needed to compute residuals, and (2) it was unclear how
                 to compute a reliable error bound for the computed
                 solution. The completion of the new BLAS Technical
                 Forum Standard has essentially removed the first
                 obstacle. To overcome the second obstacle, we show how
                 the application of iterative refinement can be used to
                 compute an error bound in any norm at small cost and
                 use this to compute both an error bound in the usual
                 infinity norm, and a componentwise relative error
                 bound. We report extensive test results on over $ 6.2 $
                 million matrices of dimensions $5$, $ 10$, $ 100$, and
                 $ 1000$. As long as a normwise (componentwise)
                 condition number computed by the algorithm is less than
                 $ 1 / m a x \{ 10, \sqrt {n} \} \varepsilon_w$, the
                 computed normwise (componentwise) error bound is at
                 most $ 2 m a x \{ 10, \sqrt {n} \} \cdot
                 \varepsilon_w$, and indeed bounds the true error. Here,
                 $n$ is the matrix dimension and $ \varepsilon_w =
                 2^{-24}$ is the working precision. Residuals were
                 computed in double precision (53 bits of precision). In
                 other words, the algorithm always computed a tiny error
                 at negligible extra cost for most linear systems. For
                 worse conditioned problems (which we can detect using
                 condition estimation), we obtained small correct error
                 bounds in over 90\% of cases.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Deng:2006:IMM
author: Rui Deng and Yujie Zhou
title: Improvement to Montgomery Modular Inverse Algorithm
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 9
pages: 1207--1210
month: sep
monthnumber: 9
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.150
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:56 MDT 2011
bibtimestamp: 2011.07.04 15:35:56 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1668048
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Rui Deng and Yujie Zhou
rawtitle: Improvement to {Montgomery} Modular Inverse Algorithm
entry:
@Article{Deng:2006:IMM,
  author =       "Rui Deng and Yujie Zhou",
  title =        "Improvement to {Montgomery} Modular Inverse
                 Algorithm",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "9",
  pages =        "1207--1210",
  month =        sep,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.150",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:56 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1668048",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: book
filename: fparith.bib
label: Deschamps:2006:SAC
author: Jean-Pierre Deschamps and Gery Jean Antoine Bioul and Gustavo D. Sutter
title: Synthesis of arithmetic circuits: FPGA, ASIC, and embedded systems
publisher: pub-WILEY
address: pub-WILEY:adr
pages: xix + 556
year: 2006
ISBN: 0-471-68783-9 (hardcover) OR 0471687839 (hardcover)
ISBN13: 978-0-471-68783-2 (hardcover) OR 9780471687832 (hardcover)
LCCN: TK7895.A65 D47 2006
bibdate: Wed Oct 1 10:16:56 MDT 2014
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; z3950.loc.gov:7090/Voyager
bibtimestamp: 2014.10.01 10:16:56 MDT
subject: Computer arithmetic and logic units; Digital electronics; Embedded computer systems
acknowledgement: ack-nhfb
authordates: 1945--
rawauthor: Jean-Pierre Deschamps and G{\'e}ry Jean Antoine Bioul and Gustavo D. Sutter
rawtitle: Synthesis of arithmetic circuits: {FPGA}, {ASIC}, and embedded systems
URL:
http://www.loc.gov/catdir/enhancements/fy0621/2005003237-b.html; http://www.loc.gov/catdir/enhancements/fy0621/2005003237-d.html; http://www.loc.gov/catdir/toc/ecip057/2005003237.html

TOC:
Mathematical background Number representation Arithmetic operations: addition and subtraction Arithmetic operations: multiplication Arithmetic operations: division Other arithmetic operations Finite field operations Hardware platforms Circuit synthesis: general principles Adders and subtractors Multipliers Dividers Other arithmetic operators Circuits for finite field operations Floating-point unit

rawTOC:
Mathematical background \\ Number representation \\ Arithmetic operations: addition and subtraction \\ Arithmetic operations: multiplication \\ Arithmetic operations: division \\ Other arithmetic operations \\ Finite field operations \\ Hardware platforms \\ Circuit synthesis: general principles \\ Adders and subtractors \\ Multipliers \\ Dividers \\ Other arithmetic operators \\ Circuits for finite field operations \\ Floating-point unit

entry:
@Book{Deschamps:2006:SAC,
  author =       "Jean-Pierre Deschamps and G{\'e}ry Jean Antoine Bioul
                 and Gustavo D. Sutter",
  title =        "Synthesis of arithmetic circuits: {FPGA}, {ASIC}, and
                 embedded systems",
  publisher =    pub-WILEY,
  address =      pub-WILEY:adr,
  pages =        "xix + 556",
  year =         "2006",
  ISBN =         "0-471-68783-9 (hardcover)",
  ISBN-13 =      "978-0-471-68783-2 (hardcover)",
  LCCN =         "TK7895.A65 D47 2006",
  bibdate =      "Wed Oct 1 10:16:56 MDT 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 z3950.loc.gov:7090/Voyager",
  URL =          "http://www.loc.gov/catdir/enhancements/fy0621/2005003237-b.html;
                 http://www.loc.gov/catdir/enhancements/fy0621/2005003237-d.html;
                 http://www.loc.gov/catdir/toc/ecip057/2005003237.html",
  acknowledgement = ack-nhfb,
  author-dates = "1945--",
  subject =      "Computer arithmetic and logic units; Digital
                 electronics; Embedded computer systems",
  tableofcontents = "Mathematical background \\
                 Number representation \\
                 Arithmetic operations: addition and subtraction \\
                 Arithmetic operations: multiplication \\
                 Arithmetic operations: division \\
                 Other arithmetic operations \\
                 Finite field operations \\
                 Hardware platforms \\
                 Circuit synthesis: general principles \\
                 Adders and subtractors \\
                 Multipliers \\
                 Dividers \\
                 Other arithmetic operators \\
                 Circuits for finite field operations \\
                 Floating-point unit",
}


bibtype: misc
filename: fparith.bib
label: Detrey:2006:FVL
author: Jeremie Detrey and Florent de Dinechin
title: FPLibrary. A VHDL library of parametrisable floating-point and LNS operators for FPGA
pages: xix + 556
year: 2006
bibdate: Sat Oct 9 12:42:00 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 12:42:00 ???
note: The FPLibrary has been superceded by the FloPoCo project cite deDinechin:2010:FGA.
URL: http://www.ens-lyon.fr/LIP/Arenaire/Ware/FPLibrary/
acknowledgement: ack-nhfb
howpublished: Web site and source code.
rawauthor: J{\'e}r{\'e}mie Detrey and Florent de Dinechin
rawnote: The FPLibrary has been superceded by the FloPoCo project \cite{deDinechin:2010:FGA}.
rawtitle: {FPLibrary}. {A} {VHDL} library of parametrisable floating-point and {LNS} operators for {FPGA}
entry:
@Misc{Detrey:2006:FVL,
  author =       "J{\'e}r{\'e}mie Detrey and Florent de Dinechin",
  title =        "{FPLibrary}. {A} {VHDL} library of parametrisable
                 floating-point and {LNS} operators for {FPGA}",
  howpublished = "Web site and source code.",
  year =         "2006",
  bibdate =      "Sat Oct 9 12:42:00 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "The FPLibrary has been superceded by the FloPoCo
                 project \cite{deDinechin:2010:FGA}.",
  URL =          "http://www.ens-lyon.fr/LIP/Arenaire/Ware/FPLibrary/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Dietz:2006:FPC
author: Hank Dietz and Bill Dieter and Randy Fisher and Kungyen Chang
title: Floating-Point Computation with Just Enough Accuracy
journal: j-LECT-NOTES-COMP-SCI
volume: 3991
pages: 226--233
year: 2006
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Wed Jan 06 09:42:37 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.01.06 09:42:37 ???
note: ICCS 2006, Part I, conference proceedings.
URL: http://aggregate.org/NPAR/iccs2006.pdf
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Hank Dietz and Bill Dieter and Randy Fisher and Kungyen Chang
rawnote: ICCS 2006, Part I, conference proceedings.
rawtitle: Floating-Point Computation with Just Enough Accuracy
abstract:
Most mathematical formulae are defined in terms of operations on real numbers, but computers can only operate on numeric values with finite precision and range. Using floating-point values as real numbers does not clearly identify the precision with which each value must be represented. Too little precision yields inaccurate results; too much wastes computational resources.par The popularity of multimedia applications has made fast hardware support for low-precision floating-point arithmetic common in Digital Signal Processors (DSPs), SIMD Within A Register (SWAR) instruction set extensions for general purpose processors, and in Graphics Processing Units (GPUs). In this paper, we describe a simple approach by which the speed of these low-precision operations can be speculatively employed to meet user-specified accuracy constraints. Where the native precision(s) yield insufficient accuracy, a simple technique is used to efficiently synthesize enhanced precision using pairs of native values.

keywords:
Digital Signal Processors (DSPs); double-double arithmetic; native pair; pair-precision arithmetic; SIMD Within A Register (SWAR)

rawabstract:
Most mathematical formulae are defined in terms of operations on real numbers, but computers can only operate on numeric values with finite precision and range. Using floating-point values as real numbers does not clearly identify the precision with which each value must be represented. Too little precision yields inaccurate results; too much wastes computational resources.\par The popularity of multimedia applications has made fast hardware support for low-precision floating-point arithmetic common in Digital Signal Processors (DSPs), SIMD Within A Register (SWAR) instruction set extensions for general purpose processors, and in Graphics Processing Units (GPUs). In this paper, we describe a simple approach by which the speed of these low-precision operations can be speculatively employed to meet user-specified accuracy constraints. Where the native precision(s) yield insufficient accuracy, a simple technique is used to efficiently synthesize enhanced precision using pairs of native values.

entry:
@Article{Dietz:2006:FPC,
  author =       "Hank Dietz and Bill Dieter and Randy Fisher and
                 Kungyen Chang",
  title =        "Floating-Point Computation with Just Enough Accuracy",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "3991",
  pages =        "226--233",
  year =         "2006",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Wed Jan 06 09:42:37 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "ICCS 2006, Part I, conference proceedings.",
  URL =          "http://aggregate.org/NPAR/iccs2006.pdf",
  abstract =     "Most mathematical formulae are defined in terms of
                 operations on real numbers, but computers can only
                 operate on numeric values with finite precision and
                 range. Using floating-point values as real numbers does
                 not clearly identify the precision with which each
                 value must be represented. Too little precision yields
                 inaccurate results; too much wastes computational
                 resources.\par

                 The popularity of multimedia applications has made fast
                 hardware support for low-precision floating-point
                 arithmetic common in Digital Signal Processors (DSPs),
                 SIMD Within A Register (SWAR) instruction set
                 extensions for general purpose processors, and in
                 Graphics Processing Units (GPUs). In this paper, we
                 describe a simple approach by which the speed of these
                 low-precision operations can be speculatively employed
                 to meet user-specified accuracy constraints. Where the
                 native precision(s) yield insufficient accuracy, a
                 simple technique is used to efficiently synthesize
                 enhanced precision using pairs of native values.",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  keywords =     "Digital Signal Processors (DSPs); double-double
                 arithmetic; native pair; pair-precision arithmetic;
                 SIMD Within A Register (SWAR)",
}


bibtype: inproceedings
filename: fparith.bib
label: Diniz:2006:DFP
author: P. C. Diniz and G. Govindu
title: Design of field-programmable dual-precision floating-point arithmetic units
crossref: Bertels:2006:FPI
pages: 1--4
year: 2006
DOI: https://doi.org/10.1109/FPL.2006.311302
bibdate: Sat Oct 9 12:37:10 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 12:37:10 ???
acknowledgement: ack-nhfb
rawauthor: P. C. Diniz and G. Govindu
rawtitle: Design of field-programmable dual-precision floating-point arithmetic units
abstract:
The growth in FPGA capacity and the inclusion of embedded arithmetic cores has enabled the use of these devices for general purpose floating-point computing. Despite their clock rate handicap with respect to contemporary general-purpose processors, these devices can be field-programmable to meet the precision requirements and operator-level parallelism of a specific computation. In this paper we describe and evaluate the performance of dual-precision, pipelined, floating-point arithmetic cores for addition, multiplication and division. Each of these arithmetic cores can be switched at run-time to perform either one double-precision operation, or with the same hardware resources, perform two single-precision operations. We also implemented quad-precision cores which can be switched to perform either one quad-precision operation or two double-precision operations. As an application of these cores, we describe and evaluate the performance potential of a custom, but flexible, vector processing units as part of a system-level architecture targeting a Xilinx Virtex-II Prom 100 FPGA device connected to multiple SRAM banks.

rawabstract:
The growth in FPGA capacity and the inclusion of embedded arithmetic cores has enabled the use of these devices for general purpose floating-point computing. Despite their clock rate handicap with respect to contemporary general-purpose processors, these devices can be field-programmable to meet the precision requirements and operator-level parallelism of a specific computation. In this paper we describe and evaluate the performance of dual-precision, pipelined, floating-point arithmetic cores for addition, multiplication and division. Each of these arithmetic cores can be switched at run-time to perform either one double-precision operation, or with the same hardware resources, perform two single-precision operations. We also implemented quad-precision cores which can be switched to perform either one quad-precision operation or two double-precision operations. As an application of these cores, we describe and evaluate the performance potential of a custom, but flexible, vector processing units as part of a system-level architecture targeting a Xilinx Virtex-II Prom 100 FPGA device connected to multiple SRAM banks.

entry:
@InProceedings{Diniz:2006:DFP,
  author =       "P. C. Diniz and G. Govindu",
  title =        "Design of field-programmable dual-precision
                 floating-point arithmetic units",
  crossref =     "Bertels:2006:FPI",
  pages =        "1--4",
  year =         "2006",
  DOI =          "https://doi.org/10.1109/FPL.2006.311302",
  bibdate =      "Sat Oct 9 12:37:10 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The growth in FPGA capacity and the inclusion of
                 embedded arithmetic cores has enabled the use of these
                 devices for general purpose floating-point computing.
                 Despite their clock rate handicap with respect to
                 contemporary general-purpose processors, these devices
                 can be field-programmable to meet the precision
                 requirements and operator-level parallelism of a
                 specific computation. In this paper we describe and
                 evaluate the performance of dual-precision, pipelined,
                 floating-point arithmetic cores for addition,
                 multiplication and division. Each of these arithmetic
                 cores can be switched at run-time to perform either one
                 double-precision operation, or with the same hardware
                 resources, perform two single-precision operations. We
                 also implemented quad-precision cores which can be
                 switched to perform either one quad-precision operation
                 or two double-precision operations. As an application
                 of these cores, we describe and evaluate the
                 performance potential of a custom, but flexible, vector
                 processing units as part of a system-level architecture
                 targeting a Xilinx Virtex-II Prom 100 FPGA device
                 connected to multiple SRAM banks.",
  acknowledgement = ack-nhfb,
  xxpages =      "733--736",
}


bibtype: article
filename: fparith.bib
label: Enge:2006:CCP
author: Andreas Enge
title: The complexity of class polynomial computation via floating point approximations
journal: arXiv.org
pages: ??--??
day: 24
month: jan
monthnumber: 1
year: 2006
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
note: Published in Mathematics of Computation 78, bf 266 (2009) 1089--1107.
URL: http://arxiv.org/abs/cs/0601104
subject: Numerical Analysis (cs.NA); Symbolic Computation (cs.SC); Number Theory (math.NT)
acknowledgement: ack-nhfb
rawauthor: Andreas Enge
rawnote: Published in Mathematics of Computation 78, {\bf 266} (2009) 1089--1107.
rawtitle: The complexity of class polynomial computation via floating point approximations
abstract:
We analyse the complexity of computing class polynomials, that are an important ingredient for CM constructions of elliptic curves, via complex floating point approximations of their roots. The heart of the algorithm is the evaluation of modular functions in several arguments. The fastest one of the presented approaches uses a technique devised by Dupont to evaluate modular functions by Newton iterations on an expression involving the arithmetic-geometric mean. It runs in time $ O (|D| log ^5 |D| log log |D|) = O (|D|^1 + epsilon ) = O (h^2 + epsilon ) $ for any $ epsilon > 0 $, where $D$ is the CM discriminant and $h$ is the degree of the class polynomial. Another fast algorithm uses multipoint evaluation techniques known from symbolic computation; its asymptotic complexity is worse by a factor of $ log |D|$. Up to logarithmic factors, this running time matches the size of the constructed polynomials. The estimate also relies on a new result concerning the complexity of enumerating the class group of an imaginary-quadratic order and on a rigorously proven upper bound for the height of class polynomials.

rawabstract:
We analyse the complexity of computing class polynomials, that are an important ingredient for CM constructions of elliptic curves, via complex floating point approximations of their roots. The heart of the algorithm is the evaluation of modular functions in several arguments. The fastest one of the presented approaches uses a technique devised by Dupont to evaluate modular functions by Newton iterations on an expression involving the arithmetic-geometric mean. It runs in time $ O (|D| \log^5 |D| \log \log |D|) = O (|D|^{1 + \epsilon }) = O (h^{2 + \epsilon }) $ for any $ \epsilon > 0 $, where $D$ is the CM discriminant and $h$ is the degree of the class polynomial. Another fast algorithm uses multipoint evaluation techniques known from symbolic computation; its asymptotic complexity is worse by a factor of $ \log |D|$. Up to logarithmic factors, this running time matches the size of the constructed polynomials. The estimate also relies on a new result concerning the complexity of enumerating the class group of an imaginary-quadratic order and on a rigorously proven upper bound for the height of class polynomials.

entry:
@Article{Enge:2006:CCP,
  author =       "Andreas Enge",
  title =        "The complexity of class polynomial computation via
                 floating point approximations",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "24",
  month =        jan,
  year =         "2006",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Published in Mathematics of Computation 78, {\bf 266}
                 (2009) 1089--1107.",
  URL =          "http://arxiv.org/abs/cs/0601104",
  abstract =     "We analyse the complexity of computing class
                 polynomials, that are an important ingredient for CM
                 constructions of elliptic curves, via complex floating
                 point approximations of their roots. The heart of the
                 algorithm is the evaluation of modular functions in
                 several arguments. The fastest one of the presented
                 approaches uses a technique devised by Dupont to
                 evaluate modular functions by Newton iterations on an
                 expression involving the arithmetic-geometric mean. It
                 runs in time $ O (|D| \log^5 |D| \log \log |D|) = O
                 (|D|^{1 + \epsilon }) = O (h^{2 + \epsilon }) $ for any
                 $ \epsilon > 0 $, where $D$ is the CM discriminant and
                 $h$ is the degree of the class polynomial. Another fast
                 algorithm uses multipoint evaluation techniques known
                 from symbolic computation; its asymptotic complexity is
                 worse by a factor of $ \log |D|$. Up to logarithmic
                 factors, this running time matches the size of the
                 constructed polynomials. The estimate also relies on a
                 new result concerning the complexity of enumerating the
                 class group of an imaginary-quadratic order and on a
                 rigorously proven upper bound for the height of class
                 polynomials.",
  acknowledgement = ack-nhfb,
  subject =      "Numerical Analysis (cs.NA); Symbolic Computation
                 (cs.SC); Number Theory (math.NT)",
}


bibtype: article
filename: fparith.bib
label: Fan:2006:RBM
author: H. Fan and M. A. Hasan
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 9
pages: 1202--1206
month: sep
monthnumber: 9
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.152
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:56 MDT 2011
bibtimestamp: 2011.07.04 15:35:56 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1668047
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Fan and M. A. Hasan
title:
Relationship between $ mathrm GF(2^m) $ Montgomery and Shifted Polynomial Basis Multiplication Algorithms

rawtitle:
Relationship between {$ \mathrm {GF}(2^m) $} {Montgomery} and Shifted Polynomial Basis Multiplication Algorithms

entry:
@Article{Fan:2006:RBM,
  author =       "H. Fan and M. A. Hasan",
  title =        "Relationship between {$ \mathrm {GF}(2^m) $}
                 {Montgomery} and Shifted Polynomial Basis
                 Multiplication Algorithms",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "9",
  pages =        "1202--1206",
  month =        sep,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.152",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:56 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1668047",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Feldstein:2006:GTO
author: Alan Feldstein and Peter R. Turner
journal: j-APPL-NUM-MATH
volume: 56
number: 3--4
pages: 517--532
month: mar
monthnumber: 3
year: 2006
CODEN: ANMAEL
ISSN: 0168-9274 (print), 1873-5460 (electronic) OR 01689274 (print), 18735460 (electronic)
ISSNL: 0168-9274 OR 01689274
bibdate: Tue Aug 24 11:17:20 MDT 2010
bibtimestamp: 2010.08.24 11:17:20 MDT
fjournal: Applied Numerical Mathematics: Transactions of IMACS
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/01689274
rawauthor: Alan Feldstein and Peter R. Turner
title:
Gradual and tapered overflow and underflow: a functional differential equation and its approximation

bibsource:
http://www.sciencedirect.com/science/journal/01689274; https://www.math.utah.edu/pub/tex/bib/applnummath.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
Gradual and tapered overflow and underflow: a functional differential equation and its approximation

entry:
@Article{Feldstein:2006:GTO,
  author =       "Alan Feldstein and Peter R. Turner",
  title =        "Gradual and tapered overflow and underflow: a
                 functional differential equation and its
                 approximation",
  journal =      j-APPL-NUM-MATH,
  volume =       "56",
  number =       "3--4",
  pages =        "517--532",
  month =        mar # "\slash " # apr,
  year =         "2006",
  CODEN =        "ANMAEL",
  ISSN =         "0168-9274 (print), 1873-5460 (electronic)",
  ISSN-L =       "0168-9274",
  bibdate =      "Tue Aug 24 11:17:20 MDT 2010",
  bibsource =    "http://www.sciencedirect.com/science/journal/01689274;
                 https://www.math.utah.edu/pub/tex/bib/applnummath.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Numerical Mathematics: Transactions of IMACS",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01689274",
}


bibtype: article
filename: fparith.bib
label: Gandhi:2006:DRA
author: Rajiv Gandhi and Samir Khuller and Srinivasan Parthasarathy and Aravind Srinivasan
title: Dependent rounding and its applications to approximation algorithms
journal: j-J-ACM
volume: 53
number: 3
pages: 324--360
month: may
monthnumber: 5
year: 2006
CODEN: JACOAH
DOI: https://doi.org/10.1145/1147954.1147956
ISSN: 0004-5411 (print), 1557-735X (electronic) OR 00045411 (print), 1557735X (electronic)
ISSNL: 0004-5411 OR 00045411
bibdate: Wed Aug 23 06:38:20 MDT 2006
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.08.23 06:38:20 MDT
fjournal: Journal of the ACM
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J401
rawauthor: Rajiv Gandhi and Samir Khuller and Srinivasan Parthasarathy and Aravind Srinivasan
rawtitle: Dependent rounding and its applications to approximation algorithms
entry:
@Article{Gandhi:2006:DRA,
  author =       "Rajiv Gandhi and Samir Khuller and Srinivasan
                 Parthasarathy and Aravind Srinivasan",
  title =        "Dependent rounding and its applications to
                 approximation algorithms",
  journal =      j-J-ACM,
  volume =       "53",
  number =       "3",
  pages =        "324--360",
  month =        may,
  year =         "2006",
  CODEN =        "JACOAH",
  DOI =          "https://doi.org/10.1145/1147954.1147956",
  ISSN =         "0004-5411 (print), 1557-735X (electronic)",
  ISSN-L =       "0004-5411",
  bibdate =      "Wed Aug 23 06:38:20 MDT 2006",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of the ACM",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J401",
}


bibtype: article
filename: fparith.bib
label: Gochman:2006:IIC
author: Simcha Gochman and Avi Mendelson and Alon Naveh and Efraim Rotem
title: Introduction to Intel Core Duo Processor Architecture
journal: j-INTEL-TECH-J
volume: 10
number: 2
pages: 89--97
day: 15
month: may
monthnumber: 5
year: 2006
DOI: https://doi.org/10.1535/itj.1002
ISSN: 1535-766X OR 1535766X
bibdate: Tue Jun 20 07:47:25 2006
bibtimestamp: 2006.06.20 07:47:25 ???
acknowledgement: ack-nhfb
rawauthor: Simcha Gochman and Avi Mendelson and Alon Naveh and Efraim Rotem
rawtitle: Introduction to {Intel Core Duo} Processor Architecture
bibsource:
ftp://download.intel.com/technology/itj/2006/volume10issue02/vol10_iss02.pdf; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://developer.intel.com/technology/itj/2006/volume10issue02/art01_Intro_to_Core_Duo/p01_abstract.htm

remark:
From p. 91: ``Another bottleneck that was discovered was the handling of the floating point (FP) Control Word (CW). The FP CW is part of the x87 state and was usually viewed as `constant'; namely it is loaded once at the beginning and stays constant throughout the program. This is indeed the way the FP CW is used by most of the programs. However there are some FP applications that manipulate the `rounding control' which is located in this register: the default rounding mode is `rounding to nearest even' but before converting results to fixed point, some applications change the round control to `chop' (this is the rule with C programs for example). Such behavior was treated rather inefficiently by the Pentium M core: each manipulation of the FP CW was effectively stalling the pipeline until its completion. The Intel Core Duo core introduced a new renaming mechanism for the FP CW so that four different versions of this register can coexist on the fly without stalling the machine.''

entry:
@Article{Gochman:2006:IIC,
  author =       "Simcha Gochman and Avi Mendelson and Alon Naveh and
                 Efraim Rotem",
  title =        "Introduction to {Intel Core Duo} Processor
                 Architecture",
  journal =      j-INTEL-TECH-J,
  volume =       "10",
  number =       "2",
  pages =        "89--97",
  day =          "15",
  month =        may,
  year =         "2006",
  DOI =          "https://doi.org/10.1535/itj.1002",
  ISSN =         "1535-766X",
  bibdate =      "Tue Jun 20 07:47:25 2006",
  bibsource =    "ftp://download.intel.com/technology/itj/2006/volume10issue02/vol10_iss02.pdf;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://developer.intel.com/technology/itj/2006/volume10issue02/art01_Intro_to_Core_Duo/p01_abstract.htm",
  acknowledgement = ack-nhfb,
  remark =       "From p. 91: ``Another bottleneck that was discovered
                 was the handling of the floating point (FP) Control
                 Word (CW). The FP CW is part of the x87 state and was
                 usually viewed as `constant'; namely it is loaded once
                 at the beginning and stays constant throughout the
                 program. This is indeed the way the FP CW is used by
                 most of the programs. However there are some FP
                 applications that manipulate the `rounding control'
                 which is located in this register: the default rounding
                 mode is `rounding to nearest even' but before
                 converting results to fixed point, some applications
                 change the round control to `chop' (this is the rule
                 with C programs for example). Such behavior was treated
                 rather inefficiently by the Pentium M core: each
                 manipulation of the FP CW was effectively stalling the
                 pipeline until its completion. The Intel Core Duo core
                 introduced a new renaming mechanism for the FP CW so
                 that four different versions of this register can
                 coexist on the fly without stalling the machine.''",
}


bibtype: article
filename: fparith.bib
label: Gok:2006:IMO
author: M. Gok and M. J. Schulte and M. G. Arnold
title: Integer multipliers with overflow detection
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 8
pages: 1062--1066
month: aug
monthnumber: 8
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.126
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:55 MDT 2011
bibtimestamp: 2011.07.04 15:35:55 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650203
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. Gok and M. J. Schulte and M. G. Arnold
rawtitle: Integer multipliers with overflow detection
entry:
@Article{Gok:2006:IMO,
  author =       "M. Gok and M. J. Schulte and M. G. Arnold",
  title =        "Integer multipliers with overflow detection",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "8",
  pages =        "1062--1066",
  month =        aug,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.126",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:55 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650203",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Goubault:2006:SAN
author: Eric Goubault and Sylvie Putot
title: Static analysis of numerical algorithms
crossref: Yi:2006:SAI
pages: 18--34
year: 2006
DOI: https://doi.org/10.1007/11823230_3
bibdate: Sat Apr 01 08:03:10 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.04.01 08:03:10 ???
URL: http://link.springer.com/chapter/10.1007/11823230_3
acknowledgement: ack-nhfb
rawauthor: Eric Goubault and Sylvie Putot
rawtitle: Static analysis of numerical algorithms
entry:
@InProceedings{Goubault:2006:SAN,
  author =       "Eric Goubault and Sylvie Putot",
  title =        "Static analysis of numerical algorithms",
  crossref =     "Yi:2006:SAI",
  pages =        "18--34",
  year =         "2006",
  DOI =          "https://doi.org/10.1007/11823230_3",
  bibdate =      "Sat Apr 01 08:03:10 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer.com/chapter/10.1007/11823230_3",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Graa:2006:IFF
author: Guillaume Da Graca and David Defour
title: Implementation of float-float operators on graphics hardware
crossref: Anonymous:2006:PCR
pages: ??--??
year: 2006
bibdate: Tue Jun 27 10:28:05 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.06.27 10:28:05 ???
acknowledgement: ack-nhfb
rawauthor: Guillaume Da Gra{\c{c}}a and David Defour
rawtitle: Implementation of float-float operators on graphics hardware
entry:
@InProceedings{Graa:2006:IFF,
  author =       "Guillaume Da Gra{\c{c}}a and David Defour",
  title =        "Implementation of float-float operators on graphics
                 hardware",
  crossref =     "Anonymous:2006:PCR",
  pages =        "??--??",
  year =         "2006",
  bibdate =      "Tue Jun 27 10:28:05 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Graca:2006:ODE
author: Daniel S. Graca and Ning Zhong and Jorge Buescu
crossref: Anonymous:2006:PCR
pages: ??--??
year: 2006
bibdate: Tue Jun 27 10:28:05 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.06.27 10:28:05 ???
acknowledgement: ack-nhfb
rawauthor: Daniel S. Gra{\c{c}}a and Ning Zhong and Jorge Buescu
title:
The ordinary differential equation defined by a computable function whose maximal interval of existence is non-computable

rawtitle:
The ordinary differential equation defined by a computable function whose maximal interval of existence is non-computable

entry:
@InProceedings{Graca:2006:ODE,
  author =       "Daniel S. Gra{\c{c}}a and Ning Zhong and Jorge
                 Buescu",
  title =        "The ordinary differential equation defined by a
                 computable function whose maximal interval of existence
                 is non-computable",
  crossref =     "Anonymous:2006:PCR",
  pages =        "??--??",
  year =         "2006",
  bibdate =      "Tue Jun 27 10:28:05 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Graillat:2006:ICH
author: Stef Graillat and Philippe Langlois and Nicolas Louvet
title: Improving the Compensated Horner Scheme with a Fused Multiply and Add
crossref: Haddad:2006:ACP
pages: 1323--1327
year: 2006
DOI: https://doi.org/10.1145/1141277.1141585
bibdate: Sat Feb 26 18:19:47 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.26 18:19:47 ???
acknowledgement: ack-nhfb
rawauthor: Stef Graillat and Philippe Langlois and Nicolas Louvet
rawtitle: Improving the Compensated {Horner} Scheme with a Fused Multiply and Add
abstract:
Several different techniques and softwares intend to improve the accuracy of results computed in a fixed finite precision. Here we focus on a method to improve the accuracy of the polynomial evaluation. It is well known that the use of the Fused Multiply and Add operation available on some microprocessors like Intel Itanium improves slightly the accuracy of the Horner scheme. In this paper, we propose an accurate compensated Horner scheme specially designed to take advantage of the Fused Multiply and Add. We prove that the computed result is as accurate as if computed in twice the working precision. The algorithm we present is fast since it only requires well optimizable floating point operations, performed in the same working precision as the given data.

rawabstract:
Several different techniques and softwares intend to improve the accuracy of results computed in a fixed finite precision. Here we focus on a method to improve the accuracy of the polynomial evaluation. It is well known that the use of the Fused Multiply and Add operation available on some microprocessors like Intel Itanium improves slightly the accuracy of the Horner scheme. In this paper, we propose an accurate compensated Horner scheme specially designed to take advantage of the Fused Multiply and Add. We prove that the computed result is as accurate as if computed in twice the working precision. The algorithm we present is fast since it only requires well optimizable floating point operations, performed in the same working precision as the given data.

entry:
@InProceedings{Graillat:2006:ICH,
  author =       "Stef Graillat and Philippe Langlois and Nicolas
                 Louvet",
  title =        "Improving the Compensated {Horner} Scheme with a Fused
                 Multiply and Add",
  crossref =     "Haddad:2006:ACP",
  pages =        "1323--1327",
  year =         "2006",
  DOI =          "https://doi.org/10.1145/1141277.1141585",
  bibdate =      "Sat Feb 26 18:19:47 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Several different techniques and softwares intend to
                 improve the accuracy of results computed in a fixed
                 finite precision. Here we focus on a method to improve
                 the accuracy of the polynomial evaluation. It is well
                 known that the use of the Fused Multiply and Add
                 operation available on some microprocessors like Intel
                 Itanium improves slightly the accuracy of the Horner
                 scheme. In this paper, we propose an accurate
                 compensated Horner scheme specially designed to take
                 advantage of the Fused Multiply and Add. We prove that
                 the computed result is as accurate as if computed in
                 twice the working precision. The algorithm we present
                 is fast since it only requires well optimizable
                 floating point operations, performed in the same
                 working precision as the given data.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Harrison:2006:FPV
author: John Harrison
title: Floating-point verification using theorem proving
crossref: Cimatti:2006:FMH
pages: 211--242
year: 2006
DOI: https://doi.org/10.1007/11757283_8
bibdate: Wed Nov 26 22:40:10 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.11.26 22:40:10 ???
acknowledgement: ack-nhfb
rawauthor: John Harrison
rawtitle: Floating-point verification using theorem proving
entry:
@InProceedings{Harrison:2006:FPV,
  author =       "John Harrison",
  title =        "Floating-point verification using theorem proving",
  crossref =     "Cimatti:2006:FMH",
  pages =        "211--242",
  year =         "2006",
  DOI =          "https://doi.org/10.1007/11757283_8",
  bibdate =      "Wed Nov 26 22:40:10 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Hars:2006:MIA
author: Laszlo Hars
title: Modular Inverse Algorithms Without Multiplications for Cryptographic Applications
journal: j-EURASIP-J-EMBED-SYS
volume: 2006
pages: 1--13
year: 2006
DOI: https://doi.org/10.1155/ES/2006/32192
ISSN: 1687-3955 (print), 1687-3963 (electronic) OR 16873955 (print), 16873963 (electronic)
ISSNL: 1687-3955 OR 16873955
bibdate: Wed Dec 28 09:54:06 2011
bibtimestamp: 2011.12.28 09:54:06 ???
note: Article ID 32192.
URL: http://downloads.hindawi.com/journals/es/2006/032192.pdf
fjournal: EURASIP Journal on Embedded Systems
acknowledgement: ack-nhfb
rawauthor: Laszlo Hars
rawnote: Article ID 32192.
rawtitle: Modular Inverse Algorithms Without Multiplications for Cryptographic Applications
bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2000.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/prng.bib

abstract:
Hardware and algorithmic optimization techniques are presented to the left-shift, right-shift, and the traditional Euclidean-modular inverse algorithms. Theoretical arguments and extensive simulations determined the resulting expected running time. On many computational platforms these turn out to be the fastest known algorithms for moderate operand lengths. They are based on variants of Euclidean-type extended GCD algorithms. On the considered computational platforms for operand lengths used in cryptography, the fastest presented modular inverse algorithms need about twice the time of modular multiplications, or even less. Consequently, in elliptic curve cryptography delaying modular divisions is slower (affine coordinates are the best) and the RSA and ElGamal cryptosystems can be accelerated.

rawabstract:
Hardware and algorithmic optimization techniques are presented to the left-shift, right-shift, and the traditional Euclidean-modular inverse algorithms. Theoretical arguments and extensive simulations determined the resulting expected running time. On many computational platforms these turn out to be the fastest known algorithms for moderate operand lengths. They are based on variants of Euclidean-type extended GCD algorithms. On the considered computational platforms for operand lengths used in cryptography, the fastest presented modular inverse algorithms need about twice the time of modular multiplications, or even less. Consequently, in elliptic curve cryptography delaying modular divisions is slower (affine coordinates are the best) and the RSA and ElGamal cryptosystems can be accelerated.

entry:
@Article{Hars:2006:MIA,
  author =       "Laszlo Hars",
  title =        "Modular Inverse Algorithms Without Multiplications for
                 Cryptographic Applications",
  journal =      j-EURASIP-J-EMBED-SYS,
  volume =       "2006",
  pages =        "1--13",
  year =         "2006",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1155/ES/2006/32192",
  ISSN =         "1687-3955 (print), 1687-3963 (electronic)",
  ISSN-L =       "1687-3955",
  bibdate =      "Wed Dec 28 09:54:06 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/prng.bib",
  note =         "Article ID 32192.",
  URL =          "http://downloads.hindawi.com/journals/es/2006/032192.pdf",
  abstract =     "Hardware and algorithmic optimization techniques are
                 presented to the left-shift, right-shift, and the
                 traditional Euclidean-modular inverse algorithms.
                 Theoretical arguments and extensive simulations
                 determined the resulting expected running time. On many
                 computational platforms these turn out to be the
                 fastest known algorithms for moderate operand lengths.
                 They are based on variants of Euclidean-type extended
                 GCD algorithms. On the considered computational
                 platforms for operand lengths used in cryptography, the
                 fastest presented modular inverse algorithms need about
                 twice the time of modular multiplications, or even
                 less. Consequently, in elliptic curve cryptography
                 delaying modular divisions is slower (affine
                 coordinates are the best) and the RSA and ElGamal
                 cryptosystems can be accelerated.",
  acknowledgement = ack-nhfb,
  fjournal =     "EURASIP Journal on Embedded Systems",
}


bibtype: article
filename: fparith.bib
label: Hill:2006:QUB
author: M. Hill and I. Robinson
title: Quadrature using 64-bit IEEE arithmetic for integrands over $ [0, 1] $ with a singularity at $1$
journal: j-THEOR-COMP-SCI
volume: 351
number: 1
pages: 82--100
day: 14
month: feb
monthnumber: 2
year: 2006
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Tue Mar 29 06:48:55 MDT 2011
bibtimestamp: 2011.03.29 06:48:55 MDT
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: M. Hill and I. Robinson
rawtitle: Quadrature using 64-bit {IEEE} arithmetic for integrands over $ [0, 1] $ with a singularity at $1$
abstract:
We present a detailed study of some problems encountered when quadrature over $ [0, 1] $ is attempted with integrands that have a singularity at $1$. Methods designed to increase the accuracy of such quadratures, for example, the application of periodising transformations, are examined in the context of the representational limitations of 64-bit IEEE arithmetic near $1$ in $ [0, 1] $. A heuristic is proposed for the forecasting of a lower bound on the irremovable error due to these limitations. We conclude by affirming the commonly accepted procedure that where possible, integrals should be symbolically transformed so that any remaining singularity occurs at $0$.

rawabstract:
We present a detailed study of some problems encountered when quadrature over $ [0, 1] $ is attempted with integrands that have a singularity at $1$. Methods designed to increase the accuracy of such quadratures, for example, the application of periodising transformations, are examined in the context of the representational limitations of 64-bit IEEE arithmetic near $1$ in $ [0, 1] $. A heuristic is proposed for the forecasting of a lower bound on the irremovable error due to these limitations. We conclude by affirming the commonly accepted procedure that where possible, integrals should be symbolically transformed so that any remaining singularity occurs at $0$.

entry:
@Article{Hill:2006:QUB,
  author =       "M. Hill and I. Robinson",
  title =        "Quadrature using 64-bit {IEEE} arithmetic for
                 integrands over $ [0, 1] $ with a singularity at $1$",
  journal =      j-THEOR-COMP-SCI,
  volume =       "351",
  number =       "1",
  pages =        "82--100",
  day =          "14",
  month =        feb,
  year =         "2006",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Tue Mar 29 06:48:55 MDT 2011",
  bibsource =    "http://www.sciencedirect.com/science/journal/03043975;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a detailed study of some problems
                 encountered when quadrature over $ [0, 1] $ is
                 attempted with integrands that have a singularity at
                 $1$. Methods designed to increase the accuracy of such
                 quadratures, for example, the application of
                 periodising transformations, are examined in the
                 context of the representational limitations of 64-bit
                 IEEE arithmetic near $1$ in $ [0, 1] $. A heuristic is
                 proposed for the forecasting of a lower bound on the
                 irremovable error due to these limitations. We conclude
                 by affirming the commonly accepted procedure that where
                 possible, integrals should be symbolically transformed
                 so that any remaining singularity occurs at $0$.",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
}


bibtype: article
filename: fparith.bib
label: How:2006:RRN
author: H. T. How and T. H. Liew and Ee-Lin Kuan and Lie-Liang Yang and L. Hanzo
journal: j-IEEE-TRANS-VEH-TECHNOL
volume: 55
number: 1
pages: 387--396
month: jan
monthnumber: 1
year: 2006
CODEN: ITUTAB
DOI: https://doi.org/10.1109/TVT.2005.861175
ISSN: 0018-9545 (print), 1939-9359 (electronic) OR 00189545 (print), 19399359 (electronic)
ISSNL: 0018-9545 OR 00189545
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=33430
fjournal: IEEE Transactions on Vehicular Technology
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=25
rawauthor: H. T. How and T. H. Liew and Ee-Lin Kuan and Lie-Liang Yang and L. Hanzo
title:
A redundant residue number system coded burst-by-burst adaptive joint-detection based CDMA speech transceiver

rawtitle:
A redundant residue number system coded burst-by-burst adaptive joint-detection based {CDMA} speech transceiver

entry:
@Article{How:2006:RRN,
  author =       "H. T. How and T. H. Liew and Ee-Lin Kuan and Lie-Liang
                 Yang and L. Hanzo",
  title =        "A redundant residue number system coded burst-by-burst
                 adaptive joint-detection based {CDMA} speech
                 transceiver",
  journal =      j-IEEE-TRANS-VEH-TECHNOL,
  volume =       "55",
  number =       "1",
  pages =        "387--396",
  month =        jan,
  year =         "2006",
  CODEN =        "ITUTAB",
  DOI =          "https://doi.org/10.1109/TVT.2005.861175",
  ISSN =         "0018-9545 (print), 1939-9359 (electronic)",
  ISSN-L =       "0018-9545",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=33430",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Vehicular Technology",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=25",
  keywords =     "residue arithmetic; residue number system",
  summary =      "A burst-by-burst (BbB) adaptive speech transceiver is
                 proposed, which can drop its source coding rate and
                 speech quality under transceiver control in order to
                 invoke a more error resilient modem mode among less
                 favorable channel conditions. The \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Hurlimann:2006:BLB
author: Werner Hurlimann
title: Benford's Law from 1881 to 2006: a bibliography
type: Report
address: Feldstrasse 145, CH-8004 Zurich, Switzerland
pages: 15
day: 5
month: jul
monthnumber: 7
year: 2006
bibdate: Fri Mar 30 11:32:30 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.30 11:32:30 ???
URL: http://arxiv.org/pdf/math.ST/0607168
keywords: Benford's Law; Law of Anomalous Numbers; Zipf's Law
acknowledgement: ack-nhfb
rawauthor: Werner H{\"u}rlimann
rawtitle: {Benford's Law} from 1881 to 2006: a bibliography
remark:
This bibliography lists 325 references on the title subject, with these (years) and counts: (1881) 1, (1912) 1, (1916) 1, (1917) 1, (1936) 1, (1938) 1, (1944) 1, (1945) 1, (1948) 2, (1950) 1, (1952) 1, (1953) 1, (1954) 1, (1957) 3, (1960) 1, (1961) 2, (1963) 1, (1964) 2, (1965) 2, (1966) 1, (1967) 1, (1968) 2, (1969) 5, (1970) 1, (1971) 4, (1972) 2, (1973) 7, (1974) 2, (1975) 1, (1976) 5, (1977) 3, (1978) 3, (1979) 2, (1981) 6, (1982) 3, (1983) 4, (1984) 7, (1985) 2, (1986) 7, (1987) 5, (1988) 1, (1988) 5, (1989) 2, (1990) 1, (1991) 4, (1992) 6, (1993) 5, (1994) 5, (1995) 1, (1995) 2, (1996) 4, (1997) 1, (1997) 9, (1998) 1, (1998) 6, (1999) 12, (2000) 10, (2001) 19, (2002) 30, (2003) 22, (2004) 29, (2005) 34, (2006) 18.

entry:
@TechReport{Hurlimann:2006:BLB,
  author =       "Werner H{\"u}rlimann",
  title =        "{Benford's Law} from 1881 to 2006: a bibliography",
  type =         "Report",
  address =      "Feldstrasse 145, CH-8004 Z{\"u}rich, Switzerland",
  pages =        "15",
  day =          "5",
  month =        jul,
  year =         "2006",
  bibdate =      "Fri Mar 30 11:32:30 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/pdf/math.ST/0607168",
  acknowledgement = ack-nhfb,
  keywords =     "Benford's Law; Law of Anomalous Numbers; Zipf's Law",
  remark =       "This bibliography lists 325 references on the title
                 subject, with these (years) and counts: (1881) 1,
                 (1912) 1, (1916) 1, (1917) 1, (1936) 1, (1938) 1,
                 (1944) 1, (1945) 1, (1948) 2, (1950) 1, (1952) 1,
                 (1953) 1, (1954) 1, (1957) 3, (1960) 1, (1961) 2,
                 (1963) 1, (1964) 2, (1965) 2, (1966) 1, (1967) 1,
                 (1968) 2, (1969) 5, (1970) 1, (1971) 4, (1972) 2,
                 (1973) 7, (1974) 2, (1975) 1, (1976) 5, (1977) 3,
                 (1978) 3, (1979) 2, (1981) 6, (1982) 3, (1983) 4,
                 (1984) 7, (1985) 2, (1986) 7, (1987) 5, (1988) 1,
                 (1988) 5, (1989) 2, (1990) 1, (1991) 4, (1992) 6,
                 (1993) 5, (1994) 5, (1995) 1, (1995) 2, (1996) 4,
                 (1997) 1, (1997) 9, (1998) 1, (1998) 6, (1999) 12,
                 (2000) 10, (2001) 19, (2002) 30, (2003) 22, (2004) 29,
                 (2005) 34, (2006) 18.",
}


bibtype: manual
filename: fparith.bib
label: IBM:2006:PDF
author: IBM Corporation
title: Preliminary Decimal-Floating-Point Architecture
publisher: pub-IBM
address: pub-IBM:adr
pages: viii + 52
month: nov
monthnumber: 11
year: 2006
bibdate: Sat Apr 07 12:13:51 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.04.07 12:13:51 ???
note: Form number SA23-2232-00.
acknowledgement: ack-nhfb
rawauthor: {IBM Corporation}
rawnote: Form number SA23-2232-00.
rawtitle: Preliminary Decimal-Floating-Point Architecture
URL:
http://publibz.boulder.ibm.com/epubs/pdf/a2322320.pdf; http://www-03.ibm.com/servers/eserver/zseries/zos/bkserv/r3pdf/zarchpops.html

abstract:
This is a preliminary description of the decimal-floating-point (DFP) facility and the floating-point support-enhancement facility. It will be superseded by the next published version of the em IBM z/Architecture Principles of Operation (SA22-7832).

rawabstract:
This is a preliminary description of the decimal-floating-point (DFP) facility and the floating-point support-enhancement facility. It will be superseded by the next published version of the {\em IBM z/Architecture Principles of Operation\/} (SA22-7832).

entry:
@Manual{IBM:2006:PDF,
  author =       "{IBM Corporation}",
  title =        "Preliminary Decimal-Floating-Point Architecture",
  publisher =    pub-IBM,
  address =      pub-IBM:adr,
  pages =        "viii + 52",
  month =        nov,
  year =         "2006",
  bibdate =      "Sat Apr 07 12:13:51 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Form number SA23-2232-00.",
  URL =          "http://publibz.boulder.ibm.com/epubs/pdf/a2322320.pdf;
                 http://www-03.ibm.com/servers/eserver/zseries/zos/bkserv/r3pdf/zarchpops.html",
  abstract =     "This is a preliminary description of the
                 decimal-floating-point (DFP) facility and the
                 floating-point support-enhancement facility. It will be
                 superseded by the next published version of the {\em
                 IBM z/Architecture Principles of Operation\/}
                 (SA22-7832).",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Imana:2006:BPF
author: J. L. Imana and J. M. Sanchez and F. Tirado
title: Bit-parallel finite field multipliers for irreducible trinomials
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 5
pages: 520--533
month: may
monthnumber: 5
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.69
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:54 MDT 2011
bibtimestamp: 2011.07.04 15:35:54 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1613833
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. L. Imana and J. M. Sanchez and F. Tirado
rawtitle: Bit-parallel finite field multipliers for irreducible trinomials
entry:
@Article{Imana:2006:BPF,
  author =       "J. L. Imana and J. M. Sanchez and F. Tirado",
  title =        "Bit-parallel finite field multipliers for irreducible
                 trinomials",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "5",
  pages =        "520--533",
  month =        may,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.69",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:54 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1613833",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: techreport
filename: fparith.bib
label: Intel:2006:IFP
author: Intel
title: Intel and Floating Point: Updating One of the Industry's Most Successful Standards
type: Web report
institution: Intel Corporation
address: San Jose, CA, USA
pages: 11
day: 17
month: jul
monthnumber: 7
year: 2006
bibdate: Thu Oct 14 14:43:38 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.14 14:43:38 ???
URL: http://www.intel.com/standards/floatingpoint.pdf
acknowledgement: ack-nhfb
rawauthor: {Intel}
rawtitle: {Intel} and Floating Point: Updating One of the Industry's Most Successful Standards
remark:
Includes mention of some major historical systems failures due to faulty handling of floating-point arithmetic, and discusses future directions for decimal arithmetic.

entry:
@TechReport{Intel:2006:IFP,
  author =       "{Intel}",
  title =        "{Intel} and Floating Point: Updating One of the
                 Industry's Most Successful Standards",
  type =         "{Web} report",
  institution =  "Intel Corporation",
  address =      "San Jose, CA, USA",
  pages =        "11",
  day =          "17",
  month =        jul,
  year =         "2006",
  bibdate =      "Thu Oct 14 14:43:38 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.intel.com/standards/floatingpoint.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Includes mention of some major historical systems
                 failures due to faulty handling of floating-point
                 arithmetic, and discusses future directions for decimal
                 arithmetic.",
}


bibtype: book
filename: fparith.bib
label: ISO:2006:IIIa
author: ISO
publisher: pub-ISO
address: pub-ISO:adr
pages: viii + 149
day: 15
month: aug
monthnumber: 8
year: 2006
bibdate: Sun Mar 15 11:09:44 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.03.15 11:09:44 ???
acknowledgement: ack-nhfb
rawauthor: {ISO}
title:
ISO / IEC 10967-3: Information technology --- Language independent arithmetic --- Part 3: Complex integer and floating point arithmetic and complex elementary numerical functions

URL:
http://standards.iso.org/ittf/PubliclyAvailableStandards/c037994_ISO_IEC_10967-3_2006(E).zip; http://www.iso.ch/cate/d24427.html

rawtitle:
{ISO\slash IEC 10967-3}: {Information} technology --- {Language} independent arithmetic --- {Part} 3: {Complex} integer and floating point arithmetic and complex elementary numerical functions

entry:
@Book{ISO:2006:IIIa,
  author =       "{ISO}",
  title =        "{ISO\slash IEC 10967-3}: {Information} technology ---
                 {Language} independent arithmetic --- {Part} 3:
                 {Complex} integer and floating point arithmetic and
                 complex elementary numerical functions",
  publisher =    pub-ISO,
  address =      pub-ISO:adr,
  pages =        "viii + 149",
  day =          "15",
  month =        aug,
  year =         "2006",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Sun Mar 15 11:09:44 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://standards.iso.org/ittf/PubliclyAvailableStandards/c037994_ISO_IEC_10967-3_2006(E).zip;
                 http://www.iso.ch/cate/d24427.html",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: ISO:2006:IIJa
author: ISO
pages: viii + 149
day: 27
month: feb
monthnumber: 2
year: 2006
bibdate: Tue Mar 07 18:23:45 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.03.07 18:23:45 ???
URL: http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1154.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: {ISO}
title:
ISO / IEC JTC1 SC22 WG14 N1154: Extension for the programming language C to support decimal floating-point arithmetic

rawtitle:
{ISO\slash IEC JTC1 SC22 WG14 N1154}: Extension for the programming language {C} to support decimal floating-point arithmetic

entry:
@Misc{ISO:2006:IIJa,
  author =       "{ISO}",
  title =        "{ISO\slash IEC JTC1 SC22 WG14 N1154}: Extension for
                 the programming language {C} to support decimal
                 floating-point arithmetic",
  howpublished = "World-Wide Web document",
  day =          "27",
  month =        feb,
  year =         "2006",
  bibdate =      "Tue Mar 07 18:23:45 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1154.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: misc
filename: fparith.bib
label: ISO:2006:IIJb
author: ISO
pages: viii + 149
day: 27
month: feb
monthnumber: 2
year: 2006
bibdate: Tue Mar 07 18:23:45 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.03.07 18:23:45 ???
URL: http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1161.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: {ISO}
title:
ISO / IEC JTC1 SC22 WG14 N1161: Rationale for TR 24732: Extension to the programming language C: Decimal Floating-Point Arithmetic

rawtitle:
{ISO\slash IEC JTC1 SC22 WG14 N1161}: Rationale for {TR 24732}: Extension to the programming language {C}: Decimal Floating-Point Arithmetic

entry:
@Misc{ISO:2006:IIJb,
  author =       "{ISO}",
  title =        "{ISO\slash IEC JTC1 SC22 WG14 N1161}: Rationale for
                 {TR 24732}: Extension to the programming language {C}:
                 Decimal Floating-Point Arithmetic",
  howpublished = "World-Wide Web document",
  day =          "27",
  month =        feb,
  year =         "2006",
  bibdate =      "Tue Mar 07 18:23:45 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1161.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: misc
filename: fparith.bib
label: ISO:2006:IIJc
author: ISO
pages: iii + 33
day: 24
month: may
monthnumber: 5
year: 2006
bibdate: Sat Feb 24 20:00:36 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.02.24 20:00:36 ???
URL: http://open-std.org/jtc1/sc22/wg14/www/docs/n1176.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: {ISO}
title:
ISO / IEC JTC1 SC22 WG14 N1176: Extension for the programming language C to support decimal floating-point arithmetic

rawtitle:
{ISO\slash IEC JTC1 SC22 WG14 N1176}: Extension for the programming language {C} to support decimal floating-point arithmetic

entry:
@Misc{ISO:2006:IIJc,
  author =       "{ISO}",
  title =        "{ISO\slash IEC JTC1 SC22 WG14 N1176}: Extension for
                 the programming language {C} to support decimal
                 floating-point arithmetic",
  howpublished = "World-Wide Web document",
  pages =        "iii + 33",
  day =          "24",
  month =        may,
  year =         "2006",
  bibdate =      "Sat Feb 24 20:00:36 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://open-std.org/jtc1/sc22/wg14/www/docs/n1176.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Kahan:2006:AIR
author: William Kahan
title: Applications of IEEE 754r's Rounding Modes
pages: iii + 33
day: 16
month: feb
monthnumber: 2
year: 2006
bibdate: Fri Feb 17 17:54:50 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.02.17 17:54:50 ???
URL: http://nonabelian.com/754/RNDGMODE.TXT
acknowledgement: ack-nhfb
howpublished: World-Wide Web document.
rawauthor: William Kahan
rawtitle: Applications of {IEEE 754r}'s Rounding Modes
entry:
@Misc{Kahan:2006:AIR,
  author =       "William Kahan",
  title =        "Applications of {IEEE 754r}'s Rounding Modes",
  howpublished = "World-Wide Web document.",
  day =          "16",
  month =        feb,
  year =         "2006",
  bibdate =      "Fri Feb 17 17:54:50 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://nonabelian.com/754/RNDGMODE.TXT",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kaivani:2006:RID
author: A. Kaivani and A. Zaker Alhosseini and S. Gorgin and M. Fazlali
crossref: Mohanty:2006:IIC
pages: 273--276
year: 2006
bibdate: Thu Aug 07 18:12:35 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 18:12:35 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: A. Kaivani and A. Zaker Alhosseini and S. Gorgin and M. Fazlali
title:
Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in IEEE-754R

abstract:
The Binary Coded Decimal (BCD) encoding has always dominated the decimal arithmetic algorithms and their hardware implementation. Due to importance of decimal arithmetic, the decimal format defined in lEEE 754 floating point standard has been revisited. It uses Densely Packed Decimal (DPD) encoding to store significand part of a decimal floating point number. Furthermore in recent years reversible logic has attracted the attention of engineers for designing low power CMOS circuits, as it is not possible to realize quantum computing without reversible logic implementation. This paper derives the reversible implementation of DPD converter to and from conventional BCD format using in IEEE 754R.

rawabstract:
The Binary Coded Decimal (BCD) encoding has always dominated the decimal arithmetic algorithms and their hardware implementation. Due to importance of decimal arithmetic, the decimal format defined in lEEE 754 floating point standard has been revisited. It uses Densely Packed Decimal (DPD) encoding to store significand part of a decimal floating point number. Furthermore in recent years reversible logic has attracted the attention of engineers for designing low power CMOS circuits, as it is not possible to realize quantum computing without reversible logic implementation. This paper derives the reversible implementation of DPD converter to and from conventional BCD format using in IEEE 754R.

rawtitle:
Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in {IEEE-754R}

entry:
@InProceedings{Kaivani:2006:RID,
  author =       "A. Kaivani and A. Zaker Alhosseini and S. Gorgin and
                 M. Fazlali",
  title =        "Reversible Implementation of Densely-Packed-Decimal
                 Converter to and from Binary-Coded-Decimal Format Using
                 in {IEEE-754R}",
  crossref =     "Mohanty:2006:IIC",
  pages =        "273--276",
  year =         "2006",
  bibdate =      "Thu Aug 07 18:12:35 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Binary Coded Decimal (BCD) encoding has always
                 dominated the decimal arithmetic algorithms and their
                 hardware implementation. Due to importance of decimal
                 arithmetic, the decimal format defined in lEEE 754
                 floating point standard has been revisited. It uses
                 Densely Packed Decimal (DPD) encoding to store
                 significand part of a decimal floating point number.
                 Furthermore in recent years reversible logic has
                 attracted the attention of engineers for designing low
                 power CMOS circuits, as it is not possible to realize
                 quantum computing without reversible logic
                 implementation. This paper derives the reversible
                 implementation of DPD converter to and from
                 conventional BCD format using in IEEE 754R.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Kang:2006:SHS
author: J.-Y. Kang and J.-L. Gaudiot
title: A Simple High-Speed Multiplier Design
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 10
pages: 1253--1258
month: oct
monthnumber: 10
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.156
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:56 MDT 2011
bibtimestamp: 2011.07.04 15:35:56 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1683756
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J.-Y. Kang and J.-L. Gaudiot
rawtitle: A Simple High-Speed Multiplier Design
entry:
@Article{Kang:2006:SHS,
  author =       "J.-Y. Kang and J.-L. Gaudiot",
  title =        "A Simple High-Speed Multiplier Design",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "10",
  pages =        "1253--1258",
  month =        oct,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.156",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:56 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1683756",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Kettani:2006:CBN
author: Houssain Kettani
title: On the Conversion Between Number Systems
journal: j-IEEE-TRANS-CIRCUITS-SYST-2
volume: 53
number: 11
pages: 1255--1258
month: nov
monthnumber: 11
year: 2006
CODEN: ICSPE5
DOI: https://doi.org/10.1109/TCSII.2006.882856
ISSN: 1057-7130 (print), 1558-125X (electronic) OR 10577130 (print), 1558125X (electronic)
ISSNL: 1057-7130 OR 10577130
bibdate: Mon Mar 19 10:05:23 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.19 10:05:23 ???
fjournal: IEEE Transactions on Circuits and Systems. 2, Analog and Digital Signal Processing
keywords: Algorithm's efficiency; base numbers; conversion
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82
rawauthor: Houssain Kettani
rawtitle: On the Conversion Between Number Systems
abstract:
This brief revisits the problem of conversion between number systems and asks the following question: given a nonnegative decimal number, what is the value of the digit at position in the corresponding base number? Thus, we do not require the knowledge of other digits except the one we are interested in. Accordingly, we present a conversion function that relates each digit in a base system to the decimal value that is equal to the base number in question. We also show some applications of this new algorithm in the areas of parallel computing and cryptography.

rawabstract:
This brief revisits the problem of conversion between number systems and asks the following question: given a nonnegative decimal number, what is the value of the digit at position in the corresponding base number? Thus, we do not require the knowledge of other digits except the one we are interested in. Accordingly, we present a conversion function that relates each digit in a base system to the decimal value that is equal to the base number in question. We also show some applications of this new algorithm in the areas of parallel computing and cryptography.

entry:
@Article{Kettani:2006:CBN,
  author =       "Houssain Kettani",
  title =        "On the Conversion Between Number Systems",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-2,
  volume =       "53",
  number =       "11",
  pages =        "1255--1258",
  month =        nov,
  year =         "2006",
  CODEN =        "ICSPE5",
  DOI =          "https://doi.org/10.1109/TCSII.2006.882856",
  ISSN =         "1057-7130 (print), 1558-125X (electronic)",
  ISSN-L =       "1057-7130",
  bibdate =      "Mon Mar 19 10:05:23 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This brief revisits the problem of conversion between
                 number systems and asks the following question: given a
                 nonnegative decimal number, what is the value of the
                 digit at position in the corresponding base number?
                 Thus, we do not require the knowledge of other digits
                 except the one we are interested in. Accordingly, we
                 present a conversion function that relates each digit
                 in a base system to the decimal value that is equal to
                 the base number in question. We also show some
                 applications of this new algorithm in the areas of
                 parallel computing and cryptography.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems. 2, Analog
                 and Digital Signal Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82",
  keywords =     "Algorithm's efficiency; base numbers; conversion",
}


bibtype: article
filename: fparith.bib
label: Kong:2006:IGA
author: Fanyu Kong and Zhun Cai and Jia Yu and Daxing Li
title: Improved generalized Atkin algorithm for computing square roots in finite fields
journal: j-INFO-PROC-LETT
volume: 98
number: 1
pages: 1--5
day: 15
month: apr
monthnumber: 4
year: 2006
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Thu Mar 31 18:41:08 MDT 2011
bibtimestamp: 2011.03.31 18:41:08 MDT
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: Fanyu Kong and Zhun Cai and Jia Yu and Daxing Li
rawtitle: Improved generalized {Atkin} algorithm for computing square roots in finite fields
bibsource:
http://www.sciencedirect.com/science/journal/00200190; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Kong:2006:IGA,
  author =       "Fanyu Kong and Zhun Cai and Jia Yu and Daxing Li",
  title =        "Improved generalized {Atkin} algorithm for computing
                 square roots in finite fields",
  journal =      j-INFO-PROC-LETT,
  volume =       "98",
  number =       "1",
  pages =        "1--5",
  day =          "15",
  month =        apr,
  year =         "2006",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Thu Mar 31 18:41:08 MDT 2011",
  bibsource =    "http://www.sciencedirect.com/science/journal/00200190;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: article
filename: fparith.bib
label: Kornerup:2006:CSV
author: Peter Kornerup and Jean-Michel Muller
title: Choosing starting values for certain Newton--Raphson iterations
journal: j-THEOR-COMP-SCI
volume: 351
number: 1
pages: 101--110
day: 14
month: feb
monthnumber: 2
year: 2006
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Tue Mar 29 06:48:55 MDT 2011
bibtimestamp: 2011.03.29 06:48:55 MDT
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: Peter Kornerup and Jean-Michel Muller
rawtitle: Choosing starting values for certain {Newton--Raphson} iterations
abstract:
We aim at finding the best possible seed values when computing $ a^1 / p $ using the Newton--Raphson iteration in a given interval. A natural choice of the seed value would be the one that best approximates the expected result. It turns out that in most cases, the best seed value can be quite far from this natural choice. When we evaluate a monotone function $ f(a) $ in the interval $ [a_mathrm min, a_mathrm max] $, by building the sequence $ x_n $ defined by the Newton--Raphson iteration, the natural choice consists in choosing $ x_0 $ equal to the arithmetic mean of the endpoint values. This minimizes the maximum possible distance between $ x_0 $ and $ f(a) $. And yet, if we perform $n$ iterations, what matters is to minimize the maximum possible distance between $ x_n $ and $ f(a) $. In several examples, the value of the best starting point varies rather significantly with the number of iterations.

rawabstract:
We aim at finding the best possible seed values when computing $ a^{1 / p} $ using the Newton--Raphson iteration in a given interval. A natural choice of the seed value would be the one that best approximates the expected result. It turns out that in most cases, the best seed value can be quite far from this natural choice. When we evaluate a monotone function $ f(a) $ in the interval $ [a_\mathrm {min}, a_\mathrm {max}] $, by building the sequence $ x_n $ defined by the Newton--Raphson iteration, the natural choice consists in choosing $ x_0 $ equal to the arithmetic mean of the endpoint values. This minimizes the maximum possible distance between $ x_0 $ and $ f(a) $. And yet, if we perform $n$ iterations, what matters is to minimize the maximum possible distance between $ x_n $ and $ f(a) $. In several examples, the value of the best starting point varies rather significantly with the number of iterations.

entry:
@Article{Kornerup:2006:CSV,
  author =       "Peter Kornerup and Jean-Michel Muller",
  title =        "Choosing starting values for certain {Newton--Raphson}
                 iterations",
  journal =      j-THEOR-COMP-SCI,
  volume =       "351",
  number =       "1",
  pages =        "101--110",
  day =          "14",
  month =        feb,
  year =         "2006",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Tue Mar 29 06:48:55 MDT 2011",
  bibsource =    "http://www.sciencedirect.com/science/journal/03043975;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We aim at finding the best possible seed values when
                 computing $ a^{1 / p} $ using the Newton--Raphson
                 iteration in a given interval. A natural choice of the
                 seed value would be the one that best approximates the
                 expected result. It turns out that in most cases, the
                 best seed value can be quite far from this natural
                 choice. When we evaluate a monotone function $ f(a) $
                 in the interval $ [a_\mathrm {min}, a_\mathrm {max}] $,
                 by building the sequence $ x_n $ defined by the
                 Newton--Raphson iteration, the natural choice consists
                 in choosing $ x_0 $ equal to the arithmetic mean of the
                 endpoint values. This minimizes the maximum possible
                 distance between $ x_0 $ and $ f(a) $. And yet, if we
                 perform $n$ iterations, what matters is to minimize the
                 maximum possible distance between $ x_n $ and $ f(a) $.
                 In several examples, the value of the best starting
                 point varies rather significantly with the number of
                 iterations.",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
}


bibtype: inproceedings
filename: fparith.bib
label: Kornerup:2006:RCN
author: Peter Kornerup and Jean-Michel Muller
title: RN-Codings: New Insights and Some Applications
crossref: Anonymous:2006:PCR
pages: ??--??
year: 2006
bibdate: Tue Jun 27 10:28:05 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.06.27 10:28:05 ???
acknowledgement: ack-nhfb
rawauthor: Peter Kornerup and Jean-Michel Muller
rawtitle: {RN}-Codings: New Insights and Some Applications
entry:
@InProceedings{Kornerup:2006:RCN,
  author =       "Peter Kornerup and Jean-Michel Muller",
  title =        "{RN}-Codings: New Insights and Some Applications",
  crossref =     "Anonymous:2006:PCR",
  pages =        "??--??",
  year =         "2006",
  bibdate =      "Tue Jun 27 10:28:05 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kulikova:2006:HFD
author: A. A. Kulikova and Yu. V. Prokhorov and V. I. Khokhlov
title: H.F.D. ($H$-function Distribution) and Benford's Law. I
journal: j-THEORY-PROBAB-APPL
volume: 50
number: 2
pages: 311--315
month: jan
monthnumber: 1
year: 2006
CODEN: TPRBAU
DOI: https://doi.org/10.1137/S0040585X97981706
ISSN: 0040-585X (print), 1095-7219 (electronic) OR 0040585X (print), 10957219 (electronic)
ISSNL: 0040-585X OR 0040585X
bibdate: Wed May 19 18:14:51 MDT 2010
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/TVP/50/2; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.19 18:14:51 MDT
fjournal: Theory of Probability and its Applications
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/tvp
rawauthor: A. A. Kulikova and Yu. V. Prokhorov and V. I. Khokhlov
rawtitle: {H.F.D.} ({$H$}-function Distribution) and {Benford's Law}. {I}
entry:
@Article{Kulikova:2006:HFD,
  author =       "A. A. Kulikova and Yu. V. Prokhorov and V. I.
                 Khokhlov",
  title =        "{H.F.D.} ({$H$}-function Distribution) and {Benford's
                 Law}. {I}",
  journal =      j-THEORY-PROBAB-APPL,
  volume =       "50",
  number =       "2",
  pages =        "311--315",
  month =        jan,
  year =         "2006",
  CODEN =        "TPRBAU",
  DOI =          "https://doi.org/10.1137/S0040585X97981706",
  ISSN =         "0040-585X (print), 1095-7219 (electronic)",
  ISSN-L =       "0040-585X",
  bibdate =      "Wed May 19 18:14:51 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/TVP/50/2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Theory of Probability and its Applications",
  journal-URL =  "http://epubs.siam.org/tvp",
}


bibtype: article
filename: fparith.bib
label: Kumar:2006:ODS
author: Sandeep Kumar and T. Wollinger and C. Paar
title: Optimum Digit Serial $ mathrm GF(2^m) $ Multipliers for Curve-Based Cryptography
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 10
pages: 1306--1311
month: oct
monthnumber: 10
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.165
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:57 MDT 2011
bibtimestamp: 2011.07.04 15:35:57 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1683761
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Sandeep Kumar and T. Wollinger and C. Paar
rawtitle: Optimum Digit Serial {$ \mathrm {GF}(2^m) $} Multipliers for Curve-Based Cryptography
bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2000.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib

entry:
@Article{Kumar:2006:ODS,
  author =       "Sandeep Kumar and T. Wollinger and C. Paar",
  title =        "Optimum Digit Serial {$ \mathrm {GF}(2^m) $}
                 Multipliers for Curve-Based Cryptography",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "10",
  pages =        "1306--1311",
  month =        oct,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.165",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:57 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1683761",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Kushner:2006:I
author: David Kushner
title: The Insomniacs
journal: j-IEEE-SPECTRUM
volume: 43
number: 12
pages: 24--29
month: dec
monthnumber: 12
year: 2006
CODEN: IEESAM
DOI: https://doi.org/10.1109/MSPEC.2006.253405
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Thu Sep 01 16:23:03 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.01 16:23:03 ???
fjournal: IEEE Spectrum
keywords: floating-point arithmetic; IBM Cell processor; Sony Playstation 3
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: David Kushner
rawtitle: The Insomniacs
entry:
@Article{Kushner:2006:I,
  author =       "David Kushner",
  title =        "The Insomniacs",
  journal =      j-IEEE-SPECTRUM,
  volume =       "43",
  number =       "12",
  pages =        "24--29",
  month =        dec,
  year =         "2006",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/MSPEC.2006.253405",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Thu Sep 01 16:23:03 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "floating-point arithmetic; IBM Cell processor; Sony
                 Playstation 3",
}


bibtype: inproceedings
filename: fparith.bib
label: Lang:2006:SRI
author: Tomas Lang and Javier D. Bruguera
title: The sunity representation to improve the accuracy of some computations
crossref: Anonymous:2006:PCR
pages: ??--??
year: 2006
bibdate: Tue Jun 27 10:28:05 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.06.27 10:28:05 ???
acknowledgement: ack-nhfb
rawauthor: Tomas Lang and Javier D. Bruguera
rawtitle: The sunity representation to improve the accuracy of some computations
entry:
@InProceedings{Lang:2006:SRI,
  author =       "Tomas Lang and Javier D. Bruguera",
  title =        "The sunity representation to improve the accuracy of
                 some computations",
  crossref =     "Anonymous:2006:PCR",
  pages =        "??--??",
  year =         "2006",
  bibdate =      "Tue Jun 27 10:28:05 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Langou:2006:EPBa
type: LAPACK Working Note
number: 175
institution: inst-UT-CS
address: inst-UT-CS:adr
pages: 17
month: jun
monthnumber: 6
year: 2006
bibdate: Mon Oct 09 12:05:43 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.10.09 12:05:43 ???
URL: http://www.netlib.org/lapack/lawnspdf/lawn175.pdf; http://www.netlib.org/lapack/lawnspdf/lawn175.ps
acknowledgement: ack-nhfb
author:
Julie Langou and Julien Langou and Piotr Luszczek and Jakub Kurzak and Alfredo Buttari and Jack Dongarra

title:
Exploiting the Performance of 32 bit Floating Point Arithmetic in Obtaining 64 bit Accuracy (Revisiting Iterative Refinement for Linear Systems)

abstract:
Recent versions of microprocessors exhibit performance characteristics for 32 bit floating point arithmetic (single precision) that is substantially higher than 64 bit floating point arithmetic (double precision). Examples include the Intel's Pentium IV and M processors, AMD's Opteron architectures and the IBM's Cell Broad Engine processor. When working in single precision, floating point operations can be performed up to two times faster on the Pentium and up to ten times faster on the Cell over double precision. The performance enhancements in these architectures are derived by accessing extensions to the basic architecture, such as SSE2 in the case of the Pentium and the vector functions on the IBM Cell. The motivation for this paper is to exploit single precision operations whenever possible and resort to double precision at critical stages while attempting to provide the full double precision results. The results described here are fairly general and can be applied to various problems in linear algebra such as solving large sparse systems, using direct or iterative methods and some eigenvalue problems. There are limitations to the success of this process, such as when the conditioning of the problem exceeds the reciprocal of the accuracy of the single precision computations. In that case the double precision algorithm should be used.

rawabstract:
Recent versions of microprocessors exhibit performance characteristics for 32 bit floating point arithmetic (single precision) that is substantially higher than 64 bit floating point arithmetic (double precision). Examples include the Intel's Pentium IV and M processors, AMD's Opteron architectures and the IBM's Cell Broad Engine processor. When working in single precision, floating point operations can be performed up to two times faster on the Pentium and up to ten times faster on the Cell over double precision. The performance enhancements in these architectures are derived by accessing extensions to the basic architecture, such as SSE2 in the case of the Pentium and the vector functions on the IBM Cell. The motivation for this paper is to exploit single precision operations whenever possible and resort to double precision at critical stages while attempting to provide the full double precision results. The results described here are fairly general and can be applied to various problems in linear algebra such as solving large sparse systems, using direct or iterative methods and some eigenvalue problems. There are limitations to the success of this process, such as when the conditioning of the problem exceeds the reciprocal of the accuracy of the single precision computations. In that case the double precision algorithm should be used.

rawauthor:
Julie Langou and Julien Langou and Piotr Luszczek and Jakub Kurzak and Alfredo Buttari and Jack Dongarra

rawtitle:
Exploiting the Performance of 32 bit Floating Point Arithmetic in Obtaining 64 bit Accuracy (Revisiting Iterative Refinement for Linear Systems)

entry:
@TechReport{Langou:2006:EPBa,
  author =       "Julie Langou and Julien Langou and Piotr Luszczek and
                 Jakub Kurzak and Alfredo Buttari and Jack Dongarra",
  title =        "Exploiting the Performance of 32 bit Floating Point
                 Arithmetic in Obtaining 64 bit Accuracy (Revisiting
                 Iterative Refinement for Linear Systems)",
  type =         "LAPACK Working Note",
  number =       "175",
  institution =  inst-UT-CS,
  address =      inst-UT-CS:adr,
  pages =        "17",
  month =        jun,
  year =         "2006",
  bibdate =      "Mon Oct 09 12:05:43 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.netlib.org/lapack/lawnspdf/lawn175.pdf;
                 http://www.netlib.org/lapack/lawnspdf/lawn175.ps",
  abstract =     "Recent versions of microprocessors exhibit performance
                 characteristics for 32 bit floating point arithmetic
                 (single precision) that is substantially higher than 64
                 bit floating point arithmetic (double precision).
                 Examples include the Intel's Pentium IV and M
                 processors, AMD's Opteron architectures and the IBM's
                 Cell Broad Engine processor. When working in single
                 precision, floating point operations can be performed
                 up to two times faster on the Pentium and up to ten
                 times faster on the Cell over double precision. The
                 performance enhancements in these architectures are
                 derived by accessing extensions to the basic
                 architecture, such as SSE2 in the case of the Pentium
                 and the vector functions on the IBM Cell. The
                 motivation for this paper is to exploit single
                 precision operations whenever possible and resort to
                 double precision at critical stages while attempting to
                 provide the full double precision results. The results
                 described here are fairly general and can be applied to
                 various problems in linear algebra such as solving
                 large sparse systems, using direct or iterative methods
                 and some eigenvalue problems. There are limitations to
                 the success of this process, such as when the
                 conditioning of the problem exceeds the reciprocal of
                 the accuracy of the single precision computations. In
                 that case the double precision algorithm should be
                 used.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Langou:2006:EPBb
crossref: ACM:2006:SCH
pages: ??--??
year: 2006
DOI: https://doi.org/10.1145/1188455.1188573
bibdate: Thu Nov 08 20:00:17 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 20:00:17 ???
acknowledgement: ack-nhfb
articleno: 113
author:
Julie Langou and Julien Langou and Piotr Luszczek and Jakub Kurzak and Alfredo Buttari and Jack Dongarra

title:
Exploiting the performance of 32 bit floating point arithmetic in obtaining 64 bit accuracy (revisiting iterative refinement for linear systems)

abstract:
Recent versions of microprocessors exhibit performance characteristics for 32 bit floating point arithmetic (single precision) that is substantially higher than 64 bit floating point arithmetic (double precision). Examples include the Intel's Pentium IV and M processors, AMD's Opteron architectures and the IBM's Cell Broad Engine processor. When working in single precision, floating point operations can be performed up to two times faster on the Pentium and up to ten times faster on the Cell over double precision. The performance enhancements in these architectures are derived by accessing extensions to the basic architecture, such as SSE2 in the case of the Pentium and the vector functions on the IBM Cell. The motivation for this paper is to exploit single precision operations whenever possible and resort to double precision at critical stages while attempting to provide the full double precision results. The results described here are fairly general and can be applied to various problems in linear algebra such as solving large sparse systems, using direct or iterative methods and some eigenvalue problems. There are limitations to the success of this process, such as when the conditioning of the problem exceeds the reciprocal of the accuracy of the single precision computations. In that case the double precision algorithm should be used.

rawtitle:
Exploiting the performance of 32 bit floating point arithmetic in obtaining 64 bit accuracy (revisiting iterative refinement for linear systems)

entry:
@InProceedings{Langou:2006:EPBb,
  author =       "Julie Langou and Julien Langou and Piotr Luszczek and
                 Jakub Kurzak and Alfredo Buttari and Jack Dongarra",
  title =        "Exploiting the performance of 32 bit floating point
                 arithmetic in obtaining 64 bit accuracy (revisiting
                 iterative refinement for linear systems)",
  crossref =     "ACM:2006:SCH",
  pages =        "??--??",
  year =         "2006",
  DOI =          "https://doi.org/10.1145/1188455.1188573",
  bibdate =      "Thu Nov 08 20:00:17 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Recent versions of microprocessors exhibit performance
                 characteristics for 32 bit floating point arithmetic
                 (single precision) that is substantially higher than 64
                 bit floating point arithmetic (double precision).
                 Examples include the Intel's Pentium IV and M
                 processors, AMD's Opteron architectures and the IBM's
                 Cell Broad Engine processor. When working in single
                 precision, floating point operations can be performed
                 up to two times faster on the Pentium and up to ten
                 times faster on the Cell over double precision. The
                 performance enhancements in these architectures are
                 derived by accessing extensions to the basic
                 architecture, such as SSE2 in the case of the Pentium
                 and the vector functions on the IBM Cell. The
                 motivation for this paper is to exploit single
                 precision operations whenever possible and resort to
                 double precision at critical stages while attempting to
                 provide the full double precision results. The results
                 described here are fairly general and can be applied to
                 various problems in linear algebra such as solving
                 large sparse systems, using direct or iterative methods
                 and some eigenvalue problems. There are limitations to
                 the success of this process, such as when the
                 conditioning of the problem exceeds the reciprocal of
                 the accuracy of the single precision computations. In
                 that case the double precision algorithm should be
                 used.",
  acknowledgement = ack-nhfb,
  articleno =    "113",
}


bibtype: techreport
filename: fparith.bib
label: Lefevre:2006:WCE
author: Vincent Lefevre and Damien Stehle and Paul Zimmermann
title: Worst Cases for the Exponential Function in the IEEE 754r tt decimal64 Format
type: Technical report
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
pages: 14
month: sep
monthnumber: 9
year: 2006
bibdate: Wed Sep 06 07:31:38 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.06 07:31:38 ???
keywords: correct rounding; decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\`e}vre and Damien Stehl{\'e} and Paul Zimmermann
rawtitle: Worst Cases for the Exponential Function in the {IEEE 754r} {{\tt decimal64}} Format
note:
To appear in a special LNCS issue following the Dagstuhl seminar 06021: Reliable Implementation of Real Number Algorithms: Theory and Practice.

URL:
http://www.loria.fr/~zimmerma/papers/decimalexp-lncs-final.pdf; http://www.loria.fr/~zimmerma/wc/decimal32.html; http://www.loria.fr/~zimmerma/wc/decimal64.html

abstract:
We searched for the worst cases for correct rounding of the exponential function in the IEEE 754r decimal64 format, and computed all the bad cases whose distance from a breakpoint (for all rounding modes) is less than $ 10^-15 $ ulp, and we give the worst ones. In particular, the worst case for $ |x| geq 3 times 10^-11 $ is $ exp (9.407822313572878 times 10^-2) = 1.098645682066338 50000000000000000 278 ldots $. This work can be extended to other elementary functions in the decimal64 format and allows the design of reasonably fast routines that will evaluate these functions with correct rounding, at least in some domains.

rawabstract:
We searched for the worst cases for correct rounding of the exponential function in the IEEE 754r decimal64 format, and computed all the bad cases whose distance from a breakpoint (for all rounding modes) is less than $ 10^{-15} $ ulp, and we give the worst ones. In particular, the worst case for $ |x| \geq 3 \times 10^{-11} $ is $ \exp (9.407822313572878 \times 10^{-2}) = 1.098645682066338 \, 50000000000000000 \, 278 \ldots {} $. This work can be extended to other elementary functions in the decimal64 format and allows the design of reasonably fast routines that will evaluate these functions with correct rounding, at least in some domains.

rawnote:
To appear in a special LNCS issue following the Dagstuhl seminar 06021: Reliable Implementation of Real Number Algorithms: Theory and Practice.

entry:
@TechReport{Lefevre:2006:WCE,
  author =       "Vincent Lef{\`e}vre and Damien Stehl{\'e} and Paul
                 Zimmermann",
  title =        "Worst Cases for the Exponential Function in the {IEEE
                 754r} {{\tt decimal64}} Format",
  type =         "Technical report",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  pages =        "14",
  month =        sep,
  year =         "2006",
  bibdate =      "Wed Sep 06 07:31:38 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "To appear in a special LNCS issue following the
                 Dagstuhl seminar 06021: Reliable Implementation of Real
                 Number Algorithms: Theory and Practice.",
  URL =          "http://www.loria.fr/~zimmerma/papers/decimalexp-lncs-final.pdf;
                 http://www.loria.fr/~zimmerma/wc/decimal32.html;
                 http://www.loria.fr/~zimmerma/wc/decimal64.html",
  abstract =     "We searched for the worst cases for correct rounding
                 of the exponential function in the IEEE 754r decimal64
                 format, and computed all the bad cases whose distance
                 from a breakpoint (for all rounding modes) is less than
                 $ 10^{-15} $ ulp, and we give the worst ones. In
                 particular, the worst case for $ |x| \geq 3 \times
                 10^{-11} $ is $ \exp (9.407822313572878 \times 10^{-2})
                 = 1.098645682066338 \, 50000000000000000 \, 278 \ldots
                 {} $. This work can be extended to other elementary
                 functions in the decimal64 format and allows the design
                 of reasonably fast routines that will evaluate these
                 functions with correct rounding, at least in some
                 domains.",
  acknowledgement = ack-nhfb,
  keywords =     "correct rounding; decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Liew:2006:SRR
author: T. H. Liew and Lie-Liang Yang and L. Hanzo
journal: j-IEEE-TRANS-COMM
volume: 54
number: 6
pages: 1006--1016
month: jun
monthnumber: 6
year: 2006
CODEN: IECMBT
DOI: https://doi.org/10.1109/TCOMM.2006.876843
ISSN: 0090-6778 (print), 1558-0857 (electronic) OR 00906778 (print), 15580857 (electronic)
ISSNL: 0090-6778 OR 00906778
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=34443
fjournal: IEEE Transactions on Communications
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: T. H. Liew and Lie-Liang Yang and L. Hanzo
title:
Systematic redundant residue number system codes: analytical upper bound and iterative decoding performance over AWGN and Rayleigh channels

rawtitle:
Systematic redundant residue number system codes: analytical upper bound and iterative decoding performance over {AWGN} and {Rayleigh} channels

entry:
@Article{Liew:2006:SRR,
  author =       "T. H. Liew and Lie-Liang Yang and L. Hanzo",
  title =        "Systematic redundant residue number system codes:
                 analytical upper bound and iterative decoding
                 performance over {AWGN} and {Rayleigh} channels",
  journal =      j-IEEE-TRANS-COMM,
  volume =       "54",
  number =       "6",
  pages =        "1006--1016",
  month =        jun,
  year =         "2006",
  CODEN =        "IECMBT",
  DOI =          "https://doi.org/10.1109/TCOMM.2006.876843",
  ISSN =         "0090-6778 (print), 1558-0857 (electronic)",
  ISSN-L =       "0090-6778",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=34443",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Communications",
  keywords =     "residue arithmetic; residue number system",
  summary =      "The novel family of redundant residue number system
                 (RRNS) codes is studied. RRNS codes constitute
                 maximum-minimum distance block codes, exhibiting
                 identical distance properties to Reed--Solomon codes.
                 Binary to RRNS symbol-mapping methods are \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Lindstrom:2006:FEC
author: Peter Lindstrom and Martin Isenburg
title: Fast and Efficient Compression of Floating-Point Data
journal: j-IEEE-TRANS-VIS-COMPUT-GRAPH
volume: 12
number: 5
pages: 1245--1250
month: sep
monthnumber: 9
year: 2006
CODEN: ITVGEA
DOI: https://doi.org/10.1109/TVCG.2006.143
ISSNL: 1077-2626 OR 10772626
bibdate: Thu Jul 3 15:20:21 MDT 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.07.03 15:20:21 MDT
fjournal: IEEE Transactions on Visualization and Computer Graphics
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2945
rawauthor: Peter Lindstrom and Martin Isenburg
rawtitle: Fast and Efficient Compression of Floating-Point Data
ISSN:
1077-2626 (print), 1941-0506 (electronic), 2160-9306 OR 10772626 (print), 19410506 (electronic), 21609306

entry:
@Article{Lindstrom:2006:FEC,
  author =       "Peter Lindstrom and Martin Isenburg",
  title =        "Fast and Efficient Compression of Floating-Point
                 Data",
  journal =      j-IEEE-TRANS-VIS-COMPUT-GRAPH,
  volume =       "12",
  number =       "5",
  pages =        "1245--1250",
  month =        sep # "\slash " # oct,
  year =         "2006",
  CODEN =        "ITVGEA",
  DOI =          "https://doi.org/10.1109/TVCG.2006.143",
  ISSN =         "1077-2626 (print), 1941-0506 (electronic), 2160-9306",
  ISSN-L =       "1077-2626",
  bibdate =      "Thu Jul 3 15:20:21 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Visualization and Computer
                 Graphics",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2945",
}


bibtype: article
filename: fparith.bib
label: Mahalingam:2006:IAM
author: Venkatraman Mahalingam and Nagarajan Ranganathan
title: Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 12
pages: 1523--1535
month: dec
monthnumber: 12
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.198
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:57 MDT 2011
bibtimestamp: 2011.07.04 15:35:57 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1717385
fjournal: IEEE Transactions on Computers
remark: See cite Mitchell:1962:CMD.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Venkatraman Mahalingam and Nagarajan Ranganathan
rawtitle: Improving Accuracy in {Mitchell}'s Logarithmic Multiplication Using Operand Decomposition
entry:
@Article{Mahalingam:2006:IAM,
  author =       "Venkatraman Mahalingam and Nagarajan Ranganathan",
  title =        "Improving Accuracy in {Mitchell}'s Logarithmic
                 Multiplication Using Operand Decomposition",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "12",
  pages =        "1523--1535",
  month =        dec,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.198",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:57 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1717385",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "See \cite{Mitchell:1962:CMD}.",
}


bibtype: article
filename: fparith.bib
label: Marques:2006:BIF
author: Osni A. Marques and E. Jason Riedy and Christof Vomel
title: Benefits of IEEE-754 Features in Modern Symmetric Tridiagonal Eigensolvers
journal: j-SIAM-J-SCI-COMP
volume: 28
number: 5
pages: 1613--1633
month: jan
monthnumber: 1
year: 2006
CODEN: SJOCE3
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Wed May 19 10:43:43 MDT 2010
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/SISC/28/5; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.19 10:43:43 MDT
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: Osni A. Marques and E. Jason Riedy and Christof V{\"o}mel
rawtitle: Benefits of {IEEE-754} Features in Modern Symmetric Tridiagonal Eigensolvers
entry:
@Article{Marques:2006:BIF,
  author =       "Osni A. Marques and E. Jason Riedy and Christof
                 V{\"o}mel",
  title =        "Benefits of {IEEE-754} Features in Modern Symmetric
                 Tridiagonal Eigensolvers",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "28",
  number =       "5",
  pages =        "1613--1633",
  month =        jan,
  year =         "2006",
  CODEN =        "SJOCE3",
  DOI =          "",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Wed May 19 10:43:43 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/28/5;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
}


bibtype: inproceedings
filename: fparith.bib
label: Maslennikowa:2006:DFB
author: N. Maslennikowa and O. Maslennikow and R. Berezowski and J.-P. Lienou
title: Design of FPGA-based Multi-operand Modular Adders for Residue Number System Converters
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 264--268
year: 2006
DOI: https://doi.org/10.1109/ISCAS.2006.1693181
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: N. Maslennikowa and O. Maslennikow and R. Berezowski and J.-P. Lienou
rawtitle: Design of {FPGA}-based Multi-operand Modular Adders for Residue Number System Converters
booktitle:
MIXDES 2006, Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 22--24 June 2006

rawbooktitle:
{MIXDES 2006}, Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 22--24 June 2006

entry:
@InProceedings{Maslennikowa:2006:DFB,
  author =       "N. Maslennikowa and O. Maslennikow and R. Berezowski
                 and J.-P. Lienou",
  booktitle =    "{MIXDES 2006}, Proceedings of the International
                 Conference Mixed Design of Integrated Circuits and
                 System, 22--24 June 2006",
  title =        "Design of {FPGA}-based Multi-operand Modular Adders
                 for Residue Number System Converters",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "264--268",
  year =         "2006",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.2006.1693181",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
}


bibtype: phdthesis
filename: fparith.bib
label: Melquiond:2006:AIC
author: Guillaume Melquiond
type: Ph.D. dissertation
school: Ecole normale superieure de Lyon
address: Lyon, France
pages: vi + 126
day: 21
month: nov
monthnumber: 11
year: 2006
bibdate: Fri Sep 22 16:41:05 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 16:41:05 ???
URL: https://theses.hal.science/tel-01094485/file/06-these.pdf
acknowledgement: ack-nhfb
rawauthor: Guillaume Melquiond
title:
De l'arithmetique d'intervalles a la certification de programmes. (French) [From interval arithmetic to program certification]

abstract:
Computer numbers are usually limited, both in range and in precision. As a consequence, a careful certification has to be performed for applications that compute with these sets of numbers. Unfortunately, performing such a certification by hand is error-prone. Formal methods can ensure that the certification is correct, but making use of them is usually long and tedious, even for experts. This thesis aims at improving the availability of these methods to developers by automatizing their implementation. The key concepts are the use of interval arithmetic, a database of theorems on computer arithmetics, and a system for rewriting expressions in order to compute tight bounds on rounding errors.par This approach has led to the development of the Gappa tool. It is designed to verify the numeric properties of programs relying on floating-point or fixed-point arithmetic. When verifying these properties, the tool also generates formal proofs of their correctness. These proofs can later be mechanically checked by the Coq proof assistant. Gappa has been successfully used for certifying some functions of the CRlibm, CGAL, and FLIP libraries, among others

keywords:
Coq proof assistant; correct rounding; fixed-point arithmetic; floating-point arithmetic; formal methods; interval arithmetic; program certification

rawabstract:
Computer numbers are usually limited, both in range and in precision. As a consequence, a careful certification has to be performed for applications that compute with these sets of numbers. Unfortunately, performing such a certification by hand is error-prone. Formal methods can ensure that the certification is correct, but making use of them is usually long and tedious, even for experts. This thesis aims at improving the availability of these methods to developers by automatizing their implementation. The key concepts are the use of interval arithmetic, a database of theorems on computer arithmetics, and a system for rewriting expressions in order to compute tight bounds on rounding errors.\par This approach has led to the development of the Gappa tool. It is designed to verify the numeric properties of programs relying on floating-point or fixed-point arithmetic. When verifying these properties, the tool also generates formal proofs of their correctness. These proofs can later be mechanically checked by the Coq proof assistant. Gappa has been successfully used for certifying some functions of the CRlibm, CGAL, and FLIP libraries, among others

rawtitle:
De l'arithm{\'e}tique d'intervalles {\`a} la certification de programmes. ({French}) [{From} interval arithmetic to program certification]

entry:
@PhdThesis{Melquiond:2006:AIC,
  author =       "Guillaume Melquiond",
  title =        "De l'arithm{\'e}tique d'intervalles {\`a} la
                 certification de programmes. ({French}) [{From}
                 interval arithmetic to program certification]",
  type =         "Ph.D. dissertation",
  school =       "{\'E}cole normale sup{\'e}rieure de Lyon",
  address =      "Lyon, France",
  pages =        "vi + 126",
  day =          "21",
  month =        nov,
  year =         "2006",
  bibdate =      "Fri Sep 22 16:41:05 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://theses.hal.science/tel-01094485/file/06-these.pdf",
  abstract =     "Computer numbers are usually limited, both in range
                 and in precision. As a consequence, a careful
                 certification has to be performed for applications that
                 compute with these sets of numbers. Unfortunately,
                 performing such a certification by hand is error-prone.
                 Formal methods can ensure that the certification is
                 correct, but making use of them is usually long and
                 tedious, even for experts. This thesis aims at
                 improving the availability of these methods to
                 developers by automatizing their implementation. The
                 key concepts are the use of interval arithmetic, a
                 database of theorems on computer arithmetics, and a
                 system for rewriting expressions in order to compute
                 tight bounds on rounding errors.\par

                 This approach has led to the development of the Gappa
                 tool. It is designed to verify the numeric properties
                 of programs relying on floating-point or fixed-point
                 arithmetic. When verifying these properties, the tool
                 also generates formal proofs of their correctness.
                 These proofs can later be mechanically checked by the
                 Coq proof assistant. Gappa has been successfully used
                 for certifying some functions of the CRlibm, CGAL, and
                 FLIP libraries, among others",
  acknowledgement = ack-nhfb,
  keywords =     "Coq proof assistant; correct rounding; fixed-point
                 arithmetic; floating-point arithmetic; formal methods;
                 interval arithmetic; program certification",
}


bibtype: article
filename: fparith.bib
label: Meurant:2006:LCG
author: Gerard Meurant and Zdenek Strakos
title: The Lanczos and conjugate gradient algorithms in finite precision arithmetic
journal: j-ACTA-NUMERICA
volume: 15
pages: 471--542
year: 2006
CODEN: ANUMFU
DOI: https://doi.org/10.1017/S096249290626001X
ISBN: 0-521-86815-7 OR 0521868157
ISBN13: 978-0-521-86815-0 OR 9780521868150
ISSN: 0962-4929 (print), 1474-0508 (electronic) OR 09624929 (print), 14740508 (electronic)
ISSNL: 0962-4929 OR 09624929
MRclass: 65F15 (65F10 65G50)
MRnumber: 2269746 (2007m:65031)
MRreviewer: A. Bultheel
bibdate: Sat Sep 24 10:35:17 2011
bibtimestamp: 2011.09.24 10:35:17 ???
fjournal: Acta Numerica
acknowledgement: ack-nhfb
ajournal: Acta Numer.
journalURL: http://journals.cambridge.org/action/displayJournal?jid=ANU
onlinedate: 16 May 2006
rawauthor: G{\'e}rard Meurant and Zden{\v{e}}k Strako{\v{s}}
rawtitle: The {Lanczos} and conjugate gradient algorithms in finite precision arithmetic
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/l/lanczos-cornelius.bib; https://www.math.utah.edu/pub/tex/bib/actanumerica.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
The Lanczos and conjugate gradient algorithms were introduced more than five decades ago as tools for numerical computation of dominant eigenvalues of symmetric matrices and for solving linear algebraic systems with symmetric positive definite matrices, respectively. Because of their fundamental relationship with the theory of orthogonal polynomials and Gauss quadrature of the Riemann--Stieltjes integral, the Lanczos and conjugate gradient algorithms represent very interesting general mathematical objects, with highly nonlinear properties which can be conveniently translated from algebraic language into the language of mathematical analysis, and vice versa. The algorithms are also very interesting numerically, since their numerical behaviour can be explained by an elegant mathematical theory, and the interplay between analysis and algebra is useful there too.par Motivated by this view, the present contribution wishes to pay a tribute to those who have made an understanding of the Lanczos and conjugate gradient algorithms possible through their pioneering work, and to review recent solutions of several open problems that have also contributed to knowledge of the subject.

rawabstract:
The Lanczos and conjugate gradient algorithms were introduced more than five decades ago as tools for numerical computation of dominant eigenvalues of symmetric matrices and for solving linear algebraic systems with symmetric positive definite matrices, respectively. Because of their fundamental relationship with the theory of orthogonal polynomials and Gauss quadrature of the Riemann--Stieltjes integral, the Lanczos and conjugate gradient algorithms represent very interesting general mathematical objects, with highly nonlinear properties which can be conveniently translated from algebraic language into the language of mathematical analysis, and vice versa. The algorithms are also very interesting numerically, since their numerical behaviour can be explained by an elegant mathematical theory, and the interplay between analysis and algebra is useful there too.\par Motivated by this view, the present contribution wishes to pay a tribute to those who have made an understanding of the Lanczos and conjugate gradient algorithms possible through their pioneering work, and to review recent solutions of several open problems that have also contributed to knowledge of the subject.

entry:
@Article{Meurant:2006:LCG,
  author =       "G{\'e}rard Meurant and Zden{\v{e}}k Strako{\v{s}}",
  title =        "The {Lanczos} and conjugate gradient algorithms in
                 finite precision arithmetic",
  journal =      j-ACTA-NUMERICA,
  volume =       "15",
  pages =        "471--542",
  year =         "2006",
  CODEN =        "ANUMFU",
  DOI =          "https://doi.org/10.1017/S096249290626001X",
  ISBN =         "0-521-86815-7",
  ISBN-13 =      "978-0-521-86815-0",
  ISSN =         "0962-4929 (print), 1474-0508 (electronic)",
  ISSN-L =       "0962-4929",
  MRclass =      "65F15 (65F10 65G50)",
  MRnumber =     "2269746 (2007m:65031)",
  MRreviewer =   "A. Bultheel",
  bibdate =      "Sat Sep 24 10:35:17 2011",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/l/lanczos-cornelius.bib;
                 https://www.math.utah.edu/pub/tex/bib/actanumerica.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Lanczos and conjugate gradient algorithms were
                 introduced more than five decades ago as tools for
                 numerical computation of dominant eigenvalues of
                 symmetric matrices and for solving linear algebraic
                 systems with symmetric positive definite matrices,
                 respectively. Because of their fundamental relationship
                 with the theory of orthogonal polynomials and Gauss
                 quadrature of the Riemann--Stieltjes integral, the
                 Lanczos and conjugate gradient algorithms represent
                 very interesting general mathematical objects, with
                 highly nonlinear properties which can be conveniently
                 translated from algebraic language into the language of
                 mathematical analysis, and vice versa. The algorithms
                 are also very interesting numerically, since their
                 numerical behaviour can be explained by an elegant
                 mathematical theory, and the interplay between analysis
                 and algebra is useful there too.\par

                 Motivated by this view, the present contribution wishes
                 to pay a tribute to those who have made an
                 understanding of the Lanczos and conjugate gradient
                 algorithms possible through their pioneering work, and
                 to review recent solutions of several open problems
                 that have also contributed to knowledge of the
                 subject.",
  acknowledgement = ack-nhfb,
  ajournal =     "Acta Numer.",
  fjournal =     "Acta Numerica",
  journal-URL =  "http://journals.cambridge.org/action/displayJournal?jid=ANU",
  onlinedate =   "16 May 2006",
}


bibtype: misc
filename: fparith.bib
label: Muller:2006:CLA
author: Jean-Michel Muller
title: CR-LIBM, and Arenaire's results on function implementation
pages: 92
month: nov
monthnumber: 11
year: 2006
bibdate: Wed Nov 15 07:54:31 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.11.15 07:54:31 ???
URL: http://grouper.ieee.org/groups/754/email/pdfNTnWzhjsBA.pdf
acknowledgement: ack-nhfb
howpublished: World-Wide Web slides.
rawauthor: Jean-Michel Muller
rawtitle: {CR-LIBM}, and {Arenaire}'s results on function implementation
entry:
@Misc{Muller:2006:CLA,
  author =       "Jean-Michel Muller",
  title =        "{CR-LIBM}, and {Arenaire}'s results on function
                 implementation",
  howpublished = "World-Wide Web slides.",
  pages =        "92",
  month =        nov,
  year =         "2006",
  bibdate =      "Wed Nov 15 07:54:31 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://grouper.ieee.org/groups/754/email/pdfNTnWzhjsBA.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: Muller:2006:EFA
author: Jean-Michel Muller
title: Elementary functions: algorithms and implementation
publisher: pub-BIRKHAUSER
address: pub-BIRKHAUSER:adr
edition: Second
pages: xxii + 266
year: 2006
ISBN: 0-8176-4372-9 OR 0817643729
ISBN13: 978-0-8176-4372-0 OR 9780817643720
LCCN: QA331 .M866 2006
bibdate: Fri Jul 25 12:00:55 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; z3950.loc.gov:7090/Voyager
bibtimestamp: 1997.07.25 12:00:55 ???
subject: Functions; Data processing; Algorithms
acknowledgement: ack-nhfb
rawauthor: Jean-Michel Muller
rawtitle: Elementary functions: algorithms and implementation
URL:
http://perso.ens-lyon.fr/jean-michel.muller/SecondEdition.html; http://www.springer.com/sgw/cda/frontpage/0,,4-40109-22-72377986-0,00.html

TOC:
Preface to the second edition Preface to the first edition Introduction Some basic things about computer arithmetic Part I. Algorithms based on polynomial approximation and/or table lookup, multiple-precision evaluation of functions Polynomial or rational approximations Table-based methods Multiple-precision evaluation of functions Part II. Shift-and-add algorithms Introduction to shift-and-add algorithms The CORDIC algorithm Some other shift-and-add algorithms Part III. Range reduction, final rounding and exceptions Range reduction Final rounding Miscellaneous Examples of implementation Bibliography Index

rawTOC:
Preface to the second edition \\ Preface to the first edition \\ Introduction \\ Some basic things about computer arithmetic \\ Part I. Algorithms based on polynomial approximation and/or table lookup, multiple-precision evaluation of functions \\ Polynomial or rational approximations \\ Table-based methods \\ Multiple-precision evaluation of functions \\ Part II. Shift-and-add algorithms \\ Introduction to shift-and-add algorithms \\ The CORDIC algorithm \\ Some other shift-and-add algorithms \\ Part III. Range reduction, final rounding and exceptions \\ Range reduction \\ Final rounding \\ Miscellaneous \\ Examples of implementation \\ Bibliography \\ Index

entry:
@Book{Muller:2006:EFA,
  author =       "Jean-Michel Muller",
  title =        "Elementary functions: algorithms and implementation",
  publisher =    pub-BIRKHAUSER,
  address =      pub-BIRKHAUSER:adr,
  edition =      "Second",
  pages =        "xxii + 266",
  year =         "2006",
  ISBN =         "0-8176-4372-9",
  ISBN-13 =      "978-0-8176-4372-0",
  LCCN =         "QA331 .M866 2006",
  bibdate =      "Fri Jul 25 12:00:55 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 z3950.loc.gov:7090/Voyager",
  price =        "US\$59.95",
  URL =          "http://perso.ens-lyon.fr/jean-michel.muller/SecondEdition.html;
                 http://www.springer.com/sgw/cda/frontpage/0,,4-40109-22-72377986-0,00.html",
  acknowledgement = ack-nhfb,
  subject =      "Functions; Data processing; Algorithms",
  tableofcontents = "Preface to the second edition \\
                 Preface to the first edition \\
                 Introduction \\
                 Some basic things about computer arithmetic \\
                 Part I. Algorithms based on polynomial approximation
                 and/or table lookup, multiple-precision evaluation of
                 functions \\
                 Polynomial or rational approximations \\
                 Table-based methods \\
                 Multiple-precision evaluation of functions \\
                 Part II. Shift-and-add algorithms \\
                 Introduction to shift-and-add algorithms \\
                 The CORDIC algorithm \\
                 Some other shift-and-add algorithms \\
                 Part III. Range reduction, final rounding and
                 exceptions \\
                 Range reduction \\
                 Final rounding \\
                 Miscellaneous \\
                 Examples of implementation \\
                 Bibliography \\
                 Index",
}


bibtype: article
filename: fparith.bib
label: Nievergelt:2006:EPD
author: Yves Nievergelt
title: Extensions of Priest's Double-Precision Summation
journal: j-SIAM-J-SCI-COMP
volume: 28
number: 5
pages: 1837--1850
month: jan
monthnumber: 1
year: 2006
CODEN: SJOCE3
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Wed May 19 10:43:43 MDT 2010
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/SISC/28/5; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.19 10:43:43 MDT
fjournal: SIAM Journal on Scientific Computing
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: Yves Nievergelt
rawtitle: Extensions of {Priest}'s Double-Precision Summation
entry:
@Article{Nievergelt:2006:EPD,
  author =       "Yves Nievergelt",
  title =        "Extensions of {Priest}'s Double-Precision Summation",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "28",
  number =       "5",
  pages =        "1837--1850",
  month =        jan,
  year =         "2006",
  CODEN =        "SJOCE3",
  DOI =          "",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Wed May 19 10:43:43 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/28/5;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "accurate floating-point summation",
}


bibtype: article
filename: fparith.bib
label: Nikmehr:2006:FDF
author: H. Nikmehr and B. Phillips and C.-C. Lim
title: Fast Decimal Floating-Point Division
journal: j-IEEE-TRANS-VLSI-SYST
volume: 14
number: 9
pages: 951--961
month: sep
monthnumber: 9
year: 2006
CODEN: IEVSE9
DOI: https://doi.org/10.1109/TVLSI.2006.884047
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Mon Mar 19 10:15:51 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.19 10:15:51 ???
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: H. Nikmehr and B. Phillips and C.-C. Lim
rawtitle: Fast Decimal Floating-Point Division
abstract:
A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney, J. E. Robertson, and T. D. Tocher. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literature

rawabstract:
A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney, J. E. Robertson, and T. D. Tocher. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literature

entry:
@Article{Nikmehr:2006:FDF,
  author =       "H. Nikmehr and B. Phillips and C.-C. Lim",
  title =        "Fast Decimal Floating-Point Division",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "14",
  number =       "9",
  pages =        "951--961",
  month =        sep,
  year =         "2006",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2006.884047",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Mon Mar 19 10:15:51 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A new implementation for decimal floating-point (DFP)
                 division is introduced. The algorithm is based on
                 high-radix SRT division The SRT division algorithm is
                 named after D. Sweeney, J. E. Robertson, and T. D.
                 Tocher. with the recurrence in a new decimal
                 signed-digit format. Quotient digits are selected using
                 comparison multiples, where the magnitude of the
                 quotient digit is calculated by comparing the truncated
                 partial remainder with limited precision multiples of
                 the divisor. The sign is determined concurrently by
                 investigating the polarity of the truncated partial
                 remainder. A timing evaluation using a logic synthesis
                 shows a significant decrease in the division execution
                 time in contrast with one of the fastest DFP dividers
                 reported in the open literature",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: OLeary:2006:CMA
author: Dianne P. O'Leary
title: Computer Memory and Arithmetic: a Look under the Hood
journal: j-COMPUT-SCI-ENG
volume: 8
number: 3
pages: 54--59
month: may
monthnumber: 5
year: 2006
CODEN: CSENFA
DOI: https://doi.org/10.1109/MCSE.2006.39
ISSN: 1521-9615 (print), 1558-366X (electronic) OR 15219615 (print), 1558366X (electronic)
ISSNL: 1521-9615 OR 15219615
bibdate: Thu Jul 3 11:16:38 MDT 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.07.03 11:16:38 MDT
fjournal: Computing in Science and Engineering
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5992
rawauthor: Dianne P. O'Leary
rawtitle: Computer Memory and Arithmetic: a Look under the Hood
abstract:
Computers have a hierarchy of storage units. Memory management systems try to store information that you will soon need in a unit that gives fast access. This means that large vectors and arrays are broken up and moved piece by piece as needed. You can write a correct computer program without ever knowing about memory management, but attention to memory management allows you to consistently write programs that don't have excessive memory delays. In this paper, we consider a model of computer memory organization. We hide some detail but give enough information to let us make decisions about how to organize our computations for efficiency. We use mathematical modeling to estimate a typical computer's memory parameters, and then we see how important these parameters are relative to the speed of floating-point arithmetic.

rawabstract:
Computers have a hierarchy of storage units. Memory management systems try to store information that you will soon need in a unit that gives fast access. This means that large vectors and arrays are broken up and moved piece by piece as needed. You can write a correct computer program without ever knowing about memory management, but attention to memory management allows you to consistently write programs that don't have excessive memory delays. In this paper, we consider a model of computer memory organization. We hide some detail but give enough information to let us make decisions about how to organize our computations for efficiency. We use mathematical modeling to estimate a typical computer's memory parameters, and then we see how important these parameters are relative to the speed of floating-point arithmetic.

entry:
@Article{OLeary:2006:CMA,
  author =       "Dianne P. O'Leary",
  title =        "Computer Memory and Arithmetic: a Look under the
                 Hood",
  journal =      j-COMPUT-SCI-ENG,
  volume =       "8",
  number =       "3",
  pages =        "54--59",
  month =        may # "\slash " # jun,
  year =         "2006",
  CODEN =        "CSENFA",
  DOI =          "https://doi.org/10.1109/MCSE.2006.39",
  ISSN =         "1521-9615 (print), 1558-366X (electronic)",
  ISSN-L =       "1521-9615",
  bibdate =      "Thu Jul 3 11:16:38 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Computers have a hierarchy of storage units. Memory
                 management systems try to store information that you
                 will soon need in a unit that gives fast access. This
                 means that large vectors and arrays are broken up and
                 moved piece by piece as needed. You can write a correct
                 computer program without ever knowing about memory
                 management, but attention to memory management allows
                 you to consistently write programs that don't have
                 excessive memory delays. In this paper, we consider a
                 model of computer memory organization. We hide some
                 detail but give enough information to let us make
                 decisions about how to organize our computations for
                 efficiency. We use mathematical modeling to estimate a
                 typical computer's memory parameters, and then we see
                 how important these parameters are relative to the
                 speed of floating-point arithmetic.",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing in Science and Engineering",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5992",
}


bibtype: article
filename: fparith.bib
label: Ou:2006:DSE
author: Jingzhao Ou and Viktor K. Prasanna
journal: j-TECS
volume: 5
number: 2
pages: 355--382
month: may
monthnumber: 5
year: 2006
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Wed Aug 23 05:26:43 MDT 2006
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.08.23 05:26:43 MDT
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?&idx=J840
rawauthor: Jingzhao Ou and Viktor K. Prasanna
title:
Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms

rawtitle:
Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms

entry:
@Article{Ou:2006:DSE,
  author =       "Jingzhao Ou and Viktor K. Prasanna",
  title =        "Design space exploration using arithmetic-level
                 hardware--software cosimulation for configurable
                 multiprocessor platforms",
  journal =      j-TECS,
  volume =       "5",
  number =       "2",
  pages =        "355--382",
  month =        may,
  year =         "2006",
  CODEN =        "????",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Wed Aug 23 05:26:43 MDT 2006",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?&idx=J840",
}


bibtype: article
filename: fparith.bib
label: Ozban:2006:NMA
author: Ahmet Yasar Ozban
title: New methods for approximating square roots
journal: j-APPL-MATH-COMP
volume: 175
number: 1
pages: 532--540
day: 1
month: apr
monthnumber: 4
year: 2006
CODEN: AMHCBQ
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Sat Jul 12 09:02:54 MDT 2008
bibtimestamp: 2008.07.12 09:02:54 MDT
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: Ahmet Ya{\c{s}}ar {\"O}zban
rawtitle: New methods for approximating square roots
entry:
@Article{Ozban:2006:NMA,
  author =       "Ahmet Ya{\c{s}}ar {\"O}zban",
  title =        "New methods for approximating square roots",
  journal =      j-APPL-MATH-COMP,
  volume =       "175",
  number =       "1",
  pages =        "532--540",
  day =          "1",
  month =        apr,
  year =         "2006",
  CODEN =        "AMHCBQ",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Sat Jul 12 09:02:54 MDT 2008",
  bibsource =    "http://www.sciencedirect.com/science/journal/00963003;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
}


bibtype: article
filename: fparith.bib
label: Park:2006:EBP
author: Sun-Mi Park and Ku-Young Chang and Dowon Hong
title: Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 9
pages: 1211--1215
month: sep
monthnumber: 9
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.146
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:56 MDT 2011
bibtimestamp: 2011.07.04 15:35:56 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1668049
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Sun-Mi Park and Ku-Young Chang and Dowon Hong
rawtitle: Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis
entry:
@Article{Park:2006:EBP,
  author =       "Sun-Mi Park and Ku-Young Chang and Dowon Hong",
  title =        "Efficient Bit-Parallel Multiplier for Irreducible
                 Pentanomials Using a Shifted Polynomial Basis",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "9",
  pages =        "1211--1215",
  month =        sep,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.146",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:56 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1668049",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Parks:2006:UTS
author: Michael Parks
title: Unifying Tests for Square Root
crossref: Anonymous:2006:PCR
pages: ??--??
year: 2006
bibdate: Tue Jun 27 10:28:05 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.06.27 10:28:05 ???
keywords: elementary functions; floating-point testing
acknowledgement: ack-nhfb
rawauthor: Michael Parks
rawtitle: Unifying Tests for Square Root
entry:
@InProceedings{Parks:2006:UTS,
  author =       "Michael Parks",
  title =        "Unifying Tests for Square Root",
  crossref =     "Anonymous:2006:PCR",
  pages =        "??--??",
  year =         "2006",
  bibdate =      "Tue Jun 27 10:28:05 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "elementary functions; floating-point testing",
}


bibtype: article
filename: fparith.bib
label: Perry:2006:BSF
author: Tekla S. Perry
title: Building a supercomputer in a flash
journal: j-IEEE-SPECTRUM
volume: 41
number: 6
pages: 24--25
month: jun
monthnumber: 6
year: 2006
CODEN: IEESAM
DOI: https://doi.org/10.1109/MSPEC.2004.1303368
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Thu Sep 01 16:21:26 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.01 16:21:26 ???
fjournal: IEEE Spectrum
keywords: floating-point arithmetic
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: Tekla S. Perry
rawtitle: Building a supercomputer in a flash
remark:
Flash mob linked 669 PCs at UCSF in six hours to produce a LINPACK speed of 180 Gflops (below the 500 Gflops goal).

entry:
@Article{Perry:2006:BSF,
  author =       "Tekla S. Perry",
  title =        "Building a supercomputer in a flash",
  journal =      j-IEEE-SPECTRUM,
  volume =       "41",
  number =       "6",
  pages =        "24--25",
  month =        jun,
  year =         "2006",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/MSPEC.2004.1303368",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Thu Sep 01 16:21:26 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "floating-point arithmetic",
  remark =       "Flash mob linked 669 PCs at UCSF in six hours to
                 produce a LINPACK speed of 180 Gflops (below the 500
                 Gflops goal).",
}


bibtype: inproceedings
filename: fparith.bib
label: Persson:2006:RCA
author: A. Persson and L. Bengtsson
booktitle: ISCAS 2006, Proceedings, 2006 IEEE International Symposium on Circuits and Systems, 21--24 May 2006
title: Reverse conversion architectures for signed-digit residue number systems
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 4
year: 2006
DOI: https://doi.org/10.1109/ISCAS.2006.1693181
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. Persson and L. Bengtsson
rawtitle: Reverse conversion architectures for signed-digit residue number systems
rawbooktitle:
{ISCAS 2006}, Proceedings, 2006 {IEEE} International Symposium on Circuits and Systems, 21--24 May 2006

entry:
@InProceedings{Persson:2006:RCA,
  author =       "A. Persson and L. Bengtsson",
  booktitle =    "{ISCAS 2006}, Proceedings, 2006 {IEEE} International
                 Symposium on Circuits and Systems, 21--24 May 2006",
  title =        "Reverse conversion architectures for signed-digit
                 residue number systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "4",
  year =         "2006",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.2006.1693181",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "This paper presents circuits for conversion from
                 radix-2 signed-digit residue numbers to binary form.
                 Four reverse converters for combined RNS/SD number
                 systems based on different moduli sets are presented.
                 Implementations are compared with respect \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Piso:2006:OMD
author: D. Piso and J. D. Bruguera
title: Optimizing the Multiplier Design for Goldschmidt's Division and Reciprocal Units
pages: 1C.3--??
year: 2006
bibdate: Sun Dec 10 14:00:32 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.10 14:00:32 ???
remark: TO DO: [11-Dec-2023] I cannot yet locate this article.
acknowledgement: ack-nhfb
rawauthor: D. Piso and J. D. Bruguera
rawtitle: Optimizing the Multiplier Design for {Goldschmidt}'s Division and Reciprocal Units
booktitle:
Proceedings of the XXI Conference on Design of Circuits and Integrated Systems (DSIS2006, Barcelona, 2006)

rawbooktitle:
Proceedings of the {XXI} Conference on Design of Circuits and Integrated Systems ({DSIS2006, Barcelona, 2006})

entry:
@InProceedings{Piso:2006:OMD,
  author =       "D. Piso and J. D. Bruguera",
  editor =       "????",
  booktitle =    "Proceedings of the {XXI} Conference on Design of
                 Circuits and Integrated Systems ({DSIS2006, Barcelona,
                 2006})",
  title =        "Optimizing the Multiplier Design for {Goldschmidt}'s
                 Division and Reciprocal Units",
  publisher =    "????",
  address =      "????",
  pages =        "1C.3--??",
  year =         "2006",
  bibdate =      "Sun Dec 10 14:00:32 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  remark =       "TO DO: [11-Dec-2023] I cannot yet locate this
                 article.",
}


bibtype: article
filename: fparith.bib
label: Pryce:2006:IAC
author: J. D. Pryce and G. F. Corliss
title: Interval Arithmetic with Containment Sets
journal: j-COMPUTING
volume: 78
number: 3
pages: 251--276
month: nov
monthnumber: 11
year: 2006
CODEN: CMPTA2
DOI: https://doi.org/10.1007/s00607-006-0180-4
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
MRclass: 54D35; 65-02; 65G30; 65G40
bibdate: Tue Jul 8 22:32:47 MDT 2008
bibtimestamp: 2008.07.08 22:32:47 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=78&issue=3&spage=251
fjournal: Computing: Archiv fur informatik und numerik
keywords: containment set; cset; division by zero; infinity; interval arithmetic; validated computation
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/607
rawauthor: J. D. Pryce and G. F. Corliss
rawtitle: Interval Arithmetic with Containment Sets
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=78&issue=3; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Pryce:2006:IAC,
  author =       "J. D. Pryce and G. F. Corliss",
  title =        "Interval Arithmetic with Containment Sets",
  journal =      j-COMPUTING,
  volume =       "78",
  number =       "3",
  pages =        "251--276",
  month =        nov,
  year =         "2006",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/s00607-006-0180-4",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  MRclass =      "54D35; 65-02; 65G30; 65G40",
  bibdate =      "Tue Jul 8 22:32:47 MDT 2008",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=78&issue=3;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=78&issue=3&spage=251",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
  keywords =     "containment set; cset; division by zero; infinity;
                 interval arithmetic; validated computation",
}


bibtype: article
filename: fparith.bib
label: Qian:2006:HMP
author: Jianbo Qian and Cao An Wang
title: How much precision is needed to compare two sums of square roots of integers?
journal: j-INFO-PROC-LETT
volume: 100
number: 5
pages: 194--198
day: 16
month: dec
monthnumber: 12
year: 2006
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Thu Mar 31 15:52:31 MDT 2011
bibtimestamp: 2011.03.31 15:52:31 MDT
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: Jianbo Qian and Cao An Wang
rawtitle: How much precision is needed to compare two sums of square roots of integers?
entry:
@Article{Qian:2006:HMP,
  author =       "Jianbo Qian and Cao An Wang",
  title =        "How much precision is needed to compare two sums of
                 square roots of integers?",
  journal =      j-INFO-PROC-LETT,
  volume =       "100",
  number =       "5",
  pages =        "194--198",
  day =          "16",
  month =        dec,
  year =         "2006",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Thu Mar 31 15:52:31 MDT 2011",
  bibsource =    "http://www.sciencedirect.com/science/journal/00200190;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: article
filename: fparith.bib
label: Rajagopal:2006:TOA
author: S. Rajagopal and J. R. Cavallaro
title: Truncated Online Arithmetic with Applications to Communication Systems
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 10
pages: 1240--1252
month: oct
monthnumber: 10
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.168
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:56 MDT 2011
bibtimestamp: 2011.07.04 15:35:56 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1683755
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Rajagopal and J. R. Cavallaro
rawtitle: Truncated Online Arithmetic with Applications to Communication Systems
entry:
@Article{Rajagopal:2006:TOA,
  author =       "S. Rajagopal and J. R. Cavallaro",
  title =        "Truncated Online Arithmetic with Applications to
                 Communication Systems",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "10",
  pages =        "1240--1252",
  month =        oct,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.168",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:56 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1683755",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Shen:2006:TAS
author: Xunyang Shen and Peter R. Turner
title: Taylor approximation for symmetric level-index arithmetic processing
journal: j-IMA-J-NUMER-ANAL
volume: 26
number: 3
pages: 584--603
month: jul
monthnumber: 7
year: 2006
CODEN: IJNADH
DOI: https://doi.org/10.1093/imanum/drl004
ISSN: 0272-4979 (print), 1464-3642 (electronic) OR 02724979 (print), 14643642 (electronic)
ISSNL: 0272-4979 OR 02724979
bibdate: Tue Jun 24 12:23:09 MDT 2008
bibtimestamp: 2008.06.24 12:23:09 MDT
fjournal: IMA Journal of Numerical Analysis
acknowledgement: ack-nhfb
journalURL: http://imajna.oxfordjournals.org/content/by/year
rawauthor: Xunyang Shen and Peter R. Turner
rawtitle: {Taylor} approximation for symmetric level-index arithmetic processing
bibsource:
http://imanum.oxfordjournals.org/content/vol26/issue3/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://comjnl.oxfordjournals.org/cgi/content/abstract/26/3/584; http://comjnl.oxfordjournals.org/cgi/reprint/26/3/584

entry:
@Article{Shen:2006:TAS,
  author =       "Xunyang Shen and Peter R. Turner",
  title =        "{Taylor} approximation for symmetric level-index
                 arithmetic processing",
  journal =      j-IMA-J-NUMER-ANAL,
  volume =       "26",
  number =       "3",
  pages =        "584--603",
  month =        jul,
  year =         "2006",
  CODEN =        "IJNADH",
  DOI =          "https://doi.org/10.1093/imanum/drl004",
  ISSN =         "0272-4979 (print), 1464-3642 (electronic)",
  ISSN-L =       "0272-4979",
  bibdate =      "Tue Jun 24 12:23:09 MDT 2008",
  bibsource =    "http://imanum.oxfordjournals.org/content/vol26/issue3/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://comjnl.oxfordjournals.org/cgi/content/abstract/26/3/584;
                 http://comjnl.oxfordjournals.org/cgi/reprint/26/3/584",
  acknowledgement = ack-nhfb,
  fjournal =     "IMA Journal of Numerical Analysis",
  journal-URL =  "http://imajna.oxfordjournals.org/content/by/year",
}


bibtype: article
filename: fparith.bib
label: Shou:2006:MAA
author: Huahao Shou and Hongwei Lin and Ralph R. Martin and Guojin Wang
journal: j-J-COMPUT-APPL-MATH
volume: 195
number: 1--2
pages: 155--171
day: 15
month: oct
monthnumber: 10
year: 2006
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:12:01 MST 2017
bibtimestamp: 2017.02.25 13:12:01 MST
URL: http://www.sciencedirect.com/science/article/pii/S0377042705004814
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Huahao Shou and Hongwei Lin and Ralph R. Martin and Guojin Wang
title:
Modified affine arithmetic in tensor form for trivariate polynomial evaluation and algebraic surface plotting

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2005.bib

rawtitle:
Modified affine arithmetic in tensor form for trivariate polynomial evaluation and algebraic surface plotting

entry:
@Article{Shou:2006:MAA,
  author =       "Huahao Shou and Hongwei Lin and Ralph R. Martin and
                 Guojin Wang",
  title =        "Modified affine arithmetic in tensor form for
                 trivariate polynomial evaluation and algebraic surface
                 plotting",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "195",
  number =       "1--2",
  pages =        "155--171",
  day =          "15",
  month =        oct,
  year =         "2006",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:12:01 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2005.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042705004814",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: article
filename: fparith.bib
label: Singh:2006:IEE
author: S. B. Singh and H. S. Kasana
title: Improved estimates for error in floating point representation analysis
journal: j-BULL-CALCUTTA-MATH-SOC
volume: 98
number: 2
pages: 117--124
year: 2006
CODEN: BCMSA5
ISSN: 0008-0659 OR 00080659
MRclass: 65G50
MRnumber: MR2217971 (2006k:65128)
bibdate: Thu Nov 8 19:16:14 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:16:14 ???
fjournal: Bulletin of the Calcutta Mathematical Society
keywords: rounding errors
acknowledgement: ack-nhfb
journalURL: http://bulletin.calmathsoc.org/database.php
rawauthor: S. B. Singh and H. S. Kasana
rawtitle: Improved estimates for error in floating point representation analysis
entry:
@Article{Singh:2006:IEE,
  author =       "S. B. Singh and H. S. Kasana",
  title =        "Improved estimates for error in floating point
                 representation analysis",
  journal =      j-BULL-CALCUTTA-MATH-SOC,
  volume =       "98",
  number =       "2",
  pages =        "117--124",
  year =         "2006",
  CODEN =        "BCMSA5",
  ISSN =         "0008-0659",
  MRclass =      "65G50",
  MRnumber =     "MR2217971 (2006k:65128)",
  bibdate =      "Thu Nov 8 19:16:14 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Bulletin of the Calcutta Mathematical Society",
  journal-URL =  "http://bulletin.calmathsoc.org/database.php",
  keywords =     "rounding errors",
}


bibtype: article
filename: fparith.bib
label: Solymosi:2006:APS
author: Jozsef Solymosi
title: Arithmetic Progressions in Sets with Small Sumsets
journal: j-COMBIN-PROBAB-COMPUT
volume: 15
number: 4
pages: 597--603
month: jul
monthnumber: 7
year: 2006
CODEN: CPCOFG
DOI: https://doi.org/10.1017/S0963548306007516
ISSN: 0963-5483 (print), 1469-2163 (electronic) OR 09635483 (print), 14692163 (electronic)
ISSNL: 0963-5483 OR 09635483
bibdate: Mon Jul 7 15:38:18 MDT 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.07.07 15:38:18 MDT
URL: http://journals.cambridge.org/action/displayIssue?jid=CPC&volumeId=15&issueId=04
acknowledgement: ack-nhfb
journalURL: http://journals.cambridge.org/action/displayJournal?jid=CPC
rawauthor: J{\'o}zsef Solymosi
rawtitle: Arithmetic Progressions in Sets with Small Sumsets
entry:
@Article{Solymosi:2006:APS,
  author =       "J{\'o}zsef Solymosi",
  title =        "Arithmetic Progressions in Sets with Small Sumsets",
  journal =      j-COMBIN-PROBAB-COMPUT,
  volume =       "15",
  number =       "4",
  pages =        "597--603",
  month =        jul,
  year =         "2006",
  CODEN =        "CPCOFG",
  DOI =          "https://doi.org/10.1017/S0963548306007516",
  ISSN =         "0963-5483 (print), 1469-2163 (electronic)",
  ISSN-L =       "0963-5483",
  bibdate =      "Mon Jul 7 15:38:18 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://journals.cambridge.org/action/displayIssue?jid=CPC&volumeId=15&issueId=04",
  acknowledgement = ack-nhfb,
  journal-URL =  "http://journals.cambridge.org/action/displayJournal?jid=CPC",
}


bibtype: book
filename: fparith.bib
label: StDenis:2006:BMH
author: Tom St Denis and Greg Rose
title: BigNum Math: Implementing Cryptographic Multiple Precision Arithmetic
publisher: pub-SYNGRESS
address: pub-SYNGRESS:adr
pages: xviii + 296
year: 2006
ISBN: 1-59749-112-8 OR 1597491128
ISBN13: 978-1-59749-112-9 OR 9781597491129
LCCN: QA402.5 2006
bibdate: Fri Jun 12 07:26:51 MDT 2009
bibtimestamp: 2009.06.12 07:26:51 MDT
URL: http://www.oreilly.com/catalog/1597491128/index.html
keywords: Karatsuba multiplication; modular exponentiation; Montgomery reduction
acknowledgement: ack-nhfb
rawauthor: Tom {St Denis} and Greg Rose
rawtitle: {BigNum} Math: Implementing Cryptographic Multiple Precision Arithmetic
bibsource:
clas.caltech.edu:210/INNOPAC; https://www.math.utah.edu/pub/tex/bib/cryptography2000.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib; z3950.bibsys.no:2100/BIBSYS

TOC:
Introduction Multiple Precision Arithmetic Exercises Portability and Stability Getting Started Maintenance Algorithms Basic Operations Sign Manipulation Basic Arithmetic Multiplication and Squaring The Multipliers Multiplication Modular Reduction Basics of Modular Reduction Exponentiation Exponentiation Basics Higher Level Algorithms Number Theoretic Algorithms

rawTOC:
Introduction \\ Multiple Precision Arithmetic \\ Exercises \\ Portability and Stability \\ Getting Started \\ Maintenance Algorithms \\ Basic Operations \\ Sign Manipulation \\ Basic Arithmetic \\ Multiplication and Squaring \\ The Multipliers \\ Multiplication \\ Modular Reduction \\ Basics of Modular Reduction \\ Exponentiation \\ Exponentiation Basics \\ Higher Level Algorithms \\ Number Theoretic Algorithms

entry:
@Book{StDenis:2006:BMH,
  author =       "Tom {St Denis} and Greg Rose",
  title =        "{BigNum} Math: Implementing Cryptographic Multiple
                 Precision Arithmetic",
  publisher =    pub-SYNGRESS,
  address =      pub-SYNGRESS:adr,
  pages =        "xviii + 296",
  year =         "2006",
  ISBN =         "1-59749-112-8",
  ISBN-13 =      "978-1-59749-112-9",
  LCCN =         "QA402.5 2006",
  bibdate =      "Fri Jun 12 07:26:51 MDT 2009",
  bibsource =    "clas.caltech.edu:210/INNOPAC;
                 https://www.math.utah.edu/pub/tex/bib/cryptography2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 z3950.bibsys.no:2100/BIBSYS",
  URL =          "http://www.oreilly.com/catalog/1597491128/index.html",
  acknowledgement = ack-nhfb,
  keywords =     "Karatsuba multiplication; modular exponentiation;
                 Montgomery reduction",
  tableofcontents = "Introduction \\
                 Multiple Precision Arithmetic \\
                 Exercises \\
                 Portability and Stability \\
                 Getting Started \\
                 Maintenance Algorithms \\
                 Basic Operations \\
                 Sign Manipulation \\
                 Basic Arithmetic \\
                 Multiplication and Squaring \\
                 The Multipliers \\
                 Multiplication \\
                 Modular Reduction \\
                 Basics of Modular Reduction \\
                 Exponentiation \\
                 Exponentiation Basics \\
                 Higher Level Algorithms \\
                 Number Theoretic Algorithms",
}


bibtype: book
filename: fparith.bib
label: StDenis:2006:BMI
author: Tom St. Denis
title: BigNum Math: Implementing Cryptographic Multiple Precision Arithmetic
publisher: pub-SYNGRESS
address: pub-SYNGRESS:adr
pages: xviii + 296
year: 2006
ISBN: 1-59749-112-8 OR 1597491128
ISBN13: 978-1-59749-112-9 OR 9781597491129
LCCN: QA402.5 .S73 2006
bibdate: Thu Oct 19 19:07:57 2006
bibsource: clas.caltech.edu:210/INNOPAC; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.10.19 19:07:57 ???
URL: http://www.oreilly.com/catalog/1597491128/index.html
keywords: Karatsuba multiplication; modular exponentiation; Montgomery reduction
acknowledgement: ack-nhfb
rawauthor: Tom {St. Denis}
rawtitle: {BigNum} Math: Implementing Cryptographic Multiple Precision Arithmetic
entry:
@Book{StDenis:2006:BMI,
  author =       "Tom {St. Denis}",
  title =        "{BigNum} Math: Implementing Cryptographic Multiple
                 Precision Arithmetic",
  publisher =    pub-SYNGRESS,
  address =      pub-SYNGRESS:adr,
  pages =        "xviii + 296",
  year =         "2006",
  ISBN =         "1-59749-112-8",
  ISBN-13 =      "978-1-59749-112-9",
  LCCN =         "QA402.5 .S73 2006",
  bibdate =      "Thu Oct 19 19:07:57 2006",
  bibsource =    "clas.caltech.edu:210/INNOPAC;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "US\$49.95",
  URL =          "http://www.oreilly.com/catalog/1597491128/index.html",
  acknowledgement = ack-nhfb,
  keywords =     "Karatsuba multiplication; modular exponentiation;
                 Montgomery reduction",
}


bibtype: misc
filename: fparith.bib
label: Steele:2006:FPM
author: Guy L. Steele Jr.
title: Floating point multiplier for delimited operands
pages: xviii + 296
day: 21
month: feb
monthnumber: 2
year: 2006
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/7003540/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7003540
rawauthor: Guy L. {Steele Jr.}
rawtitle: Floating point multiplier for delimited operands
abstract:
A method for providing a floating point product consistent with the present invention includes multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages. The method further includes correcting an error introduced by the subprecise operand by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand.

rawabstract:
A method for providing a floating point product consistent with the present invention includes multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages. The method further includes correcting an error introduced by the subprecise operand by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand.

entry:
@Misc{Steele:2006:FPM,
  author =       "Guy L. {Steele Jr.}",
  title =        "Floating point multiplier for delimited operands",
  howpublished = "US Patent 7003540",
  day =          "21",
  month =        feb,
  year =         "2006",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7003540/fulltext.html",
  abstract =     "A method for providing a floating point product
                 consistent with the present invention includes
                 multiplying a subprecise operand and a non-subprecise
                 operand using a plurality of intermediate stages. The
                 method further includes correcting an error introduced
                 by the subprecise operand by performing an operation in
                 conjunction with a one of the plurality of intermediate
                 stages utilizing a compensating summand.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Steele:2006:FPSa
author: Guy L. Steele Jr.
title: Floating point system with improved support of interval arithmetic
pages: xviii + 296
day: 27
month: jun
monthnumber: 6
year: 2006
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/7069288/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7069288
rawauthor: Guy L. {Steele Jr.}
rawtitle: Floating point system with improved support of interval arithmetic
abstract:
Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One embodiment consistent with the principles of the present invention provides a method of enhancing support of an interval computation when performing a floating point arithmetic operation, comprising the steps, performed by a processor, of receiving a first floating point operand, receiving a second floating point operand, executing the floating point arithmetic operation on the first floating point operand and the second floating point operand, determining whether a NaN substitution is necessary, producing a floating point result if the NaN substitution is determined to be unnecessary, and substituting an alternative value as the floating point result if the NaN substitution is determined to be necessary.

rawabstract:
Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One embodiment consistent with the principles of the present invention provides a method of enhancing support of an interval computation when performing a floating point arithmetic operation, comprising the steps, performed by a processor, of receiving a first floating point operand, receiving a second floating point operand, executing the floating point arithmetic operation on the first floating point operand and the second floating point operand, determining whether a NaN substitution is necessary, producing a floating point result if the NaN substitution is determined to be unnecessary, and substituting an alternative value as the floating point result if the NaN substitution is determined to be necessary.

entry:
@Misc{Steele:2006:FPSa,
  author =       "Guy L. {Steele Jr.}",
  title =        "Floating point system with improved support of
                 interval arithmetic",
  howpublished = "US Patent 7069288",
  day =          "27",
  month =        jun,
  year =         "2006",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7069288/fulltext.html",
  abstract =     "Embodiments consistent with the principles of the
                 present invention provide improved results, compared to
                 IEEE Std. 754, for floating point operations used in
                 interval arithmetic calculations. One embodiment
                 consistent with the principles of the present invention
                 provides a method of enhancing support of an interval
                 computation when performing a floating point arithmetic
                 operation, comprising the steps, performed by a
                 processor, of receiving a first floating point operand,
                 receiving a second floating point operand, executing
                 the floating point arithmetic operation on the first
                 floating point operand and the second floating point
                 operand, determining whether a NaN substitution is
                 necessary, producing a floating point result if the NaN
                 substitution is determined to be unnecessary, and
                 substituting an alternative value as the floating point
                 result if the NaN substitution is determined to be
                 necessary.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Steele:2006:FPSb
author: Guy L. Steele Jr.
title: Floating point status information testing circuit
pages: xviii + 296
day: 21
month: mar
monthnumber: 3
year: 2006
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/7016928/fulltext.html
keywords: floating-point testing
acknowledgement: ack-nhfb
howpublished: US Patent 7016928
rawauthor: Guy L. {Steele Jr.}
rawtitle: Floating point status information testing circuit
abstract:
A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point operand based upon data within the operand. An operand buffer may supply the operand to the analysis circuit. The result generator circuit is responsive to at least one control signal and asserts a result signal if the floating point analysis circuit matches the floating point status to a predetermined format specified by the control signal. The result signal can condition the outcome of a floating point instruction. The result generator may also respond to multiple control signals asserted when testing a single operand for different formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, exact, and inexact.

rawabstract:
A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point operand based upon data within the operand. An operand buffer may supply the operand to the analysis circuit. The result generator circuit is responsive to at least one control signal and asserts a result signal if the floating point analysis circuit matches the floating point status to a predetermined format specified by the control signal. The result signal can condition the outcome of a floating point instruction. The result generator may also respond to multiple control signals asserted when testing a single operand for different formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, exact, and inexact.

entry:
@Misc{Steele:2006:FPSb,
  author =       "Guy L. {Steele Jr.}",
  title =        "Floating point status information testing circuit",
  howpublished = "US Patent 7016928",
  day =          "21",
  month =        mar,
  year =         "2006",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7016928/fulltext.html",
  abstract =     "A floating point operand testing circuit includes an
                 analysis circuit and a result generator circuit coupled
                 to the analysis circuit. The analysis circuit
                 determines the status of a floating point operand based
                 upon data within the operand. An operand buffer may
                 supply the operand to the analysis circuit. The result
                 generator circuit is responsive to at least one control
                 signal and asserts a result signal if the floating
                 point analysis circuit matches the floating point
                 status to a predetermined format specified by the
                 control signal. The result signal can condition the
                 outcome of a floating point instruction. The result
                 generator may also respond to multiple control signals
                 asserted when testing a single operand for different
                 formats, such as not-a-number (NaN), infinity,
                 normalized, denormalized, invalid operation, overflow,
                 underflow, division by zero, exact, and inexact.",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point testing",
}


bibtype: misc
filename: fparith.bib
label: Steele:2006:FPU
author: Guy L. Steele Jr.
title: Floating point unit for detecting and representing inexact computations without flags or traps
pages: xviii + 296
day: 27
month: jun
monthnumber: 6
year: 2006
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/7069289/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7069289
rawauthor: Guy L. {Steele Jr.}
rawtitle: Floating point unit for detecting and representing inexact computations without flags or traps
abstract:
A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a separate floating point status register for the inexact status information. In one embodiment, inexact status information is preserved by determining whether the at least one operand is inexact. Further, an intermediate result of the floating point computation is analyzed to determine whether it is inexact. Finally, the intermediate result is rounded based on whether the at least one operand is inexact and whether the intermediate result is inexact to preserve an inexact status of the at least one operand and the intermediate result.

rawabstract:
A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a separate floating point status register for the inexact status information. In one embodiment, inexact status information is preserved by determining whether the at least one operand is inexact. Further, an intermediate result of the floating point computation is analyzed to determine whether it is inexact. Finally, the intermediate result is rounded based on whether the at least one operand is inexact and whether the intermediate result is inexact to preserve an inexact status of the at least one operand and the intermediate result.

entry:
@Misc{Steele:2006:FPU,
  author =       "Guy L. {Steele Jr.}",
  title =        "Floating point unit for detecting and representing
                 inexact computations without flags or traps",
  howpublished = "US Patent 7069289",
  day =          "27",
  month =        jun,
  year =         "2006",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7069289/fulltext.html",
  abstract =     "A method and system perform a rounding step of a
                 floating point computation on at least one floating
                 point operand to preserve an inexact status. Inexact
                 status information generated from the rounding step may
                 be encoded within the result, instead of requiring a
                 separate floating point status register for the inexact
                 status information. In one embodiment, inexact status
                 information is preserved by determining whether the at
                 least one operand is inexact. Further, an intermediate
                 result of the floating point computation is analyzed to
                 determine whether it is inexact. Finally, the
                 intermediate result is rounded based on whether the at
                 least one operand is inexact and whether the
                 intermediate result is inexact to preserve an inexact
                 status of the at least one operand and the intermediate
                 result.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Steele:2006:SMP
author: Guy L. Steele Jr.
title: System and method for performing floating point operations involving extended exponents
pages: xviii + 296
day: 31
month: jan
monthnumber: 1
year: 2006
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/6993549/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 6993549
rawauthor: Guy L. {Steele Jr.}
rawtitle: System and method for performing floating point operations involving extended exponents
abstract:
An extended exponent floating point unit performs an extended exponent floating point operation on a plurality of operands to produce a product of the plurality of operands. The extended exponent floating point unit groups the plurality of operands into at least one group, determines a plurality of scale factors for the plurality of operands, respectively, and provides a running sum of the plurality of scale factors. The extended exponent floating point unit further scales the plurality of operands to obtain a plurality of scaled operands, multiplies the plurality of scaled operands to obtain a group product, and scales the group product to obtain a scaled group product. The scaled group product is adjusted based on the running sum. The plurality of operands are grouped such that when all the plurality of scaled operands in the at least one group are multiplied an overflow or underflow will not occur.

rawabstract:
An extended exponent floating point unit performs an extended exponent floating point operation on a plurality of operands to produce a product of the plurality of operands. The extended exponent floating point unit groups the plurality of operands into at least one group, determines a plurality of scale factors for the plurality of operands, respectively, and provides a running sum of the plurality of scale factors. The extended exponent floating point unit further scales the plurality of operands to obtain a plurality of scaled operands, multiplies the plurality of scaled operands to obtain a group product, and scales the group product to obtain a scaled group product. The scaled group product is adjusted based on the running sum. The plurality of operands are grouped such that when all the plurality of scaled operands in the at least one group are multiplied an overflow or underflow will not occur.

entry:
@Misc{Steele:2006:SMP,
  author =       "Guy L. {Steele Jr.}",
  title =        "System and method for performing floating point
                 operations involving extended exponents",
  howpublished = "US Patent 6993549",
  day =          "31",
  month =        jan,
  year =         "2006",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/6993549/fulltext.html",
  abstract =     "An extended exponent floating point unit performs an
                 extended exponent floating point operation on a
                 plurality of operands to produce a product of the
                 plurality of operands. The extended exponent floating
                 point unit groups the plurality of operands into at
                 least one group, determines a plurality of scale
                 factors for the plurality of operands, respectively,
                 and provides a running sum of the plurality of scale
                 factors. The extended exponent floating point unit
                 further scales the plurality of operands to obtain a
                 plurality of scaled operands, multiplies the plurality
                 of scaled operands to obtain a group product, and
                 scales the group product to obtain a scaled group
                 product. The scaled group product is adjusted based on
                 the running sum. The plurality of operands are grouped
                 such that when all the plurality of scaled operands in
                 the at least one group are multiplied an overflow or
                 underflow will not occur.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Steele:2006:TOC
author: Guy L. Steele Jr.
title: Total order comparator unit for comparing values of two floating point operands
pages: xviii + 296
day: 07
month: nov
monthnumber: 11
year: 2006
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/7133890/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7133890
rawauthor: Guy L. {Steele Jr.}
rawtitle: Total order comparator unit for comparing values of two floating point operands
abstract:
A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand, a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand, and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand. The result can condition the outcome of a floating point instruction. The floating point total order comparator circuit may recognize several predetermined operand formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero, exact, and inexact.

rawabstract:
A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand, a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand, and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand. The result can condition the outcome of a floating point instruction. The floating point total order comparator circuit may recognize several predetermined operand formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero, exact, and inexact.

entry:
@Misc{Steele:2006:TOC,
  author =       "Guy L. {Steele Jr.}",
  title =        "Total order comparator unit for comparing values of
                 two floating point operands",
  howpublished = "US Patent 7133890",
  day =          "07",
  month =        nov,
  year =         "2006",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7133890/fulltext.html",
  abstract =     "A floating point total order comparator circuit for
                 comparing a first floating point operand and a second
                 floating point operand includes a first analysis
                 circuit for determining a format of the first floating
                 point operand based upon floating point status
                 information encoded within the first floating point
                 operand, a second analysis circuit for determining a
                 format of the second floating point operand based upon
                 floating point status information encoded within the
                 second floating point operand, and a result generator
                 circuit coupled to the analysis circuits for producing
                 a result indicating a total order comparative
                 relationship between the first floating point operand
                 and the second floating point operand based on the
                 format of the first floating point operand and the
                 format of the second floating point operand. The result
                 can condition the outcome of a floating point
                 instruction. The floating point total order comparator
                 circuit may recognize several predetermined operand
                 formats, such as not-a-number (NaN), infinity,
                 normalized, denormalized, invalid operation, overflow,
                 underflow, division by zero, positive zero, negative
                 zero, exact, and inexact.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Strzebonski:2006:CAD
author: Adam W. Strzebonski
title: Cylindrical Algebraic Decomposition using validated numerics
journal: j-J-SYMBOLIC-COMP
volume: 41
number: 9
pages: 1021--1038
month: sep
monthnumber: 9
year: 2006
CODEN: JSYCEH
ISSN: 0747-7171 (print), 1095-855X (electronic) OR 07477171 (print), 1095855X (electronic)
ISSNL: 0747-7171 OR 07477171
bibdate: Wed Aug 25 20:13:18 MDT 2010
bibtimestamp: 2010.08.25 20:13:18 MDT
fjournal: Journal of Symbolic Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07477171/
rawauthor: Adam W. Strzebo{\'n}ski
rawtitle: {Cylindrical Algebraic Decomposition} using validated numerics
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jsymcomp.bib

entry:
@Article{Strzebonski:2006:CAD,
  author =       "Adam W. Strzebo{\'n}ski",
  title =        "{Cylindrical Algebraic Decomposition} using validated
                 numerics",
  journal =      j-J-SYMBOLIC-COMP,
  volume =       "41",
  number =       "9",
  pages =        "1021--1038",
  month =        sep,
  year =         "2006",
  CODEN =        "JSYCEH",
  ISSN =         "0747-7171 (print), 1095-855X (electronic)",
  ISSN-L =       "0747-7171",
  bibdate =      "Wed Aug 25 20:13:18 MDT 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsymcomp.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Symbolic Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07477171/",
}


bibtype: inproceedings
filename: fparith.bib
label: Strzodka:2006:PMP
author: R. Strzodka and D. Goddeke
crossref: Pocek:2006:FAI
pages: 259--270
year: 2006
bibdate: Sat Oct 9 13:03:16 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 13:03:16 ???
acknowledgement: ack-nhfb
rawauthor: R. Strzodka and D. Goddeke
title:
Pipelined mixed precision algorithms on FPGAs for fast and accurate PDE solvers from low precision components

rawtitle:
Pipelined mixed precision algorithms on {FPGAs} for fast and accurate {PDE} solvers from low precision components

entry:
@InProceedings{Strzodka:2006:PMP,
  author =       "R. Strzodka and D. Goddeke",
  title =        "Pipelined mixed precision algorithms on {FPGAs} for
                 fast and accurate {PDE} solvers from low precision
                 components",
  crossref =     "Pocek:2006:FAI",
  pages =        "259--270",
  year =         "2006",
  bibdate =      "Sat Oct 9 13:03:16 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Taylor:2006:IAI
author: Paul Taylor
title: Interval Analysis Without Intervals
crossref: Anonymous:2006:PCR
pages: ??--??
year: 2006
bibdate: Tue Jun 27 10:28:05 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.06.27 10:28:05 ???
acknowledgement: ack-nhfb
rawauthor: Paul Taylor
rawtitle: Interval Analysis Without Intervals
entry:
@InProceedings{Taylor:2006:IAI,
  author =       "Paul Taylor",
  title =        "Interval Analysis Without Intervals",
  crossref =     "Anonymous:2006:PCR",
  pages =        "??--??",
  year =         "2006",
  bibdate =      "Tue Jun 27 10:28:05 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Thakkar:2006:PDP
author: Anuja J. Thakkar and Abdel Ejnioui
title: Pipelining of double precision floating point division and square root operations
crossref: Menezes:2006:PAS
pages: 488--493
year: 2006
DOI: https://doi.org/10.1145/1185448.1185555
bibdate: Sat Oct 9 13:04:49 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 13:04:49 ???
acknowledgement: ack-nhfb
rawauthor: Anuja J. Thakkar and Abdel Ejnioui
rawtitle: Pipelining of double precision floating point division and square root operations
abstract:
Space applications rely increasingly on high data rate DSP algorithms. These algorithms use double precision floating point arithmetic operations. While most DSP applications can be compiled on DSP processors, high data rate DSP computations require novel implementation technologies to support their high throughputs. Only recently, gate densities in FPGAs have reached a level which makes them attractive platforms to implement compute-intensive DSP applications. In this context, this paper presents the sequential and pipelined designs of a double precision floating point divider and square root unit on FPGAs. Contrary to pipelined parallel implementations, the pipelining of these units is based on unrolling the iterations in low-radix digit recurrence algorithms. These units are mapped on generic FPGA reconfigurable fabric without taking advantage of any advanced architectural components available in high capacity FPGAs. The implementations of these designs show that their performances are comparable to, and sometimes higher than, the performances of non-iterative designs based of high radix numbers. The iterative divider and square root unit occupy less than 1% of an XC2V6000 FPGA chip while their pipelined counterparts can produce throughputs that reach the 100 MFLOPS mark by consuming a modest 8% of the chip area.

rawabstract:
Space applications rely increasingly on high data rate DSP algorithms. These algorithms use double precision floating point arithmetic operations. While most DSP applications can be compiled on DSP processors, high data rate DSP computations require novel implementation technologies to support their high throughputs. Only recently, gate densities in FPGAs have reached a level which makes them attractive platforms to implement compute-intensive DSP applications. In this context, this paper presents the sequential and pipelined designs of a double precision floating point divider and square root unit on FPGAs. Contrary to pipelined parallel implementations, the pipelining of these units is based on unrolling the iterations in low-radix digit recurrence algorithms. These units are mapped on generic FPGA reconfigurable fabric without taking advantage of any advanced architectural components available in high capacity FPGAs. The implementations of these designs show that their performances are comparable to, and sometimes higher than, the performances of non-iterative designs based of high radix numbers. The iterative divider and square root unit occupy less than 1\% of an XC2V6000 FPGA chip while their pipelined counterparts can produce throughputs that reach the 100 MFLOPS mark by consuming a modest 8\% of the chip area.

entry:
@InProceedings{Thakkar:2006:PDP,
  author =       "Anuja J. Thakkar and Abdel Ejnioui",
  title =        "Pipelining of double precision floating point division
                 and square root operations",
  crossref =     "Menezes:2006:PAS",
  pages =        "488--493",
  year =         "2006",
  DOI =          "https://doi.org/10.1145/1185448.1185555",
  bibdate =      "Sat Oct 9 13:04:49 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Space applications rely increasingly on high data rate
                 DSP algorithms. These algorithms use double precision
                 floating point arithmetic operations. While most DSP
                 applications can be compiled on DSP processors, high
                 data rate DSP computations require novel implementation
                 technologies to support their high throughputs. Only
                 recently, gate densities in FPGAs have reached a level
                 which makes them attractive platforms to implement
                 compute-intensive DSP applications. In this context,
                 this paper presents the sequential and pipelined
                 designs of a double precision floating point divider
                 and square root unit on FPGAs. Contrary to pipelined
                 parallel implementations, the pipelining of these units
                 is based on unrolling the iterations in low-radix digit
                 recurrence algorithms. These units are mapped on
                 generic FPGA reconfigurable fabric without taking
                 advantage of any advanced architectural components
                 available in high capacity FPGAs. The implementations
                 of these designs show that their performances are
                 comparable to, and sometimes higher than, the
                 performances of non-iterative designs based of high
                 radix numbers. The iterative divider and square root
                 unit occupy less than 1\% of an XC2V6000 FPGA chip
                 while their pipelined counterparts can produce
                 throughputs that reach the 100 MFLOPS mark by consuming
                 a modest 8\% of the chip area.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Thapliyal:2006:CIF
author: Himanshu Thapliyal and Hamid R. Arabnia and A. P. Vinod
journal: arXiv.org
pages: ??--??
day: 14
month: oct
monthnumber: 10
year: 2006
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/cs/0610090
subject: Hardware Architecture (cs.AR)
acknowledgement: ack-nhfb
rawauthor: Himanshu Thapliyal and Hamid R. Arabnia and A. P. Vinod
title:
Combined Integer and Floating Point Multiplication Architecture (CIFM) for FPGAs and Its Reversible Logic Implementation

abstract:
In this paper, the authors propose the idea of a combined integer and floating point multiplier(CIFM) for FPGAs. The authors propose the replacement of existing 18x18 dedicated multipliers in FPGAs with dedicated 24x24 multipliers designed with small 4x4 bit multipliers. It is also proposed that for every dedicated 24x24 bit multiplier block designed with 4x4 bit multipliers, four redundant 4x4 multiplier should be provided to enforce the feature of self repairability (to recover from the faults). In the proposed CIFM reconfigurability at run time is also provided resulting in low power. The major source of motivation for providing the dedicated 24x24 bit multiplier stems from the fact that single precision floating point multiplier requires 24x24 bit integer multiplier for mantissa multiplication. A reconfigurable, self-repairable 24x24 bit multiplier (implemented with 4x4 bit multiply modules) will ideally suit this purpose, making FPGAs more suitable for integer as well floating point operations. A dedicated 4x4 bit multiplier is also proposed in this paper. Moreover, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the proposed CIFM. The reversible CIFM designed and proposed here will form the basis of the completely reversible FPGAs.

rawabstract:
In this paper, the authors propose the idea of a combined integer and floating point multiplier(CIFM) for FPGAs. The authors propose the replacement of existing 18x18 dedicated multipliers in FPGAs with dedicated 24x24 multipliers designed with small 4x4 bit multipliers. It is also proposed that for every dedicated 24x24 bit multiplier block designed with 4x4 bit multipliers, four redundant 4x4 multiplier should be provided to enforce the feature of self repairability (to recover from the faults). In the proposed CIFM reconfigurability at run time is also provided resulting in low power. The major source of motivation for providing the dedicated 24x24 bit multiplier stems from the fact that single precision floating point multiplier requires 24x24 bit integer multiplier for mantissa multiplication. A reconfigurable, self-repairable 24x24 bit multiplier (implemented with 4x4 bit multiply modules) will ideally suit this purpose, making FPGAs more suitable for integer as well floating point operations. A dedicated 4x4 bit multiplier is also proposed in this paper. Moreover, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the proposed CIFM. The reversible CIFM designed and proposed here will form the basis of the completely reversible FPGAs.

rawtitle:
Combined Integer and Floating Point Multiplication Architecture ({CIFM}) for {FPGAs} and Its Reversible Logic Implementation

entry:
@Article{Thapliyal:2006:CIF,
  author =       "Himanshu Thapliyal and Hamid R. Arabnia and A. P.
                 Vinod",
  title =        "Combined Integer and Floating Point Multiplication
                 Architecture ({CIFM}) for {FPGAs} and Its Reversible
                 Logic Implementation",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "14",
  month =        oct,
  year =         "2006",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/cs/0610090",
  abstract =     "In this paper, the authors propose the idea of a
                 combined integer and floating point multiplier(CIFM)
                 for FPGAs. The authors propose the replacement of
                 existing 18x18 dedicated multipliers in FPGAs with
                 dedicated 24x24 multipliers designed with small 4x4 bit
                 multipliers. It is also proposed that for every
                 dedicated 24x24 bit multiplier block designed with 4x4
                 bit multipliers, four redundant 4x4 multiplier should
                 be provided to enforce the feature of self
                 repairability (to recover from the faults). In the
                 proposed CIFM reconfigurability at run time is also
                 provided resulting in low power. The major source of
                 motivation for providing the dedicated 24x24 bit
                 multiplier stems from the fact that single precision
                 floating point multiplier requires 24x24 bit integer
                 multiplier for mantissa multiplication. A
                 reconfigurable, self-repairable 24x24 bit multiplier
                 (implemented with 4x4 bit multiply modules) will
                 ideally suit this purpose, making FPGAs more suitable
                 for integer as well floating point operations. A
                 dedicated 4x4 bit multiplier is also proposed in this
                 paper. Moreover, in the recent years, reversible logic
                 has emerged as a promising technology having its
                 applications in low power CMOS, quantum computing,
                 nanotechnology, and optical computing. It is not
                 possible to realize quantum computing without
                 reversible logic. Thus, this paper also paper provides
                 the reversible logic implementation of the proposed
                 CIFM. The reversible CIFM designed and proposed here
                 will form the basis of the completely reversible
                 FPGAs.",
  acknowledgement = ack-nhfb,
  subject =      "Hardware Architecture (cs.AR)",
}


bibtype: inproceedings
filename: fparith.bib
label: Thapliyal:2006:DNR
author: Himanshu Thapliyal and Sumedha K. Gupta
title: Design of Novel Reversible Carry Look-Ahead BCD Subtractor
crossref: Mohanty:2006:IIC
pages: 253--258
year: 2006
DOI: https://doi.org/10.1109/ICIT.2006.44
bibdate: Thu Aug 07 19:09:50 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 19:09:50 ???
acknowledgement: ack-nhfb
rawauthor: Himanshu Thapliyal and Sumedha K. Gupta
rawtitle: Design of Novel Reversible Carry Look-Ahead {BCD} Subtractor
abstract:
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard. A major enhancement to the standard is the addition of decimal format, thus the design of BCD arithmetic units is likely to get significant attention. Firstly, this paper introduces a novel carry look-ahead BCD adder and then builds a novel carry look-ahead BCD subtractor based on it. Secondly, it introduces the reversible logic implementation of the proposed carry look-ahead BCD subtractor. We have tried to design the reversible logic implementation of the BCD Subtractor optimal in terms of number of reversible gates used and garbage outputs produced. Thus, the proposed work will be of significant value as the technologies mature.

rawabstract:
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard. A major enhancement to the standard is the addition of decimal format, thus the design of BCD arithmetic units is likely to get significant attention. Firstly, this paper introduces a novel carry look-ahead BCD adder and then builds a novel carry look-ahead BCD subtractor based on it. Secondly, it introduces the reversible logic implementation of the proposed carry look-ahead BCD subtractor. We have tried to design the reversible logic implementation of the BCD Subtractor optimal in terms of number of reversible gates used and garbage outputs produced. Thus, the proposed work will be of significant value as the technologies mature.

entry:
@InProceedings{Thapliyal:2006:DNR,
  author =       "Himanshu Thapliyal and Sumedha K. Gupta",
  title =        "Design of Novel Reversible Carry Look-Ahead {BCD}
                 Subtractor",
  crossref =     "Mohanty:2006:IIC",
  pages =        "253--258",
  year =         "2006",
  DOI =          "https://doi.org/10.1109/ICIT.2006.44",
  bibdate =      "Thu Aug 07 19:09:50 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "IEEE 754r is the ongoing revision to the IEEE 754
                 floating point standard. A major enhancement to the
                 standard is the addition of decimal format, thus the
                 design of BCD arithmetic units is likely to get
                 significant attention. Firstly, this paper introduces a
                 novel carry look-ahead BCD adder and then builds a
                 novel carry look-ahead BCD subtractor based on it.
                 Secondly, it introduces the reversible logic
                 implementation of the proposed carry look-ahead BCD
                 subtractor. We have tried to design the reversible
                 logic implementation of the BCD Subtractor optimal in
                 terms of number of reversible gates used and garbage
                 outputs produced. Thus, the proposed work will be of
                 significant value as the technologies mature.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Thapliyal:2006:NBA
author: H. Thapliyal and S. Kotiyal and M. B. Srinivas
title: Novel BCD adders and their reversible logic implementation for IEEE 754R format
crossref: IEEE:2006:ICV
pages: 253--258
year: 2006
DOI: https://doi.org/10.1109/VLSID.2006.122
bibdate: Mon Mar 19 10:19:57 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.19 10:19:57 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: H. Thapliyal and S. Kotiyal and M. B. Srinivas
rawtitle: Novel {BCD} adders and their reversible logic implementation for {IEEE 754R} format
abstract:
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel BCD adders called carry skip and carry look-ahead BCD adders respectively. Furthermore, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the conventional BCD adder as the well as the proposed carry skip BCD adder using a recently proposed TSG gate. Furthermore, a new reversible gate called TS-3 is also being proposed and it has been shown that the proposed reversible logic implementation of the BCD adders is much better compared to recently proposed one, in terms of number of reversible gates used and garbage outputs produced. The reversible BCD circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU.

rawabstract:
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel BCD adders called carry skip and carry look-ahead BCD adders respectively. Furthermore, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the conventional BCD adder as the well as the proposed carry skip BCD adder using a recently proposed TSG gate. Furthermore, a new reversible gate called TS-3 is also being proposed and it has been shown that the proposed reversible logic implementation of the BCD adders is much better compared to recently proposed one, in terms of number of reversible gates used and garbage outputs produced. The reversible BCD circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU.

entry:
@InProceedings{Thapliyal:2006:NBA,
  author =       "H. Thapliyal and S. Kotiyal and M. B. Srinivas",
  title =        "Novel {BCD} adders and their reversible logic
                 implementation for {IEEE 754R} format",
  crossref =     "IEEE:2006:ICV",
  year =         "2006",
  DOI =          "https://doi.org/10.1109/VLSID.2006.122",
  bibdate =      "Mon Mar 19 10:19:57 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "IEEE 754r is the ongoing revision to the IEEE 754
                 floating point standard and a major enhancement to the
                 standard is the addition of decimal format. This paper
                 proposes two novel BCD adders called carry skip and
                 carry look-ahead BCD adders respectively. Furthermore,
                 in the recent years, reversible logic has emerged as a
                 promising technology having its applications in low
                 power CMOS, quantum computing, nanotechnology, and
                 optical computing. It is not possible to realize
                 quantum computing without reversible logic. Thus, this
                 paper also paper provides the reversible logic
                 implementation of the conventional BCD adder as the
                 well as the proposed carry skip BCD adder using a
                 recently proposed TSG gate. Furthermore, a new
                 reversible gate called TS-3 is also being proposed and
                 it has been shown that the proposed reversible logic
                 implementation of the BCD adders is much better
                 compared to recently proposed one, in terms of number
                 of reversible gates used and garbage outputs produced.
                 The reversible BCD circuits designed and proposed here
                 form the basis of the decimal ALU of a primitive
                 quantum CPU.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Toivonen:2006:VFF
author: T. Toivonen and J. Heikkila
title: Video filtering with Fermat number theoretic transforms using residue number system
journal: j-IEEE-TRANS-CIRCUITS-SYST-VIDEO-TECH
volume: 16
number: 1
pages: 92--101
month: jan
monthnumber: 1
year: 2006
CODEN: ITCTEM
DOI: https://doi.org/10.1109/TCSVT.2005.858612
ISSN: 1051-8215 (print), 1558-2205 (electronic) OR 10518215 (print), 15582205 (electronic)
ISSNL: 1051-8215 OR 10518215
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=33196
fjournal: IEEE Transactions on Circuits and Systems for Video Technology
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=76
rawauthor: T. Toivonen and J. Heikkila
rawtitle: Video filtering with {Fermat} number theoretic transforms using residue number system
entry:
@Article{Toivonen:2006:VFF,
  author =       "T. Toivonen and J. Heikkila",
  title =        "Video filtering with {Fermat} number theoretic
                 transforms using residue number system",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-VIDEO-TECH,
  volume =       "16",
  number =       "1",
  pages =        "92--101",
  month =        jan,
  year =         "2006",
  CODEN =        "ITCTEM",
  DOI =          "https://doi.org/10.1109/TCSVT.2005.858612",
  ISSN =         "1051-8215 (print), 1558-2205 (electronic)",
  ISSN-L =       "1051-8215",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=33196",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems for Video
                 Technology",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=76",
  keywords =     "residue arithmetic; residue number system",
  summary =      "We investigate image and video convolutions based on
                 Fermat number transform (FNT) modulo q=2/sup M/+1 where
                 M is an integer power of two. These transforms are
                 found to be ideal for image convolutions, except that
                 the choices for the word length, \ldots{}",
}


bibtype: book
filename: fparith.bib
label: Trott:2006:MGN
author: Michael Trott
title: The Mathematica guidebook for numerics
publisher: pub-SV
address: pub-SV:adr
pages: xxxvi + 1208
year: 2006
ISBN: 0-387-95011-7 OR 0387950117
ISBN13: 978-0-387-95011-2 OR 9780387950112
LCCN: QA76.95 .T773 2006
MRclass: 65-00
MRnumber: MR2174594 (2006m:65001)
bibdate: Thu Nov 8 19:02:51 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:02:51 ???
note: With 1 DVD (Windows, Macintosh, Mac, UNIX)
acknowledgement: ack-nhfb
rawauthor: Michael Trott
rawnote: With 1 DVD (Windows, Macintosh, Mac, UNIX)
rawtitle: The {Mathematica} guidebook for numerics
entry:
@Book{Trott:2006:MGN,
  author =       "Michael Trott",
  title =        "The {Mathematica} guidebook for numerics",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "xxxvi + 1208",
  year =         "2006",
  ISBN =         "0-387-95011-7",
  ISBN-13 =      "978-0-387-95011-2",
  LCCN =         "QA76.95 .T773 2006",
  MRclass =      "65-00",
  MRnumber =     "MR2174594 (2006m:65001)",
  bibdate =      "Thu Nov 8 19:02:51 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "With 1 DVD (Windows, Macintosh, Mac, UNIX)",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: VanMeter:2006:DAQ
author: Rodney Van Meter and Kae Nemoto and W. J. Munro and Kohei M. Itoh
title: Distributed Arithmetic on a Quantum Multicomputer
journal: j-COMP-ARCH-NEWS
volume: 34
number: 2
pages: 354--365
year: 2006
CODEN: CANED2
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Mon Aug 21 15:00:05 MDT 2006
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.08.21 15:00:05 MDT
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J89
rawauthor: Rodney {Van Meter} and Kae Nemoto and W. J. Munro and Kohei M. Itoh
rawtitle: Distributed Arithmetic on a Quantum Multicomputer
entry:
@Article{VanMeter:2006:DAQ,
  author =       "Rodney {Van Meter} and Kae Nemoto and W. J. Munro and
                 Kohei M. Itoh",
  title =        "Distributed Arithmetic on a Quantum Multicomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "354--365",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
}


bibtype: inproceedings
filename: fparith.bib
label: Vazquez:2006:CSD
author: Alvaro Vazquez and Elisardo Antelo
title: Conditional Speculative Decimal Addition
crossref: Anonymous:2006:PCR
pages: ??--??
year: 2006
bibdate: Tue Jun 27 10:28:05 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.06.27 10:28:05 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Alvaro Vazquez and Elisardo Antelo
rawtitle: Conditional Speculative Decimal Addition
entry:
@InProceedings{Vazquez:2006:CSD,
  author =       "Alvaro Vazquez and Elisardo Antelo",
  title =        "Conditional Speculative Decimal Addition",
  crossref =     "Anonymous:2006:PCR",
  pages =        "??--??",
  year =         "2006",
  bibdate =      "Tue Jun 27 10:28:05 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Villalba:2006:DRM
author: J. Villalba and T. Lang and M. A. Gonzalez
title: Double-residue modular range reduction for floating-point hardware implementations
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 3
pages: 254--267
month: mar
monthnumber: 3
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.38
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:53 MDT 2011
bibtimestamp: 2011.07.04 15:35:53 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1583556
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. Villalba and T. Lang and M. A. Gonzalez
rawtitle: Double-residue modular range reduction for floating-point hardware implementations
entry:
@Article{Villalba:2006:DRM,
  author =       "J. Villalba and T. Lang and M. A. Gonzalez",
  title =        "Double-residue modular range reduction for
                 floating-point hardware implementations",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "3",
  pages =        "254--267",
  month =        mar,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.38",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:53 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1583556",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:2006:ACV
author: X. Wang and S. Braganza and M. Leeser
title: Advanced components in the variable precision floating-point library
crossref: Pocek:2006:FAI
pages: 249--258
year: 2006
DOI: https://doi.org/10.1109/FCCM.2006.21
bibdate: Sat Oct 9 13:07:28 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 13:07:28 ???
acknowledgement: ack-nhfb
rawauthor: X. Wang and S. Braganza and M. Leeser
rawtitle: Advanced components in the variable precision floating-point library
abstract:
Optimal reconfigurable hardware implementations may require the use of arbitrary floating-point formats that do not necessarily conform to IEEE specified sizes. The authors have previously presented a variable precision floating-point library for use with reconfigurable hardware. The authors recently added three advanced components: floating-point division, floating-point square root and floating-point accumulation to our library. These advanced components use algorithms that are well suited to FPGA implementations and exhibit a good tradeoff between area, latency and throughput. The floating-point format of our library is both general and flexible. All IEEE formats, including 64-bit double-precision format, are a subset of our format. All previously published floating-point formats for reconfigurable hardware are a subset of our format as well. The generic floating-point format supported by all of our library components makes it easy and convenient to create a pipelined, custom data path with optimal bitwidth for each operation. Our library can be used to achieve more parallelism and less power dissipation than adhering to a standard format. To further increase parallelism and reduce power dissipation, our library also supports hybrid fixed and floating point operations in the same design. The division and square root designs are based on table lookup and Taylor series expansion, and make use of memories and multipliers embedded on the FPGA chip. The iterative accumulator utilizes the library addition module as well as buffering and control logic to achieve performance similar to that of the addition by itself. They are all fully pipelined designs with clock speed comparable to that of other library components to aid the designer in implementing fast, complex, pipelined designs.

rawabstract:
Optimal reconfigurable hardware implementations may require the use of arbitrary floating-point formats that do not necessarily conform to IEEE specified sizes. The authors have previously presented a variable precision floating-point library for use with reconfigurable hardware. The authors recently added three advanced components: floating-point division, floating-point square root and floating-point accumulation to our library. These advanced components use algorithms that are well suited to FPGA implementations and exhibit a good tradeoff between area, latency and throughput. The floating-point format of our library is both general and flexible. All IEEE formats, including 64-bit double-precision format, are a subset of our format. All previously published floating-point formats for reconfigurable hardware are a subset of our format as well. The generic floating-point format supported by all of our library components makes it easy and convenient to create a pipelined, custom data path with optimal bitwidth for each operation. Our library can be used to achieve more parallelism and less power dissipation than adhering to a standard format. To further increase parallelism and reduce power dissipation, our library also supports hybrid fixed and floating point operations in the same design. The division and square root designs are based on table lookup and Taylor series expansion, and make use of memories and multipliers embedded on the FPGA chip. The iterative accumulator utilizes the library addition module as well as buffering and control logic to achieve performance similar to that of the addition by itself. They are all fully pipelined designs with clock speed comparable to that of other library components to aid the designer in implementing fast, complex, pipelined designs.

entry:
@InProceedings{Wang:2006:ACV,
  author =       "X. Wang and S. Braganza and M. Leeser",
  title =        "Advanced components in the variable precision
                 floating-point library",
  crossref =     "Pocek:2006:FAI",
  pages =        "249--258",
  year =         "2006",
  DOI =          "https://doi.org/10.1109/FCCM.2006.21",
  bibdate =      "Sat Oct 9 13:07:28 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Optimal reconfigurable hardware implementations may
                 require the use of arbitrary floating-point formats
                 that do not necessarily conform to IEEE specified
                 sizes. The authors have previously presented a variable
                 precision floating-point library for use with
                 reconfigurable hardware. The authors recently added
                 three advanced components: floating-point division,
                 floating-point square root and floating-point
                 accumulation to our library. These advanced components
                 use algorithms that are well suited to FPGA
                 implementations and exhibit a good tradeoff between
                 area, latency and throughput. The floating-point format
                 of our library is both general and flexible. All IEEE
                 formats, including 64-bit double-precision format, are
                 a subset of our format. All previously published
                 floating-point formats for reconfigurable hardware are
                 a subset of our format as well. The generic
                 floating-point format supported by all of our library
                 components makes it easy and convenient to create a
                 pipelined, custom data path with optimal bitwidth for
                 each operation. Our library can be used to achieve more
                 parallelism and less power dissipation than adhering to
                 a standard format. To further increase parallelism and
                 reduce power dissipation, our library also supports
                 hybrid fixed and floating point operations in the same
                 design. The division and square root designs are based
                 on table lookup and Taylor series expansion, and make
                 use of memories and multipliers embedded on the FPGA
                 chip. The iterative accumulator utilizes the library
                 addition module as well as buffering and control logic
                 to achieve performance similar to that of the addition
                 by itself. They are all fully pipelined designs with
                 clock speed comparable to that of other library
                 components to aid the designer in implementing fast,
                 complex, pipelined designs.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Wang:2006:PAN
author: Chengpu Wang
title: Precision Arithmetic: A New Floating-Point Arithmetic
journal: arXiv.org
pages: ??--??
day: 25
month: jun
monthnumber: 6
year: 2006
MRclass: 65Y04, 65T50
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/cs/0606103
remark: This document has been updated 21 times from 25 Jun 2006 to 3 Apr 2014.
subject: Discrete Mathematics (cs.DM); Data Structures and Algorithms (cs.DS); Numerical Analysis (cs.NA)
acknowledgement: ack-nhfb
rawauthor: Chengpu Wang
rawtitle: Precision Arithmetic: A New Floating-Point Arithmetic
abstract:
A new deterministic floating-point arithmetic called precision arithmetic is developed to track precision for arithmetic calculations. It uses a novel rounding scheme to avoid excessive rounding error propagation of conventional floating-point arithmetic. Unlike interval arithmetic, its uncertainty tracking is based on statistics and the central limit theorem, with a much tighter bounding range. Its stable rounding error distribution is approximated by a truncated normal distribution. Generic standards and systematic methods for validating uncertainty-bearing arithmetics are discussed. The precision arithmetic is found to be better than interval arithmetic in both uncertainty-tracking and uncertainty-bounding for normal usages. The precision arithmetic is available publicly at url http://precisionarithm.sourceforge.net/

rawabstract:
A new deterministic floating-point arithmetic called precision arithmetic is developed to track precision for arithmetic calculations. It uses a novel rounding scheme to avoid excessive rounding error propagation of conventional floating-point arithmetic. Unlike interval arithmetic, its uncertainty tracking is based on statistics and the central limit theorem, with a much tighter bounding range. Its stable rounding error distribution is approximated by a truncated normal distribution. Generic standards and systematic methods for validating uncertainty-bearing arithmetics are discussed. The precision arithmetic is found to be better than interval arithmetic in both uncertainty-tracking and uncertainty-bounding for normal usages. The precision arithmetic is available publicly at \url{http://precisionarithm.sourceforge.net/}

entry:
@Article{Wang:2006:PAN,
  author =       "Chengpu Wang",
  title =        "Precision Arithmetic: A New Floating-Point
                 Arithmetic",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "25",
  month =        jun,
  year =         "2006",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  MRclass =      "65Y04, 65T50",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/cs/0606103",
  abstract =     "A new deterministic floating-point arithmetic called
                 precision arithmetic is developed to track precision
                 for arithmetic calculations. It uses a novel rounding
                 scheme to avoid excessive rounding error propagation of
                 conventional floating-point arithmetic. Unlike interval
                 arithmetic, its uncertainty tracking is based on
                 statistics and the central limit theorem, with a much
                 tighter bounding range. Its stable rounding error
                 distribution is approximated by a truncated normal
                 distribution. Generic standards and systematic methods
                 for validating uncertainty-bearing arithmetics are
                 discussed. The precision arithmetic is found to be
                 better than interval arithmetic in both
                 uncertainty-tracking and uncertainty-bounding for
                 normal usages. The precision arithmetic is available
                 publicly at
                 \url{http://precisionarithm.sourceforge.net/}",
  acknowledgement = ack-nhfb,
  remark =       "This document has been updated 21 times from 25 Jun
                 2006 to 3 Apr 2014.",
  subject =      "Discrete Mathematics (cs.DM); Data Structures and
                 Algorithms (cs.DS); Numerical Analysis (cs.NA)",
}


bibtype: article
filename: fparith.bib
label: Wires:2006:RRS
author: Kent E. Wires and Michael J. Schulte
title: Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication
journal: j-J-VLSI-SIGNAL-PROC
volume: 42
number: 3
pages: 257--272
month: mar
monthnumber: 3
year: 2006
CODEN: JVSPED
DOI: https://doi.org/10.1007/s11265-006-4186-0
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Mon Mar 05 08:26:23 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.05 08:26:23 ???
URL: http://springerlink.metapress.com/content/t6027p6713727606/fulltext.pdf
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
rawauthor: Kent E. Wires and Michael J. Schulte
rawtitle: Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication
abstract:
Reciprocals and reciprocal square roots are used in several digital signal processing, multimedia, and scientific computing applications. This paper presents high-speed methods for computing reciprocals and reciprocal square roots. These methods use a table lookup, operand modification, and multiplication to obtain an initial approximation. This is followed by a modified Newton--Raphson iteration, which improves the accuracy of the initial approximation. The initial approximation and Newton--Raphson iteration employ specialized hardware to reduce the delay, area, and power dissipation. The application of these methods is illustrated through the design of reciprocal and reciprocal square root units for operands in the IEEE single precision format. These designs are pipelined to produce a new result every clock cycle.

keywords:
computer arithmetic; function approximation; Newton--Raphson iteration; reciprocal; reciprocal square root; table lookup

rawabstract:
Reciprocals and reciprocal square roots are used in several digital signal processing, multimedia, and scientific computing applications. This paper presents high-speed methods for computing reciprocals and reciprocal square roots. These methods use a table lookup, operand modification, and multiplication to obtain an initial approximation. This is followed by a modified Newton--Raphson iteration, which improves the accuracy of the initial approximation. The initial approximation and Newton--Raphson iteration employ specialized hardware to reduce the delay, area, and power dissipation. The application of these methods is illustrated through the design of reciprocal and reciprocal square root units for operands in the IEEE single precision format. These designs are pipelined to produce a new result every clock cycle.

entry:
@Article{Wires:2006:RRS,
  author =       "Kent E. Wires and Michael J. Schulte",
  title =        "Reciprocal and Reciprocal Square Root Units with
                 Operand Modification and Multiplication",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "42",
  number =       "3",
  pages =        "257--272",
  month =        mar,
  year =         "2006",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1007/s11265-006-4186-0",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Mon Mar 05 08:26:23 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://springerlink.metapress.com/content/t6027p6713727606/fulltext.pdf",
  abstract =     "Reciprocals and reciprocal square roots are used in
                 several digital signal processing, multimedia, and
                 scientific computing applications. This paper presents
                 high-speed methods for computing reciprocals and
                 reciprocal square roots. These methods use a table
                 lookup, operand modification, and multiplication to
                 obtain an initial approximation. This is followed by a
                 modified Newton--Raphson iteration, which improves the
                 accuracy of the initial approximation. The initial
                 approximation and Newton--Raphson iteration employ
                 specialized hardware to reduce the delay, area, and
                 power dissipation. The application of these methods is
                 illustrated through the design of reciprocal and
                 reciprocal square root units for operands in the IEEE
                 single precision format. These designs are pipelined to
                 produce a new result every clock cycle.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of VLSI Signal Processing",
  keywords =     "computer arithmetic; function approximation;
                 Newton--Raphson iteration; reciprocal; reciprocal
                 square root; table lookup",
}


bibtype: article
filename: fparith.bib
label: Wong:2006:FES
author: K. W. Wong and Edward C. W. Lee and L. M. Cheng and Xiaofeng Liao
title: Fast elliptic scalar multiplication using new double-base chain and point halving
journal: j-APPL-MATH-COMP
volume: 183
number: 2
pages: 1000--1007
day: 15
month: dec
monthnumber: 12
year: 2006
CODEN: AMHCBQ
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Sat Jul 12 09:03:00 MDT 2008
bibtimestamp: 2008.07.12 09:03:00 MDT
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: K. W. Wong and Edward C. W. Lee and L. M. Cheng and Xiaofeng Liao
rawtitle: Fast elliptic scalar multiplication using new double-base chain and point halving
entry:
@Article{Wong:2006:FES,
  author =       "K. W. Wong and Edward C. W. Lee and L. M. Cheng and
                 Xiaofeng Liao",
  title =        "Fast elliptic scalar multiplication using new
                 double-base chain and point halving",
  journal =      j-APPL-MATH-COMP,
  volume =       "183",
  number =       "2",
  pages =        "1000--1007",
  day =          "15",
  month =        dec,
  year =         "2006",
  CODEN =        "AMHCBQ",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Sat Jul 12 09:03:00 MDT 2008",
  bibsource =    "http://www.sciencedirect.com/science/journal/00963003;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
}


bibtype: article
filename: fparith.bib
label: Xenoulis:2006:TAS
author: G. Xenoulis and M. Psarakis and D. Gizopoulos and A. Paschalis
title: Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units
journal: j-IEEE-TRANS-COMPUT
volume: 55
number: 11
pages: 1449--1457
month: nov
monthnumber: 11
year: 2006
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2006.187
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:35:57 MDT 2011
bibtimestamp: 2011.07.04 15:35:57 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1705453
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: G. Xenoulis and M. Psarakis and D. Gizopoulos and A. Paschalis
rawtitle: Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units
entry:
@Article{Xenoulis:2006:TAS,
  author =       "G. Xenoulis and M. Psarakis and D. Gizopoulos and A.
                 Paschalis",
  title =        "Testability Analysis and Scalable Test Generation for
                 High-Speed Floating-Point Units",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "55",
  number =       "11",
  pages =        "1449--1457",
  month =        nov,
  year =         "2006",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2006.187",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:35:57 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1705453",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Xia:2006:RSI
author: Bican Xia and Ting Zhang
title: Real solution isolation using interval arithmetic
journal: j-COMPUT-MATH-APPL
volume: 52
number: 6--7
pages: 853--860
month: sep
monthnumber: 9
year: 2006
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 21:49:55 MST 2017
bibtimestamp: 2017.03.01 21:49:55 MST
URL: http://www.sciencedirect.com/science/article/pii/S0898122106002896
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: Bican Xia and Ting Zhang
rawtitle: Real solution isolation using interval arithmetic
entry:
@Article{Xia:2006:RSI,
  author =       "Bican Xia and Ting Zhang",
  title =        "Real solution isolation using interval arithmetic",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "52",
  number =       "6--7",
  pages =        "853--860",
  month =        sep # "\slash " # oct,
  year =         "2006",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 21:49:55 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0898122106002896",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: manual
filename: fparith.bib
label: XILINX:2006:XLF
author: XILINX
title: XILINX LogiCORE floating-point operator v3.0 product specification
organization: Xilinx, Inc.
pages: 853--860
day: 28
month: sep
monthnumber: 9
year: 2006
bibdate: Sat Oct 9 13:09:37 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 13:09:37 ???
URL: http://www.xilinx.com/bvdocs/ipcenter/data_sheet/floating_point_ds335.pdf
acknowledgement: ack-nhfb
rawauthor: {XILINX}
rawtitle: {XILINX LogiCORE} floating-point operator v3.0 product specification
entry:
@Manual{XILINX:2006:XLF,
  author =       "{XILINX}",
  title =        "{XILINX LogiCORE} floating-point operator v3.0 product
                 specification",
  organization = "Xilinx, Inc.",
  day =          "28",
  month =        sep,
  year =         "2006",
  bibdate =      "Sat Oct 9 13:09:37 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.xilinx.com/bvdocs/ipcenter/data_sheet/floating_point_ds335.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: You:2006:DDA
author: Younggap You and Yong Dae Kim and Jong Hwa Choi
title: Dynamic Decimal Adder Circuit Design by using the Carry Lookahead
crossref: IEEE:2006:PIW
pages: 242--244
year: 2006
bibdate: Mon Mar 19 11:11:29 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.19 11:11:29 ???
URL: http://ieeexplore.ieee.org/iel5/10974/34591/01649627.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Younggap You and Yong Dae Kim and Jong Hwa Choi
rawtitle: Dynamic Decimal Adder Circuit Design by using the Carry Lookahead
abstract:
This paper presents a carry lookahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the proposed dynamic decimal adder is analyzed demonstrating its speed improvement. Timing simulation on the proposed decimal addition circuit employing 0.25 $ mu $ m CMOS technology yields the worst case delay of 622ns.

rawabstract:
This paper presents a carry lookahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the proposed dynamic decimal adder is analyzed demonstrating its speed improvement. Timing simulation on the proposed decimal addition circuit employing 0.25 $ \mu $ m CMOS technology yields the worst case delay of 622ns.

entry:
@InProceedings{You:2006:DDA,
  author =       "Younggap You and Yong Dae Kim and Jong Hwa Choi",
  title =        "Dynamic Decimal Adder Circuit Design by using the
                 Carry Lookahead",
  crossref =     "IEEE:2006:PIW",
  pages =        "242--244",
  year =         "2006",
  bibdate =      "Mon Mar 19 11:11:29 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/iel5/10974/34591/01649627.pdf",
  abstract =     "This paper presents a carry lookahead (CLA) circuitry
                 design based on dynamic circuit aiming at delay
                 reduction in addition of BCD coded decimal numbers. The
                 performance of the proposed dynamic decimal adder is
                 analyzed demonstrating its speed improvement. Timing
                 simulation on the proposed decimal addition circuit
                 employing 0.25 $ \mu $ m CMOS technology yields the
                 worst case delay of 622ns.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Zhu:2006:FGA
author: Yong-Kang Zhu and Wayne Hayes
title: Fast, guaranteed-accurate sums of many floating-point numbers
crossref: Anonymous:2006:PCR
pages: ??--??
year: 2006
bibdate: Tue Jun 27 10:28:05 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.06.27 10:28:05 ???
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
rawauthor: Yong-Kang Zhu and Wayne Hayes
rawtitle: Fast, guaranteed-accurate sums of many floating-point numbers
entry:
@InProceedings{Zhu:2006:FGA,
  author =       "Yong-Kang Zhu and Wayne Hayes",
  title =        "Fast, guaranteed-accurate sums of many floating-point
                 numbers",
  crossref =     "Anonymous:2006:PCR",
  pages =        "??--??",
  year =         "2006",
  bibdate =      "Tue Jun 27 10:28:05 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation",
}


bibtype: techreport
filename: fparith.bib
label: Zimmermann:2006:AFD
author: Paul Zimmermann
title: Asymptotically Fast Division for GMP
type: Technical report
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
pages: ??--??
day: 31
month: aug
monthnumber: 8
year: 2006
bibdate: Sun Sep 10 07:18:34 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.10 07:18:34 ???
URL: http://www.loria.fr/~zimmerma/papers/invert.pdf
acknowledgement: ack-nhfb
rawauthor: Paul Zimmermann
rawtitle: Asymptotically Fast Division for {GMP}
abstract:
Until version 4.2.1, GNU MP (GMP for short) division has complexity O(M(n) log n), which is not asymptotically optimal. We propose here some division algorithms that achieve O(M(n)) with small constants.

rawabstract:
Until version 4.2.1, GNU MP (GMP for short) division has complexity O(M(n) log n), which is not asymptotically optimal. We propose here some division algorithms that achieve O(M(n)) with small constants.

entry:
@TechReport{Zimmermann:2006:AFD,
  author =       "Paul Zimmermann",
  title =        "Asymptotically Fast Division for {GMP}",
  type =         "Technical report",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  day =          "31",
  month =        aug,
  year =         "2006",
  bibdate =      "Sun Sep 10 07:18:34 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.loria.fr/~zimmerma/papers/invert.pdf",
  abstract =     "Until version 4.2.1, GNU MP (GMP for short) division
                 has complexity O(M(n) log n), which is not
                 asymptotically optimal. We propose here some division
                 algorithms that achieve O(M(n)) with small constants.",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Zimmermann:2006:EBC
author: Paul Zimmermann and Richard Brent and Colin Percival
title: Errors Bounds on Complex Floating-Point Multiplication
type: Technical report
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
year: 2006
bibdate: Sun Sep 10 07:21:42 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.10 07:21:42 ???
URL: http://www.loria.fr/~zimmerma/papers/index.html
acknowledgement: ack-nhfb
rawauthor: Paul Zimmermann and Richard Brent and Colin Percival
rawtitle: Errors Bounds on Complex Floating-Point Multiplication
abstract:
Given floating-point arithmetic with $t$-digit base-$ beta $ significands in which all arithmetic operations are performed as if calculated to infinite precision and rounded to a nearest representable value, we prove that the product of complex values $ z_0 $ and $ z_1 $ can be computed with maximum absolute error $ |z_0 | |z_1 | (1 / 2) beta ^1 - t sqrt 5 $. In particular, this provides relative error bounds of $ 2 - 24 sqrt 5 $ and $ 2 - 53 sqrt 5 $ for IEEE 754 single and double precision arithmetic respectively, provided that overflow, underflow, and denormals do not occur. We also provide the numerical worst cases for IEEE 754 single and double precision arithmetic.

rawabstract:
Given floating-point arithmetic with $t$-digit base-$ \beta $ significands in which all arithmetic operations are performed as if calculated to infinite precision and rounded to a nearest representable value, we prove that the product of complex values $ z_0 $ and $ z_1 $ can be computed with maximum absolute error $ |z_0 | |z_1 | (1 / 2) \beta^{1 - t} \sqrt {5} $. In particular, this provides relative error bounds of $ {2 - 24} \sqrt {5} $ and $ {2 - 53} \sqrt {5} $ for IEEE 754 single and double precision arithmetic respectively, provided that overflow, underflow, and denormals do not occur. We also provide the numerical worst cases for IEEE 754 single and double precision arithmetic.

entry:
@TechReport{Zimmermann:2006:EBC,
  author =       "Paul Zimmermann and Richard Brent and Colin Percival",
  title =        "Errors Bounds on Complex Floating-Point
                 Multiplication",
  type =         "Technical report",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  pages =        "????",
  year =         "2006",
  bibdate =      "Sun Sep 10 07:21:42 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.loria.fr/~zimmerma/papers/index.html",
  abstract =     "Given floating-point arithmetic with $t$-digit base-$
                 \beta $ significands in which all arithmetic operations
                 are performed as if calculated to infinite precision
                 and rounded to a nearest representable value, we prove
                 that the product of complex values $ z_0 $ and $ z_1 $
                 can be computed with maximum absolute error $ |z_0 |
                 |z_1 | (1 / 2) \beta^{1 - t} \sqrt {5} $. In
                 particular, this provides relative error bounds of $ {2
                 - 24} \sqrt {5} $ and $ {2 - 53} \sqrt {5} $ for IEEE
                 754 single and double precision arithmetic
                 respectively, provided that overflow, underflow, and
                 denormals do not occur. We also provide the numerical
                 worst cases for IEEE 754 single and double precision
                 arithmetic.",
  acknowledgement = ack-nhfb,
  xxnote =       "Check author order?? Paper not yet online.",
}


bibtype: misc
filename: fparith.bib
label: Zimmermann:2006:WC
author: Paul Zimmermann
title: Worst Cases for $ sin (hbox BIG) $
day: 2
month: nov
monthnumber: 11
year: 2006
bibdate: Wed Nov 15 07:56:07 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.11.15 07:56:07 ???
URL: http://www.loria.fr/~zimmerma/talks/sinbig.pdf
acknowledgement: ack-nhfb
howpublished: World-Wide Web slides.
rawauthor: Paul Zimmermann
rawtitle: Worst Cases for $ \sin (\hbox {BIG}) $
entry:
@Misc{Zimmermann:2006:WC,
  author =       "Paul Zimmermann",
  title =        "Worst Cases for $ \sin (\hbox {BIG}) $",
  howpublished = "World-Wide Web slides.",
  day =          "2",
  month =        nov,
  year =         "2006",
  bibdate =      "Wed Nov 15 07:56:07 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.loria.fr/~zimmerma/talks/sinbig.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Zimmermann:2006:YE
author: Paul Zimmermann and Bruce Dodson
title: 20 Years of ECM
crossref: Hess:2006:ANT
pages: 525--541
year: 2006
DOI: https://doi.org/10.1007/11792086_37
bibdate: Mon May 31 12:31:07 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.05.31 12:31:07 ???
URL: https://members.loria.fr/PZimmermann/papers/40760525.pdf
keywords: assembly code; elliptic curve; Fermat number; modular multiplication; quadratic domain
acknowledgement: ack-nhfb
rawauthor: Paul Zimmermann and Bruce Dodson
rawtitle: 20 Years of {ECM}
abstract:
The Elliptic Curve Method for integer factorization (ECM) was invented by H. W. Lenstra, Jr., in 1985 [14]. In the past 20 years, many improvements of ECM were proposed on the mathematical, algorithmic, and implementation sides. This paper summarizes the current state-of-the-art, as implemented in the GMP-ECM software.

rawabstract:
The Elliptic Curve Method for integer factorization (ECM) was invented by H. W. Lenstra, Jr., in 1985 [14]. In the past 20 years, many improvements of ECM were proposed on the mathematical, algorithmic, and implementation sides. This paper summarizes the current state-of-the-art, as implemented in the GMP-ECM software.

entry:
@InProceedings{Zimmermann:2006:YE,
  author =       "Paul Zimmermann and Bruce Dodson",
  title =        "20 Years of {ECM}",
  crossref =     "Hess:2006:ANT",
  pages =        "525--541",
  year =         "2006",
  DOI =          "https://doi.org/10.1007/11792086_37",
  bibdate =      "Mon May 31 12:31:07 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://members.loria.fr/PZimmermann/papers/40760525.pdf",
  abstract =     "The Elliptic Curve Method for integer factorization
                 (ECM) was invented by H. W. Lenstra, Jr., in 1985 [14].
                 In the past 20 years, many improvements of ECM were
                 proposed on the mathematical, algorithmic, and
                 implementation sides. This paper summarizes the current
                 state-of-the-art, as implemented in the GMP-ECM
                 software.",
  acknowledgement = ack-nhfb,
  keywords =     "assembly code; elliptic curve; Fermat number; modular
                 multiplication; quadratic domain",
}


